Fix incorrect types in testbenches

Author: ablomm

cpu/testbenches/alu_tb.sv

@@ -6,7 +6,7 @@ module alu_tb;
   logic carry_in;
   logic [31:0] a, b;
   wire [31:0] out;
-  wire [ 3:0] status;
+  alu_status_t status;
 
   alu alu0 (.*);
 

cpu/testbenches/cu_tb.sv

@@ -14,7 +14,7 @@ module cu_tb;
   logic wr;
 
   logic oe_alu;
-  logic [3:0] alu_op;
+  alu_op_e alu_op;
 
   reg_mask_e a_reg_mask;
   reg_mask_e b_reg_mask;

cpu/testbenches/status_reg_tb.sv

@@ -3,8 +3,8 @@ import reg_pkg::*;
 module status_reg_tb;
   logic clk;
   logic rst = 0;
-  tri [5:0] a, b;
-  logic [5:0] in;
+  tri status_t a, b;
+  status_t in;
   logic oe_a, oe_b, ld;
   alu_status_t alu_status_in;
   logic ld_alu_status;