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20.4.0.00013 (#9)
* 20.4.0.00013 * commit targetdb, version 20.4.0.00013 --------- Co-authored-by: GitHub Action <action@github.com>
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‎.github/workflows/build.yml‎

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REGISTRY: ghcr.io
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IMAGE_NAME: ccstudio
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MAJOR_VER: 20
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MINOR_VER: 3
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PATCH_VER: 1
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BUILD_VER: "00005"
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MINOR_VER: 4
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PATCH_VER: 0
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BUILD_VER: "00013"
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COMPONENTS: PF_SITARA_MCU,PF_ARM_MPU,PF_C28,PF_C6000SC,PF_HERCULES,PF_MMWAVE,PF_MSP430,PF_MSPM0,PF_MSPM33,PF_OMAPL,PF_PGA,PF_MSP432,PF_AUTO,PF_TM4C,PF_DIGITAL_POWER,PF_WCONN
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jobs:

‎targetdb/Modules/C2000/f28p551x_access_protection_regs.xml‎

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<module id="ACCESS_PROTECTION_REGS" HW_revision="" description="ACCESS PROTECTION Registers">
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<register id="NMAVFLG" width="32" page="1" offset="0x0" internal="0" description="Non-Controller Access Violation Flag Register">
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<bitfield id="CPUREAD" description="Non Controller CPU Read Access Violation Flag" begin="0" end="0" width="1" rwaccess="R"/>
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<bitfield id="CPUWRITE" description="Non Controller CPU Write Access Violation Flag" begin="1" end="1" width="1" rwaccess="R"/>
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<bitfield id="CPUFETCH" description="Non Controller CPU Fetch Access Violation Flag" begin="2" end="2" width="1" rwaccess="R"/>
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<bitfield id="DMAWRITE" description="Non Controller DMA Write Access Violation Flag" begin="3" end="3" width="1" rwaccess="R"/>
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<bitfield id="CLA1READ" description="Non Controller CLA1 Read Access Violation Flag" begin="4" end="4" width="1" rwaccess="R"/>
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<bitfield id="CLA1WRITE" description="Non Controller CLA1 Write Access Violation Flag" begin="5" end="5" width="1" rwaccess="R"/>
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<bitfield id="CLA1FETCH" description="Non Controller CLA1 Fetch Access Violation Flag" begin="6" end="6" width="1" rwaccess="R"/>
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<bitfield id="DMAREAD" description="Non Controller DMA Read Access Violation Flag" begin="10" end="10" width="1" rwaccess="R"/>
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<bitfield id="NPUREAD" description="Non Controller NPU Read Access Violation Flag" begin="11" end="11" width="1" rwaccess="R"/>
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<bitfield id="NPUWRITE" description="Non Controller NPU Write Violation Flag" begin="12" end="12" width="1" rwaccess="R"/>
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</register>
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<register id="NMAVSET" width="32" page="1" offset="0x2" internal="0" description="Non-Controller Access Violation Flag Set Register">
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<bitfield id="CPUREAD" description="Non Controller CPU Read Access Violation Flag Set" begin="0" end="0" width="1" rwaccess="RW"/>
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<bitfield id="CPUWRITE" description="Non Controller CPU Write Access Violation Flag Set" begin="1" end="1" width="1" rwaccess="RW"/>
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<bitfield id="CPUFETCH" description="Non Controller CPU Fetch Access Violation Flag Set" begin="2" end="2" width="1" rwaccess="RW"/>
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<bitfield id="DMAWRITE" description="Non Controller DMA Write Access Violation Flag Set" begin="3" end="3" width="1" rwaccess="RW"/>
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<bitfield id="CLA1READ" description="Non Controller CLA1 Read Access Violation Flag Set" begin="4" end="4" width="1" rwaccess="RW"/>
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<bitfield id="CLA1WRITE" description="Non Controller CLA1 Write Access Violation Flag Set" begin="5" end="5" width="1" rwaccess="RW"/>
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<bitfield id="CLA1FETCH" description="Non Controller CLA1 Fetch Access Violation Flag Set" begin="6" end="6" width="1" rwaccess="RW"/>
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<bitfield id="DMAREAD" description="Non Controller DMA Read Access Violation Flag Set" begin="10" end="10" width="1" rwaccess="RW"/>
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<bitfield id="NPUREAD" description="Non Controller NPU Read Access Violation Flag Set" begin="11" end="11" width="1" rwaccess="RW"/>
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<bitfield id="NPUWRITE" description="Non Controller NPU Write Access Violation Flag Set" begin="12" end="12" width="1" rwaccess="RW"/>
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</register>
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<register id="NMAVCLR" width="32" page="1" offset="0x4" internal="0" description="Non-Controller Access Violation Flag Clear Register">
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<bitfield id="CPUREAD" description="Non Controller CPU Read Access Violation Flag Clear " begin="0" end="0" width="1" rwaccess="RW"/>
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<bitfield id="CPUWRITE" description="Non Controller CPU Write Access Violation Flag Clear " begin="1" end="1" width="1" rwaccess="RW"/>
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<bitfield id="CPUFETCH" description="Non Controller CPU Fetch Access Violation Flag Clear " begin="2" end="2" width="1" rwaccess="RW"/>
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<bitfield id="DMAWRITE" description="Non Controller DMA Write Access Violation Flag Clear " begin="3" end="3" width="1" rwaccess="RW"/>
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<bitfield id="CLA1READ" description="Non Controller CLA1 Read Access Violation Flag Clear " begin="4" end="4" width="1" rwaccess="RW"/>
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<bitfield id="CLA1WRITE" description="Non Controller CLA1 Write Access Violation Flag Clear " begin="5" end="5" width="1" rwaccess="RW"/>
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<bitfield id="CLA1FETCH" description="Non Controller CLA1 Fetch Access Violation Flag Clear " begin="6" end="6" width="1" rwaccess="RW"/>
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<bitfield id="DMAREAD" description="Non Controller DMA Read Access Violation Flag Clear " begin="10" end="10" width="1" rwaccess="RW"/>
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<bitfield id="NPUREAD" description="Non Controller NPU Read Access Violation Flag Clear " begin="11" end="11" width="1" rwaccess="RW"/>
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<bitfield id="NPUWRITE" description="Non Controller NPU Write Access Violation Flag Clear " begin="12" end="12" width="1" rwaccess="RW"/>
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</register>
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<register id="NMAVINTEN" width="32" page="1" offset="0x6" internal="0" description="Non-Controller Access Violation Interrupt Enable Register">
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<bitfield id="CPUREAD" description="Non Controller CPU Read Access Violation Interrupt Enable " begin="0" end="0" width="1" rwaccess="RW"/>
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<bitfield id="CPUWRITE" description="Non Controller CPU Write Access Violation Interrupt Enable " begin="1" end="1" width="1" rwaccess="RW"/>
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<bitfield id="CPUFETCH" description="Non Controller CPU Fetch Access Violation Interrupt Enable " begin="2" end="2" width="1" rwaccess="RW"/>
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<bitfield id="DMAWRITE" description="Non Controller DMA Write Access Violation Interrupt Enable " begin="3" end="3" width="1" rwaccess="RW"/>
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<bitfield id="CLA1READ" description="Non Controller CLA1 Read Access Violation Interrupt Enable " begin="4" end="4" width="1" rwaccess="RW"/>
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<bitfield id="CLA1WRITE" description="Non Controller CLA1 Write Access Violation Interrupt Enable " begin="5" end="5" width="1" rwaccess="RW"/>
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<bitfield id="CLA1FETCH" description="Non Controller CLA1 Fetch Access Violation Interrupt Enable " begin="6" end="6" width="1" rwaccess="RW"/>
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<bitfield id="DMAREAD" description="Non Controller DMA Read Access Violation Interrupt Enable " begin="10" end="10" width="1" rwaccess="RW"/>
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<bitfield id="NPUREAD" description="Non Controller NPU Read Access Violation Interrupt Enable " begin="11" end="11" width="1" rwaccess="RW"/>
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<bitfield id="NPUWRITE" description="Non Controller NPU Write Violation Interrupt Enable " begin="12" end="12" width="1" rwaccess="RW"/>
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</register>
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<register id="NMCPURDAVADDR" width="32" page="1" offset="0x8" internal="0" description="Non-Controller CPU Read Access Violation Address">
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<bitfield id="NMCPURDAVADDR" description="Non Controller CPU read access violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
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</register>
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<register id="NMCPUWRAVADDR" width="32" page="1" offset="0xa" internal="0" description="Non-Controller CPU Write Access Violation Address">
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<bitfield id="NMCPUWRAVADDR" description="Non Controller CPU write access violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
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</register>
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<register id="NMCPUFAVADDR" width="32" page="1" offset="0xc" internal="0" description="Non-Controller CPU Fetch Access Violation Address">
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<bitfield id="NMCPUFAVADDR" description="Non Controller CPU fetch access violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
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</register>
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<register id="NMDMAWRAVADDR" width="32" page="1" offset="0xe" internal="0" description="Non-Controller DMA Write Access Violation Address">
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<bitfield id="NMDMAWRAVADDR" description="Non Controller DMA write access violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
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</register>
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<register id="NMCLA1RDAVADDR" width="32" page="1" offset="0x10" internal="0" description="Non-Controller CLA1 Read Access Violation Address">
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<bitfield id="NMCLA1RDAVADDR" description="Non Controller CLA1 read access violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
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</register>
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<register id="NMCLA1WRAVADDR" width="32" page="1" offset="0x12" internal="0" description="Non-Controller CLA1 Write Access Violation Address">
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<bitfield id="NMCLA1WRAVADDR" description="Non Controller CLA1 write violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
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</register>
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<register id="NMCLA1FAVADDR" width="32" page="1" offset="0x14" internal="0" description="Non-Controller CLA1 Fetch Access Violation Address">
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<bitfield id="NMCLA1FAVADDR" description="Non Controller CLA1 fetch violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
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</register>
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<register id="NMDMARDAVADDR" width="32" page="1" offset="0x1c" internal="0" description="Non-Controller DMA Read Access Violation Address">
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<bitfield id="NMDMARDAVADDR" description="Non Controller DMA read access violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
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</register>
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<register id="MAVFLG" width="32" page="1" offset="0x20" internal="0" description="Controller Access Violation Flag Register">
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<bitfield id="CPUFETCH" description="Controller CPU Fetch Access Violation Flag" begin="0" end="0" width="1" rwaccess="R"/>
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<bitfield id="CPUWRITE" description="Controller CPU Write Access Violation Flag" begin="1" end="1" width="1" rwaccess="R"/>
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<bitfield id="DMAWRITE" description="Controller DMA Write Access Violation Flag" begin="2" end="2" width="1" rwaccess="R"/>
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</register>
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<register id="MAVSET" width="32" page="1" offset="0x22" internal="0" description="Controller Access Violation Flag Set Register">
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<bitfield id="CPUFETCH" description="Controller CPU Fetch Access Violation Flag Set" begin="0" end="0" width="1" rwaccess="RW"/>
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<bitfield id="CPUWRITE" description="Controller CPU Write Access Violation Flag Set" begin="1" end="1" width="1" rwaccess="RW"/>
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<bitfield id="DMAWRITE" description="Controller DMA Write Access Violation Flag Set" begin="2" end="2" width="1" rwaccess="RW"/>
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</register>
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<register id="MAVCLR" width="32" page="1" offset="0x24" internal="0" description="Controller Access Violation Flag Clear Register">
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<bitfield id="CPUFETCH" description="Controller CPU Fetch Access Violation Flag Clear " begin="0" end="0" width="1" rwaccess="RW"/>
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<bitfield id="CPUWRITE" description="Controller CPU Write Access Violation Flag Clear " begin="1" end="1" width="1" rwaccess="RW"/>
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<bitfield id="DMAWRITE" description="Controller DMA Write Access Violation Flag Clear " begin="2" end="2" width="1" rwaccess="RW"/>
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</register>
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<register id="MAVINTEN" width="32" page="1" offset="0x26" internal="0" description="Controller Access Violation Interrupt Enable Register">
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<bitfield id="CPUFETCH" description="Controller CPU Fetch Access Violation Interrupt Enable " begin="0" end="0" width="1" rwaccess="RW"/>
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<bitfield id="CPUWRITE" description="Controller CPU Write Access Violation Interrupt Enable " begin="1" end="1" width="1" rwaccess="RW"/>
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<bitfield id="DMAWRITE" description="Controller DMA Write Access Violation Interrupt Enable " begin="2" end="2" width="1" rwaccess="RW"/>
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</register>
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<register id="MCPUFAVADDR" width="32" page="1" offset="0x28" internal="0" description="Controller CPU Fetch Access Violation Address">
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<bitfield id="MCPUFAVADDR" description="Controller CPU fetch access violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
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</register>
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<register id="MCPUWRAVADDR" width="32" page="1" offset="0x2a" internal="0" description="Controller CPU Write Access Violation Address">
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<bitfield id="MCPUWRAVADDR" description="Controller CPU write access violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
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</register>
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<register id="MDMAWRAVADDR" width="32" page="1" offset="0x2c" internal="0" description="Controller DMA Write Access Violation Address">
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<bitfield id="MDMAWRAVADDR" description="Controller DMA write access violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
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</register>
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<register id="NMNPURDAVADDR" width="32" page="1" offset="0x3a" internal="0" description="Non-Controller NPU Read Access Violation Address">
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<bitfield id="NMNPURDAVADDR" description="Non Controller NPU read violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
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</register>
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<register id="NMNPUWRAVADDR" width="32" page="1" offset="0x3c" internal="0" description="Non-Controller NPU Write Access Violation Address">
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<bitfield id="NMNPUWRAVADDR" description="Non Controller NPU write violation address register. " begin="31" end="0" width="32" rwaccess="R"/>
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</register>
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</module>

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