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Question regarding Clocking Wizard IP reset type in “SDSoC Platform Creation Labs > Lab 1” #23

@peter2chang

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@peter2chang

In lab1 step2 (create an IP Integrator Design), Clocking Wizard IP’s reset type is set to active low. Is it because the Zynq7 SoC is used? Should I need to set reset type to Low for all my projects that use Zynq7 in the future? Thanks in advance!

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