Upstream update available: designs/src/vortex/dev/repo

[claude]

Upstream update available: vortex

Field	Value
Pinned	31e4765d (2025-10-19)
Upstream	d425a56e (2026-05-11)
Commits behind	86
Days stale	204

Severity: major

Justification: Range adds a new on-chip debug subsystem (DebugModule + JTAG DTM + remote-bitbang server for OpenOCD/GDB integration), a substantial SST + openMPI integration (and openMPI-paradigm benchmarks), an AXI Burst-mode fix (Fixed → Incr) for Vivado SmartConnect, TF32 support in tensor compute, and a simx source-tree restructure for submodule support. CI/toolchain pinning was also overhauled (vortex-toolchain-prebuilt v2.3, centralized VERSION file). DebugModule is RTL-affecting; TF32 and AXI burst-mode are likely to shift area/timing of the HighTide vortex/asap7 variant.

What changed (highlights)

• Debug subsystem — new DebugModule + JTAG DTM for RISC-V; remote bitbang server for OpenOCD; emulator integration (register reads, PC init, halt state, final-PC notification); 64-bit support for register/memory access; variable-byte memory access; MISA CSR read fix for GDB ELF loading; comprehensive debug-mode guide (docs/debug_mode.md); cfg port 9824 → 9823 (Single-Hart). Refactor in 9b5e664 "refactor(dtm): relocate debug stack, drop unrelated TF32, add coverage".
• SST + openMPI integration — initial design-redesign; libvortex.so for SST; openMPI for Vortex SIMX; SST cycle-interface fixes; SST scripts/config-path updates; apptainer CI; centralized SST sources after install (space savings).
• TF32 support — added in tensor compute and tracing.
• AXI Burst-mode fix — switch from Fixed to Incr for Vivado SmartConnect (#297).
• simx restructure — source-tree reorganized to support submodules.
• HDL fixes — vx_spawn fix; data race in bss; srai decode fix; local mem fix in simx; __assert → __vortex_assert rename; RAM::copy memmove direction fix + device-match check.
• MPI / regression — gate mpi_* regression tests behind MPI=1; relax mpi_blocked_sgemm ULP tolerance for Cannon's algorithm; CI MPI test coverage added.
• CI / toolchain — fix toolchain scripts for new Verilator + add sta tool; pin toolchain downloads to vortex-toolchain-prebuilt v2.3; centralize version pins in VERSION file; verilator download enhanced for Ubuntu Focal; remove Ubuntu 22.04 from supported OS; GITHUB_PATH fix; cache-size config examples in README.
• Docs — microarchitecture.md update; debug-mode README enhancements; platforms.mk U50 update.
• Misc — copybuf added; srai test; PR-regression fixes; build fixes; centralized version pins.

Recommendation

Defer + plan — the debug subsystem touches the core's CSR + memory interfaces and is RTL-relevant; expect non-trivial timing/area changes on the asap7 variant. Before bumping, verify the yosys-slang phantom-driver workaround (#304, our cb488bea) is still needed and that the 6 stub-RAM configs (192x16/193x16/85x16/87x16/560x4/654x4) still match. The simx restructure may require RTL-list updates in HighTide's designs/src/vortex/dev/repo filegroup.

---

Last refreshed: 2026-05-18T10:27Z