FakeRAM2.0/example_input_file.cfg at main · VLSIDA/FakeRAM2.0 · GitHub

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#SAMPLE INPUT FILE; VALUES NOT REALISTIC
{
  # The process node.
  "tech_nm": 7,

  # The operating voltage.
  "voltage": 0.7,

  # String to add in front of every metal layer number for the layer name.
  "metal_prefix": "M",

  # Horizontal Metal layer for macro pins
  "metal_layer": "M4",

  # The pin width for signal pins.
  "pin_width_nm": 24,

  # The minimum pin pitch for signal pins
  "pin_pitch_nm": 48,

  # Metal track pitch
  "metal_track_pitch_nm": 48,

  # Manufacturing Grid
  "manufacturing_grid_nm": 1,

  # Contacted Poly Pitch
  "contacted_poly_pitch_nm": 54,

  #column mux factor
  "column_mux_factor": 1,

  # Fin pitch
  "fin_pitch_nm" : 27,

  # Optional snap the width and height of the sram to a multiple value.
  "snap_width_nm":  190,
  "snap_height_nm": 1400,

  # List of SRAM configurations (name width depth and banks)
  "srams": [
    {"name": "testram_1rw_32w384d_4_sram",
     "width": 32,
     "depth": 384,
     "banks": 1,
     "write_mode": "write_first",
     "write_granularity": 4,
     "r": 0,
     "w": 0,
     "rw": [1, "left"]
    },
    {"name": "testram_1r_16w128d_8_sram",
     "width": 16,
     "depth": 128,
     "banks": 1,
     "write_mode": "read_first",
     "write_granularity": 8,
     "r": [1, "right"],
     "w": 0,
     "rw": 0
    },
    {"name": "testram_1w_64w256d_16_sram",
     "width": 64,
     "depth": 256,
     "banks": 1,
     "write_mode": "write_first",
     "write_granularity": 16,
     "r": 0,
     "w": [1, "left"],
     "rw": 0
    },
    {"name": "testram_2rw_32w1024d_sram",
     "width": 32,
     "depth": 1024,
     "banks": 1,
     "write_mode": "read_first",
     "r": 0,
     "w": 0,
     "rw": [2, "right"]
    },
    {"name": "testram_1r1w_8w64d_4_sram",
     "width": 8,
     "depth": 64,
     "banks": 1,
     "write_mode": "write_first",
     "write_granularity": 4,
     "r": [1, "left"],
     "w": [1, "right"],
     "rw": 0
    }
  ]

  # TENTATIVE PARAMETERS
}