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TimRudyTimRudy
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Improve .ice component sizing, layout, pin names
1 parent 0d559b6 commit a805332

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4 files changed

+676
-619
lines changed

4 files changed

+676
-619
lines changed

‎ice/UART-BG.ice‎

Lines changed: 121 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -11,44 +11,96 @@
1111
"board": "icezum",
1212
"graph": {
1313
"blocks": [
14+
{
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"id": "01c30fd4-6162-425e-9af0-2f40273021fa",
16+
"type": "basic.output",
17+
"data": {
18+
"name": "",
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"virtual": true
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},
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"position": {
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"x": 1056,
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"y": 24
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}
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},
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{
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"id": "aef86b17-5dea-4001-9cce-0fc7f1c58c33",
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"type": "basic.output",
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"data": {
18-
"name": "rxClk"
30+
"name": "rxClk",
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"virtual": true
1932
},
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"position": {
21-
"x": 816,
22-
"y": 96
34+
"x": 1056,
35+
"y": 144
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}
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},
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{
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"id": "c2df35e2-6b64-4b6b-b29b-9d66b6115158",
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"type": "basic.output",
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"data": {
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"name": "",
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"virtual": true
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},
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"position": {
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"x": 1056,
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"y": 264
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}
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},
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{
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"id": "5fb29465-2ee7-45bb-afa4-9a3de895c774",
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"type": "basic.input",
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"data": {
29-
"name": "clk"
54+
"name": "clk",
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"virtual": true,
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"clock": true
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},
58+
"position": {
59+
"x": 40,
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"y": 328
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}
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},
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{
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"id": "531f63ad-0c27-425d-82de-96e038bf38ec",
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"type": "basic.output",
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"data": {
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"name": "",
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"virtual": true
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},
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"position": {
32-
"x": 32,
33-
"y": 216
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"x": 1056,
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"y": 384
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}
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},
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{
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"id": "49ed377b-71f0-4d1b-a73b-62a59341ca8b",
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"type": "basic.output",
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"data": {
40-
"name": "txClk"
79+
"name": "txClk",
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"virtual": true
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},
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"position": {
43-
"x": 816,
44-
"y": 336
83+
"x": 1056,
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"y": 504
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}
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},
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{
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"id": "0a0ab721-9757-4d4f-8e2e-3a88705e9b4a",
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"type": "basic.output",
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"data": {
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"name": "",
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"virtual": true
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},
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"position": {
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"x": 1056,
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"y": 624
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}
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},
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{
48100
"id": "ba573190-2ead-411a-a323-1b15a22d46db",
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"type": "basic.code",
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"data": {
51-
"code": "/*\n * Baud rate generator to divide {CLOCK_RATE} (internal system clock) into\n * {BAUD_RATE} tx/rx pair, with rx oversample by default 16x\n */\n\nparameter CLOCK_RATE = 100000000;\nparameter BAUD_RATE = 9600;\nparameter RX_OVERSAMPLE_RATE = 16;\n\nlocalparam RX_ACC_MAX = CLOCK_RATE / (2 * BAUD_RATE * RX_OVERSAMPLE_RATE);\nlocalparam TX_ACC_MAX = CLOCK_RATE / (2 * BAUD_RATE);\nlocalparam RX_ACC_WIDTH = $clog2(RX_ACC_MAX);\nlocalparam TX_ACC_WIDTH = $clog2(TX_ACC_MAX);\n\nwire clk;\nreg rxClk;\nreg txClk;\n\nreg [RX_ACC_WIDTH-1:0] rx_counter = 0;\nreg [TX_ACC_WIDTH-1:0] tx_counter = 0;\n\ninitial begin\n rxClk = 1'b0;\n txClk = 1'b0;\nend\n\nalways @(posedge clk) begin\n // rx clock\n if (rx_counter == RX_ACC_MAX[RX_ACC_WIDTH-1:0]) begin\n rx_counter <= 0;\n rxClk <= ~rxClk;\n end else begin\n rx_counter <= rx_counter + 1'b1;\n end\n\n // tx clock\n if (tx_counter == TX_ACC_MAX[TX_ACC_WIDTH-1:0]) begin\n tx_counter <= 0;\n txClk <= ~txClk;\n end else begin\n tx_counter <= tx_counter + 1'b1;\n end\nend\n\nassign clk = pin1_clk;\nassign pin8_rxClk = rxClk;\nassign pin9_txClk = txClk;\n",
103+
"code": "/*\n * Baud rate generator to divide {CLOCK_RATE} (internal system clock) into\n * {BAUD_RATE} tx/rx pair, with rx oversample by default 16x\n */\n\nparameter CLOCK_RATE = 100000000;\nparameter BAUD_RATE = 9600;\nparameter RX_OVERSAMPLE_RATE = 16;\n\nlocalparam RX_ACC_MAX = CLOCK_RATE / (2 * BAUD_RATE * RX_OVERSAMPLE_RATE);\nlocalparam TX_ACC_MAX = CLOCK_RATE / (2 * BAUD_RATE);\nlocalparam RX_ACC_WIDTH = $clog2(RX_ACC_MAX);\nlocalparam TX_ACC_WIDTH = $clog2(TX_ACC_MAX);\n\nwire clk;\nreg rxClk;\nreg txClk;\n\nreg [RX_ACC_WIDTH-1:0] rx_counter = 0;\nreg [TX_ACC_WIDTH-1:0] tx_counter = 0;\n\ninitial begin\n rxClk = 1'b0;\n txClk = 1'b0;\nend\n\nalways @(posedge clk) begin\n // rx clock\n if (rx_counter == RX_ACC_MAX[RX_ACC_WIDTH-1:0]) begin\n rx_counter <= 0;\n rxClk <= ~rxClk;\n end else begin\n rx_counter <= rx_counter + 1'b1;\n end\n\n // tx clock\n if (tx_counter == TX_ACC_MAX[TX_ACC_WIDTH-1:0]) begin\n tx_counter <= 0;\n txClk <= ~txClk;\n end else begin\n tx_counter <= tx_counter + 1'b1;\n end\nend\n\nassign clk = pin1_clk;\nassign pin3_rxClk = rxClk;\nassign pin6_txClk = txClk;\n",
52104
"params": [],
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"ports": {
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"in": [
@@ -58,21 +110,33 @@
58110
],
59111
"out": [
60112
{
61-
"name": "pin8_rxClk"
113+
"name": "pin2_NC"
114+
},
115+
{
116+
"name": "pin3_rxClk"
117+
},
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{
119+
"name": "pin4_NC"
120+
},
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{
122+
"name": "pin5_NC"
62123
},
63124
{
64-
"name": "pin9_txClk"
125+
"name": "pin6_txClk"
126+
},
127+
{
128+
"name": "pin7_NC"
65129
}
66130
]
67131
}
68132
},
69133
"position": {
70134
"x": 280,
71-
"y": 8
135+
"y": 0
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},
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"size": {
74-
"width": 388,
75-
"height": 480
138+
"width": 636,
139+
"height": 712
76140
}
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}
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],
@@ -90,7 +154,17 @@
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{
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"source": {
92156
"block": "ba573190-2ead-411a-a323-1b15a22d46db",
93-
"port": "pin8_rxClk"
157+
"port": "pin2_NC"
158+
},
159+
"target": {
160+
"block": "01c30fd4-6162-425e-9af0-2f40273021fa",
161+
"port": "in"
162+
}
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},
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{
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"source": {
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"block": "ba573190-2ead-411a-a323-1b15a22d46db",
167+
"port": "pin3_rxClk"
94168
},
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"target": {
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"block": "aef86b17-5dea-4001-9cce-0fc7f1c58c33",
@@ -100,12 +174,42 @@
100174
{
101175
"source": {
102176
"block": "ba573190-2ead-411a-a323-1b15a22d46db",
103-
"port": "pin9_txClk"
177+
"port": "pin4_NC"
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},
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"target": {
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"block": "c2df35e2-6b64-4b6b-b29b-9d66b6115158",
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"port": "in"
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}
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},
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{
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"source": {
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"block": "ba573190-2ead-411a-a323-1b15a22d46db",
187+
"port": "pin5_NC"
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},
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"target": {
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"block": "531f63ad-0c27-425d-82de-96e038bf38ec",
191+
"port": "in"
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}
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},
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{
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"source": {
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"block": "ba573190-2ead-411a-a323-1b15a22d46db",
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"port": "pin6_txClk"
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},
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"target": {
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"block": "49ed377b-71f0-4d1b-a73b-62a59341ca8b",
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"port": "in"
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}
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},
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{
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"source": {
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"block": "ba573190-2ead-411a-a323-1b15a22d46db",
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"port": "pin7_NC"
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},
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"target": {
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"block": "0a0ab721-9757-4d4f-8e2e-3a88705e9b4a",
211+
"port": "in"
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}
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}
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]
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}

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