Reads to PPUSTATUS within the first three cycles of vertical blanking will cause special case behaviour in original hardware due to a race condition between the CPU and PPU clock rates. Reading at (0, 241) will read bit 7 as clear and prevent it from being set. Reading at (1, 241) or (2, 241) will read and clear bit 7 correctly. All three of these cases will prevent the CPU from observing a PPU NMI. Some games rely on this behavior, and so it must be emulated.
Reads to PPUSTATUS within the first three cycles of vertical blanking will cause special case behaviour in original hardware due to a race condition between the CPU and PPU clock rates. Reading at (0, 241) will read bit 7 as clear and prevent it from being set. Reading at (1, 241) or (2, 241) will read and clear bit 7 correctly. All three of these cases will prevent the CPU from observing a PPU NMI. Some games rely on this behavior, and so it must be emulated.