From 4ad1599a88b56cdb6022806ef93ef9ccc3fd4f7f Mon Sep 17 00:00:00 2001
From: Jeff Ng <jeffng@precisioninno.com>
Date: Fri, 18 Jul 2025 15:08:13 +0000
Subject: [PATCH] dual port sram from spreadsheet support

Signed-off-by: Jeff Ng <jeffng@precisioninno.com>
---
 spreadsheet_ram.py                     |   93 +-
 test/au/ss_dpsram_128x64.au            | 4226 ++++++++++++++++++++++++
 test/cfg/ss_dpsram_128x64_physical.csv |  311 ++
 test/cfg/ss_metrics.csv                |    2 +-
 test/dpsram_ss_flow_test.py            |   40 +
 utils/lef_exporter.py                  |   28 +-
 utils/liberty_exporter.py              |   45 +-
 utils/rw_port_group.py                 |    8 +
 utils/ss_port_organizer.py             |  106 +
 utils/verilog_exporter.py              |   77 +-
 10 files changed, 4812 insertions(+), 124 deletions(-)
 create mode 100644 test/au/ss_dpsram_128x64.au
 create mode 100644 test/cfg/ss_dpsram_128x64_physical.csv
 create mode 100755 test/dpsram_ss_flow_test.py
 create mode 100644 utils/ss_port_organizer.py

diff --git a/spreadsheet_ram.py b/spreadsheet_ram.py
index 939cd22..53a32cc 100755
--- a/spreadsheet_ram.py
+++ b/spreadsheet_ram.py
@@ -12,10 +12,10 @@
 from utils.run_utils import RunUtils
 from utils.rw_port_group import RWPortGroup
 from utils.ss_port_creator import SSPortCreator
+from utils.ss_port_organizer import SSPortOrganizer
 from utils.single_port_ssram import SinglePortSSRAM
 
 # TODO
-# support dual port
 # support reg file
 
 #
@@ -103,22 +103,13 @@ def _import_custom_mappings(self, file_name):
         self._pin_type_map = self._util_module.get_pin_type_map()
         self._key_map = self._util_module.get_key_map()
 
-    def classify_pin(self, pin_name):
-        """
-        Returns the pin classification to help identify whether the pin or bus
-        is the address, data in, data out, write enable, clock or power pin or
-        bus
-        """
-        if pin_name in self._pin_type_map:
-            return self._pin_type_map[pin_name]
-        return None
-
     def create_memory(self, mem_config, physical):
         """Extracts the data from the CSV files and returns the memory object"""
 
         # Get the physical data and organize it
         phys_data = self.read_physical_file(physical)
-        pins = self.organize_pins(phys_data)
+        pin_org = SSPortOrganizer(self._pin_type_map)
+        pin_org.organize_ports(phys_data)
         num_pins = len(phys_data["pin_data"])
 
         # Get the metrics data and organize it
@@ -127,7 +118,7 @@ def create_memory(self, mem_config, physical):
         mem_config = MemoryConfig.from_json(macro_metrics)
 
         mem = SinglePortSSRAM(mem_config, self._process, timing_data, num_pins)
-        self.set_logical_pins(mem, pins)
+        self.set_logical_pins(mem, pin_org)
         port_creator = SSPortCreator(mem, self._pin_type_map)
         port_creator.create_ports(phys_data["pin_data"])
         if "obs" in phys_data:
@@ -194,36 +185,6 @@ def read_physical_file(self, file_name):
                     )
         return macro_data
 
-    def organize_pins(self, macro_data):
-        """
-        Iterates through the macro_data and creates a pin dictionary that
-        maps the pin or bus name to a dictionary that includes the pin name,
-        msb, lsb, and type
-        """
-
-        pins = {}
-        bus_name_re = re.compile("^(\S+)\[(\d+)\]")
-        for pin_name, pin_data in macro_data["pin_data"].items():
-            result = bus_name_re.match(pin_name)
-            if result:
-                bus_name = result.group(1)
-                bit_num = int(result.group(2))
-                if bus_name in pins:
-                    pins[bus_name]["lsb"] = min(bit_num, pins[bus_name]["lsb"])
-                    pins[bus_name]["msb"] = max(bit_num, pins[bus_name]["msb"])
-                else:
-                    pins[bus_name] = {
-                        "name": bus_name,
-                        "msb": bit_num,
-                        "lsb": bit_num,
-                        "type": self.classify_pin(bus_name),
-                    }
-            else:
-                if pin_name in pins: # pragma: no cover
-                    raise Exception(f"pin {pin_name} appears twice")
-                pins[pin_name] = {"name": pin_name, "type": self.classify_pin(pin_name)}
-
-        return pins
 
     def get_size_keys(self):
         """Returns the keys that map to depth and width"""
@@ -270,30 +231,30 @@ def read_metrics_file(self, file_name, macro_name):
                             )
         return macro_metrics
 
-    def set_logical_pins(self, mem, pins):
+    def set_logical_pins(self, mem, pin_org):
         """Sets the pins to be used for Verilog and Liberty output"""
-        rw_port_group = RWPortGroup()
-        mem.add_rw_port_group(rw_port_group)
-        for pin_name, pin_data in pins.items():
-            pin_type = pin_data["type"]
-            if pin_type == "clock":
-                rw_port_group.set_clock_name(pin_name)
-            elif pin_type in ["power", "ground"]:
-                # skip
-                pass
-            elif pin_type == "address_bus":
-                rw_port_group.set_address_bus_name(pin_name)
-            elif pin_type == "data_bus":
-                rw_port_group.set_data_input_bus_name(pin_name)
-            elif pin_type == "output_bus":
-                rw_port_group.set_data_output_bus_name(pin_name)
-            elif pin_type == "write_enable":
-                rw_port_group.set_write_enable_name(pin_name)
-            elif "msb" in pin_data:
-                bus = {"name": pin_name, "msb": pin_data["msb"], "lsb": pin_data["lsb"]}
-                mem.add_misc_bus(bus)
-            else:
-                mem.add_misc_port(pin_name)
+
+        for suffix,src in pin_org.get_rw_groups().items():
+            rw_port_group = RWPortGroup()
+            rw_port_group.set_suffix(suffix)
+            for pin_type,port_data in src.items():
+                pin_name = port_data["name"]
+                if pin_type == "clock":
+                    rw_port_group.set_clock_name(pin_name)
+                elif pin_type == "address_bus":
+                    rw_port_group.set_address_bus_name(pin_name)
+                elif pin_type == "data_bus":
+                    rw_port_group.set_data_input_bus_name(pin_name)
+                elif pin_type == "output_bus":
+                    rw_port_group.set_data_output_bus_name(pin_name)
+                elif pin_type == "write_enable":
+                    rw_port_group.set_write_enable_name(pin_name)
+            mem.add_rw_port_group(rw_port_group)
+        for src in pin_org.get_misc_busses():
+            mem.add_misc_bus(src)
+        for src in pin_org.get_misc_ports():
+            if src["type"] not in ["power", "ground"]:
+                mem.add_misc_port(src["name"])
 
     @staticmethod
     def main():
diff --git a/test/au/ss_dpsram_128x64.au b/test/au/ss_dpsram_128x64.au
new file mode 100644
index 0000000..dbf86ae
--- /dev/null
+++ b/test/au/ss_dpsram_128x64.au
@@ -0,0 +1,4226 @@
+# Generated by FakeRAM 2.0
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+PROPERTYDEFINITIONS
+  MACRO width INTEGER ;
+  MACRO depth INTEGER ;
+  MACRO banks INTEGER ;
+END PROPERTYDEFINITIONS
+MACRO ss_dpsram_128x64
+  PROPERTY width 64 ;
+  PROPERTY depth 128 ;
+  PROPERTY banks 8 ;
+  FOREIGN ss_dpsram_128x64 0 0 ;
+  SYMMETRY X Y R90 ;
+  SIZE 49.500 BY 200.050 ;
+  CLASS BLOCK ;
+  PIN clk_b
+    DIRECTION INPUT ;
+    USE CLOCK ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 106.914 19.620 107.548 ;
+    END
+  END clk_b
+  PIN addr_a[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 20.370 102.870 20.410 103.504 ;
+    END
+  END addr_a[0]
+  PIN addr_a[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 20.510 102.790 20.530 103.424 ;
+    END
+  END addr_a[1]
+  PIN addr_a[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 20.100 103.384 20.260 104.018 ;
+    END
+  END addr_a[2]
+  PIN addr_a[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 20.370 103.544 20.410 104.178 ;
+    END
+  END addr_a[3]
+  PIN addr_a[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 20.510 103.464 20.530 104.098 ;
+    END
+  END addr_a[4]
+  PIN addr_a[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 20.640 103.384 20.660 104.018 ;
+    END
+  END addr_a[5]
+  PIN addr_a[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 102.870 19.620 103.504 ;
+    END
+  END addr_a[6]
+  PIN addr_a[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 102.790 19.743 103.424 ;
+    END
+  END addr_a[7]
+  PIN addr_a[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.810 102.710 19.860 103.344 ;
+    END
+  END addr_a[8]
+  PIN addr_b[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 20.100 102.790 20.140 103.424 ;
+    END
+  END addr_b[0]
+  PIN addr_b[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 20.100 102.710 20.260 103.344 ;
+    END
+  END addr_b[1]
+  PIN addr_b[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 20.370 104.218 20.410 104.852 ;
+    END
+  END addr_b[2]
+  PIN addr_b[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 20.510 104.138 20.530 104.772 ;
+    END
+  END addr_b[3]
+  PIN addr_b[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 20.640 104.058 20.660 104.692 ;
+    END
+  END addr_b[4]
+  PIN addr_b[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 103.544 19.620 104.178 ;
+    END
+  END addr_b[5]
+  PIN addr_b[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 103.464 19.743 104.098 ;
+    END
+  END addr_b[6]
+  PIN addr_b[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.810 103.384 19.860 104.018 ;
+    END
+  END addr_b[7]
+  PIN addr_b[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.820 103.544 20.020 104.178 ;
+    END
+  END addr_b[8]
+  PIN din_a[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 208.344 19.620 208.978 ;
+    END
+  END din_a[0]
+  PIN din_a[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 206.895 19.620 207.529 ;
+    END
+  END din_a[1]
+  PIN din_a[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 205.446 19.620 206.080 ;
+    END
+  END din_a[2]
+  PIN din_a[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 203.997 19.620 204.631 ;
+    END
+  END din_a[3]
+  PIN din_a[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 202.548 19.620 203.182 ;
+    END
+  END din_a[4]
+  PIN din_a[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 201.099 19.620 201.733 ;
+    END
+  END din_a[5]
+  PIN din_a[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 199.650 19.620 200.284 ;
+    END
+  END din_a[6]
+  PIN din_a[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 198.201 19.620 198.835 ;
+    END
+  END din_a[7]
+  PIN din_a[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 196.752 19.620 197.386 ;
+    END
+  END din_a[8]
+  PIN din_a[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 195.303 19.620 195.937 ;
+    END
+  END din_a[9]
+  PIN din_a[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 193.854 19.620 194.488 ;
+    END
+  END din_a[10]
+  PIN din_a[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 192.405 19.620 193.039 ;
+    END
+  END din_a[11]
+  PIN din_a[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 190.956 19.620 191.590 ;
+    END
+  END din_a[12]
+  PIN din_a[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 189.507 19.620 190.141 ;
+    END
+  END din_a[13]
+  PIN din_a[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 188.058 19.620 188.692 ;
+    END
+  END din_a[14]
+  PIN din_a[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 186.609 19.620 187.243 ;
+    END
+  END din_a[15]
+  PIN din_a[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 185.160 19.620 185.794 ;
+    END
+  END din_a[16]
+  PIN din_a[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 183.711 19.620 184.345 ;
+    END
+  END din_a[17]
+  PIN din_a[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 182.262 19.620 182.896 ;
+    END
+  END din_a[18]
+  PIN din_a[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 180.813 19.620 181.447 ;
+    END
+  END din_a[19]
+  PIN din_a[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 179.364 19.620 179.998 ;
+    END
+  END din_a[20]
+  PIN din_a[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 177.915 19.620 178.549 ;
+    END
+  END din_a[21]
+  PIN din_a[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 176.466 19.620 177.100 ;
+    END
+  END din_a[22]
+  PIN din_a[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 175.017 19.620 175.651 ;
+    END
+  END din_a[23]
+  PIN din_a[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 173.568 19.620 174.202 ;
+    END
+  END din_a[24]
+  PIN din_a[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 172.119 19.620 172.753 ;
+    END
+  END din_a[25]
+  PIN din_a[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 170.670 19.620 171.304 ;
+    END
+  END din_a[26]
+  PIN din_a[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 169.221 19.620 169.855 ;
+    END
+  END din_a[27]
+  PIN din_a[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 167.772 19.620 168.406 ;
+    END
+  END din_a[28]
+  PIN din_a[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 166.323 19.620 166.957 ;
+    END
+  END din_a[29]
+  PIN din_a[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 164.874 19.620 165.508 ;
+    END
+  END din_a[30]
+  PIN din_a[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 163.425 19.620 164.059 ;
+    END
+  END din_a[31]
+  PIN din_a[32]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 156.824 19.620 157.458 ;
+    END
+  END din_a[32]
+  PIN din_a[33]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 155.375 19.620 156.009 ;
+    END
+  END din_a[33]
+  PIN din_a[34]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 153.926 19.620 154.560 ;
+    END
+  END din_a[34]
+  PIN din_a[35]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 152.477 19.620 153.111 ;
+    END
+  END din_a[35]
+  PIN din_a[36]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 151.028 19.620 151.662 ;
+    END
+  END din_a[36]
+  PIN din_a[37]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 149.579 19.620 150.213 ;
+    END
+  END din_a[37]
+  PIN din_a[38]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 148.130 19.620 148.764 ;
+    END
+  END din_a[38]
+  PIN din_a[39]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 146.681 19.620 147.315 ;
+    END
+  END din_a[39]
+  PIN din_a[40]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 145.232 19.620 145.866 ;
+    END
+  END din_a[40]
+  PIN din_a[41]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 143.783 19.620 144.417 ;
+    END
+  END din_a[41]
+  PIN din_a[42]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 142.334 19.620 142.968 ;
+    END
+  END din_a[42]
+  PIN din_a[43]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 140.885 19.620 141.519 ;
+    END
+  END din_a[43]
+  PIN din_a[44]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 139.436 19.620 140.070 ;
+    END
+  END din_a[44]
+  PIN din_a[45]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 137.987 19.620 138.621 ;
+    END
+  END din_a[45]
+  PIN din_a[46]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 136.538 19.620 137.172 ;
+    END
+  END din_a[46]
+  PIN din_a[47]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 135.089 19.620 135.723 ;
+    END
+  END din_a[47]
+  PIN din_a[48]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 133.640 19.620 134.274 ;
+    END
+  END din_a[48]
+  PIN din_a[49]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 132.191 19.620 132.825 ;
+    END
+  END din_a[49]
+  PIN din_a[50]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 130.742 19.620 131.376 ;
+    END
+  END din_a[50]
+  PIN din_a[51]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 129.293 19.620 129.927 ;
+    END
+  END din_a[51]
+  PIN din_a[52]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 127.844 19.620 128.478 ;
+    END
+  END din_a[52]
+  PIN din_a[53]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 126.395 19.620 127.029 ;
+    END
+  END din_a[53]
+  PIN din_a[54]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 124.946 19.620 125.580 ;
+    END
+  END din_a[54]
+  PIN din_a[55]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 123.497 19.620 124.131 ;
+    END
+  END din_a[55]
+  PIN din_a[56]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 122.048 19.620 122.682 ;
+    END
+  END din_a[56]
+  PIN din_a[57]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 120.599 19.620 121.233 ;
+    END
+  END din_a[57]
+  PIN din_a[58]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 119.150 19.620 119.784 ;
+    END
+  END din_a[58]
+  PIN din_a[59]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 117.701 19.620 118.335 ;
+    END
+  END din_a[59]
+  PIN din_a[60]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 116.252 19.620 116.886 ;
+    END
+  END din_a[60]
+  PIN din_a[61]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 114.803 19.620 115.437 ;
+    END
+  END din_a[61]
+  PIN din_a[62]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 113.354 19.620 113.988 ;
+    END
+  END din_a[62]
+  PIN din_a[63]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 111.905 19.620 112.539 ;
+    END
+  END din_a[63]
+  PIN din_a[64]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 98.542 19.620 99.176 ;
+    END
+  END din_a[64]
+  PIN din_a[65]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 97.093 19.620 97.727 ;
+    END
+  END din_a[65]
+  PIN din_a[66]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 95.644 19.620 96.278 ;
+    END
+  END din_a[66]
+  PIN din_a[67]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 94.195 19.620 94.829 ;
+    END
+  END din_a[67]
+  PIN din_a[68]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 92.746 19.620 93.380 ;
+    END
+  END din_a[68]
+  PIN din_a[69]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 91.297 19.620 91.931 ;
+    END
+  END din_a[69]
+  PIN din_a[70]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 89.848 19.620 90.482 ;
+    END
+  END din_a[70]
+  PIN din_a[71]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 88.399 19.620 89.033 ;
+    END
+  END din_a[71]
+  PIN din_a[72]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 86.950 19.620 87.584 ;
+    END
+  END din_a[72]
+  PIN din_a[73]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 85.501 19.620 86.135 ;
+    END
+  END din_a[73]
+  PIN din_a[74]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 84.052 19.620 84.686 ;
+    END
+  END din_a[74]
+  PIN din_a[75]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 82.603 19.620 83.237 ;
+    END
+  END din_a[75]
+  PIN din_a[76]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 81.154 19.620 81.788 ;
+    END
+  END din_a[76]
+  PIN din_a[77]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 79.705 19.620 80.339 ;
+    END
+  END din_a[77]
+  PIN din_a[78]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 78.256 19.620 78.890 ;
+    END
+  END din_a[78]
+  PIN din_a[79]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 76.807 19.620 77.441 ;
+    END
+  END din_a[79]
+  PIN din_a[80]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 75.358 19.620 75.992 ;
+    END
+  END din_a[80]
+  PIN din_a[81]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 73.909 19.620 74.543 ;
+    END
+  END din_a[81]
+  PIN din_a[82]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 72.460 19.620 73.094 ;
+    END
+  END din_a[82]
+  PIN din_a[83]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 71.011 19.620 71.645 ;
+    END
+  END din_a[83]
+  PIN din_a[84]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 69.562 19.620 70.196 ;
+    END
+  END din_a[84]
+  PIN din_a[85]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 68.113 19.620 68.747 ;
+    END
+  END din_a[85]
+  PIN din_a[86]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 66.664 19.620 67.298 ;
+    END
+  END din_a[86]
+  PIN din_a[87]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 65.215 19.620 65.849 ;
+    END
+  END din_a[87]
+  PIN din_a[88]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 63.766 19.620 64.400 ;
+    END
+  END din_a[88]
+  PIN din_a[89]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 62.317 19.620 62.951 ;
+    END
+  END din_a[89]
+  PIN din_a[90]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 60.868 19.620 61.502 ;
+    END
+  END din_a[90]
+  PIN din_a[91]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 59.419 19.620 60.053 ;
+    END
+  END din_a[91]
+  PIN din_a[92]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 57.970 19.620 58.604 ;
+    END
+  END din_a[92]
+  PIN din_a[93]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 56.521 19.620 57.155 ;
+    END
+  END din_a[93]
+  PIN din_a[94]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 55.072 19.620 55.706 ;
+    END
+  END din_a[94]
+  PIN din_a[95]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 53.623 19.620 54.257 ;
+    END
+  END din_a[95]
+  PIN din_a[96]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 47.022 19.620 47.656 ;
+    END
+  END din_a[96]
+  PIN din_a[97]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 45.573 19.620 46.207 ;
+    END
+  END din_a[97]
+  PIN din_a[98]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 44.124 19.620 44.758 ;
+    END
+  END din_a[98]
+  PIN din_a[99]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 42.675 19.620 43.309 ;
+    END
+  END din_a[99]
+  PIN din_a[100]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 41.226 19.620 41.860 ;
+    END
+  END din_a[100]
+  PIN din_a[101]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 39.777 19.620 40.411 ;
+    END
+  END din_a[101]
+  PIN din_a[102]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 38.328 19.620 38.962 ;
+    END
+  END din_a[102]
+  PIN din_a[103]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 36.879 19.620 37.513 ;
+    END
+  END din_a[103]
+  PIN din_a[104]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 35.430 19.620 36.064 ;
+    END
+  END din_a[104]
+  PIN din_a[105]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 33.981 19.620 34.615 ;
+    END
+  END din_a[105]
+  PIN din_a[106]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 32.532 19.620 33.166 ;
+    END
+  END din_a[106]
+  PIN din_a[107]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 31.083 19.620 31.717 ;
+    END
+  END din_a[107]
+  PIN din_a[108]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 29.634 19.620 30.268 ;
+    END
+  END din_a[108]
+  PIN din_a[109]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 28.185 19.620 28.819 ;
+    END
+  END din_a[109]
+  PIN din_a[110]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 26.736 19.620 27.370 ;
+    END
+  END din_a[110]
+  PIN din_a[111]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 25.287 19.620 25.921 ;
+    END
+  END din_a[111]
+  PIN din_a[112]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 23.838 19.620 24.472 ;
+    END
+  END din_a[112]
+  PIN din_a[113]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 22.389 19.620 23.023 ;
+    END
+  END din_a[113]
+  PIN din_a[114]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 20.940 19.620 21.574 ;
+    END
+  END din_a[114]
+  PIN din_a[115]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 19.491 19.620 20.125 ;
+    END
+  END din_a[115]
+  PIN din_a[116]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 18.042 19.620 18.676 ;
+    END
+  END din_a[116]
+  PIN din_a[117]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 16.593 19.620 17.227 ;
+    END
+  END din_a[117]
+  PIN din_a[118]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 15.144 19.620 15.778 ;
+    END
+  END din_a[118]
+  PIN din_a[119]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 13.695 19.620 14.329 ;
+    END
+  END din_a[119]
+  PIN din_a[120]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 12.246 19.620 12.880 ;
+    END
+  END din_a[120]
+  PIN din_a[121]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 10.797 19.620 11.431 ;
+    END
+  END din_a[121]
+  PIN din_a[122]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 9.348 19.620 9.982 ;
+    END
+  END din_a[122]
+  PIN din_a[123]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 7.899 19.620 8.533 ;
+    END
+  END din_a[123]
+  PIN din_a[124]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 6.450 19.620 7.084 ;
+    END
+  END din_a[124]
+  PIN din_a[125]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 5.001 19.620 5.635 ;
+    END
+  END din_a[125]
+  PIN din_a[126]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 3.552 19.620 4.186 ;
+    END
+  END din_a[126]
+  PIN din_a[127]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 2.103 19.620 2.737 ;
+    END
+  END din_a[127]
+  PIN dout_b[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 208.264 19.740 208.898 ;
+    END
+  END dout_b[0]
+  PIN dout_b[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 206.815 19.740 207.449 ;
+    END
+  END dout_b[1]
+  PIN dout_b[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 205.366 19.740 206.000 ;
+    END
+  END dout_b[2]
+  PIN dout_b[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 203.917 19.740 204.551 ;
+    END
+  END dout_b[3]
+  PIN dout_b[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 202.468 19.740 203.102 ;
+    END
+  END dout_b[4]
+  PIN dout_b[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 201.019 19.740 201.653 ;
+    END
+  END dout_b[5]
+  PIN dout_b[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 199.570 19.740 200.204 ;
+    END
+  END dout_b[6]
+  PIN dout_b[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 198.121 19.740 198.755 ;
+    END
+  END dout_b[7]
+  PIN dout_b[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 196.672 19.740 197.306 ;
+    END
+  END dout_b[8]
+  PIN dout_b[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 195.223 19.740 195.857 ;
+    END
+  END dout_b[9]
+  PIN dout_b[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 193.774 19.740 194.408 ;
+    END
+  END dout_b[10]
+  PIN dout_b[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 192.325 19.740 192.959 ;
+    END
+  END dout_b[11]
+  PIN dout_b[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 190.876 19.740 191.510 ;
+    END
+  END dout_b[12]
+  PIN dout_b[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 189.427 19.740 190.061 ;
+    END
+  END dout_b[13]
+  PIN dout_b[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 187.978 19.740 188.612 ;
+    END
+  END dout_b[14]
+  PIN dout_b[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 186.529 19.740 187.163 ;
+    END
+  END dout_b[15]
+  PIN dout_b[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 185.080 19.740 185.714 ;
+    END
+  END dout_b[16]
+  PIN dout_b[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 183.631 19.740 184.265 ;
+    END
+  END dout_b[17]
+  PIN dout_b[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 182.182 19.740 182.816 ;
+    END
+  END dout_b[18]
+  PIN dout_b[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 180.733 19.740 181.367 ;
+    END
+  END dout_b[19]
+  PIN dout_b[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 179.284 19.740 179.918 ;
+    END
+  END dout_b[20]
+  PIN dout_b[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 177.835 19.740 178.469 ;
+    END
+  END dout_b[21]
+  PIN dout_b[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 176.386 19.740 177.020 ;
+    END
+  END dout_b[22]
+  PIN dout_b[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 174.937 19.740 175.571 ;
+    END
+  END dout_b[23]
+  PIN dout_b[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 173.488 19.740 174.122 ;
+    END
+  END dout_b[24]
+  PIN dout_b[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 172.039 19.740 172.673 ;
+    END
+  END dout_b[25]
+  PIN dout_b[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 170.590 19.740 171.224 ;
+    END
+  END dout_b[26]
+  PIN dout_b[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 169.141 19.740 169.775 ;
+    END
+  END dout_b[27]
+  PIN dout_b[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 167.692 19.740 168.326 ;
+    END
+  END dout_b[28]
+  PIN dout_b[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 166.243 19.740 166.877 ;
+    END
+  END dout_b[29]
+  PIN dout_b[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 164.794 19.740 165.428 ;
+    END
+  END dout_b[30]
+  PIN dout_b[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 163.345 19.740 163.979 ;
+    END
+  END dout_b[31]
+  PIN dout_b[32]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 156.744 19.740 157.378 ;
+    END
+  END dout_b[32]
+  PIN dout_b[33]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 155.295 19.740 155.929 ;
+    END
+  END dout_b[33]
+  PIN dout_b[34]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 153.846 19.740 154.480 ;
+    END
+  END dout_b[34]
+  PIN dout_b[35]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 152.397 19.740 153.031 ;
+    END
+  END dout_b[35]
+  PIN dout_b[36]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 150.948 19.740 151.582 ;
+    END
+  END dout_b[36]
+  PIN dout_b[37]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 149.499 19.740 150.133 ;
+    END
+  END dout_b[37]
+  PIN dout_b[38]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 148.050 19.740 148.684 ;
+    END
+  END dout_b[38]
+  PIN dout_b[39]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 146.601 19.740 147.235 ;
+    END
+  END dout_b[39]
+  PIN dout_b[40]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 145.152 19.740 145.786 ;
+    END
+  END dout_b[40]
+  PIN dout_b[41]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 143.703 19.740 144.337 ;
+    END
+  END dout_b[41]
+  PIN dout_b[42]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 142.254 19.740 142.888 ;
+    END
+  END dout_b[42]
+  PIN dout_b[43]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 140.805 19.740 141.439 ;
+    END
+  END dout_b[43]
+  PIN dout_b[44]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 139.356 19.740 139.990 ;
+    END
+  END dout_b[44]
+  PIN dout_b[45]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 137.907 19.740 138.541 ;
+    END
+  END dout_b[45]
+  PIN dout_b[46]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 136.458 19.740 137.092 ;
+    END
+  END dout_b[46]
+  PIN dout_b[47]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 135.009 19.740 135.643 ;
+    END
+  END dout_b[47]
+  PIN dout_b[48]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 133.560 19.740 134.194 ;
+    END
+  END dout_b[48]
+  PIN dout_b[49]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 132.111 19.740 132.745 ;
+    END
+  END dout_b[49]
+  PIN dout_b[50]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 130.662 19.740 131.296 ;
+    END
+  END dout_b[50]
+  PIN dout_b[51]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 129.213 19.740 129.847 ;
+    END
+  END dout_b[51]
+  PIN dout_b[52]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 127.764 19.740 128.398 ;
+    END
+  END dout_b[52]
+  PIN dout_b[53]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 126.315 19.740 126.949 ;
+    END
+  END dout_b[53]
+  PIN dout_b[54]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 124.866 19.740 125.500 ;
+    END
+  END dout_b[54]
+  PIN dout_b[55]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 123.417 19.740 124.051 ;
+    END
+  END dout_b[55]
+  PIN dout_b[56]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 121.968 19.740 122.602 ;
+    END
+  END dout_b[56]
+  PIN dout_b[57]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 120.519 19.740 121.153 ;
+    END
+  END dout_b[57]
+  PIN dout_b[58]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 119.070 19.740 119.704 ;
+    END
+  END dout_b[58]
+  PIN dout_b[59]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 117.621 19.740 118.255 ;
+    END
+  END dout_b[59]
+  PIN dout_b[60]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 116.172 19.740 116.806 ;
+    END
+  END dout_b[60]
+  PIN dout_b[61]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 114.723 19.740 115.357 ;
+    END
+  END dout_b[61]
+  PIN dout_b[62]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 113.274 19.740 113.908 ;
+    END
+  END dout_b[62]
+  PIN dout_b[63]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 111.825 19.740 112.459 ;
+    END
+  END dout_b[63]
+  PIN dout_b[64]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 98.462 19.740 99.096 ;
+    END
+  END dout_b[64]
+  PIN dout_b[65]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 97.013 19.740 97.647 ;
+    END
+  END dout_b[65]
+  PIN dout_b[66]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 95.564 19.740 96.198 ;
+    END
+  END dout_b[66]
+  PIN dout_b[67]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 94.115 19.740 94.749 ;
+    END
+  END dout_b[67]
+  PIN dout_b[68]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 92.666 19.740 93.300 ;
+    END
+  END dout_b[68]
+  PIN dout_b[69]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 91.217 19.740 91.851 ;
+    END
+  END dout_b[69]
+  PIN dout_b[70]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 89.768 19.740 90.402 ;
+    END
+  END dout_b[70]
+  PIN dout_b[71]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 88.319 19.740 88.953 ;
+    END
+  END dout_b[71]
+  PIN dout_b[72]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 86.870 19.740 87.504 ;
+    END
+  END dout_b[72]
+  PIN dout_b[73]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 85.421 19.740 86.055 ;
+    END
+  END dout_b[73]
+  PIN dout_b[74]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 83.972 19.740 84.606 ;
+    END
+  END dout_b[74]
+  PIN dout_b[75]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 82.523 19.740 83.157 ;
+    END
+  END dout_b[75]
+  PIN dout_b[76]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 81.074 19.740 81.708 ;
+    END
+  END dout_b[76]
+  PIN dout_b[77]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 79.625 19.740 80.259 ;
+    END
+  END dout_b[77]
+  PIN dout_b[78]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 78.176 19.740 78.810 ;
+    END
+  END dout_b[78]
+  PIN dout_b[79]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 76.727 19.740 77.361 ;
+    END
+  END dout_b[79]
+  PIN dout_b[80]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 75.278 19.740 75.912 ;
+    END
+  END dout_b[80]
+  PIN dout_b[81]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 73.829 19.740 74.463 ;
+    END
+  END dout_b[81]
+  PIN dout_b[82]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 72.380 19.740 73.014 ;
+    END
+  END dout_b[82]
+  PIN dout_b[83]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 70.931 19.740 71.565 ;
+    END
+  END dout_b[83]
+  PIN dout_b[84]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 69.482 19.740 70.116 ;
+    END
+  END dout_b[84]
+  PIN dout_b[85]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 68.033 19.740 68.667 ;
+    END
+  END dout_b[85]
+  PIN dout_b[86]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 66.584 19.740 67.218 ;
+    END
+  END dout_b[86]
+  PIN dout_b[87]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 65.135 19.740 65.769 ;
+    END
+  END dout_b[87]
+  PIN dout_b[88]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 63.686 19.740 64.320 ;
+    END
+  END dout_b[88]
+  PIN dout_b[89]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 62.237 19.740 62.871 ;
+    END
+  END dout_b[89]
+  PIN dout_b[90]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 60.788 19.740 61.422 ;
+    END
+  END dout_b[90]
+  PIN dout_b[91]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 59.339 19.740 59.973 ;
+    END
+  END dout_b[91]
+  PIN dout_b[92]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 57.890 19.740 58.524 ;
+    END
+  END dout_b[92]
+  PIN dout_b[93]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 56.441 19.740 57.075 ;
+    END
+  END dout_b[93]
+  PIN dout_b[94]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 54.992 19.740 55.626 ;
+    END
+  END dout_b[94]
+  PIN dout_b[95]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 53.543 19.740 54.177 ;
+    END
+  END dout_b[95]
+  PIN dout_b[96]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 46.942 19.740 47.576 ;
+    END
+  END dout_b[96]
+  PIN dout_b[97]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 45.493 19.740 46.127 ;
+    END
+  END dout_b[97]
+  PIN dout_b[98]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 44.044 19.740 44.678 ;
+    END
+  END dout_b[98]
+  PIN dout_b[99]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 42.595 19.740 43.229 ;
+    END
+  END dout_b[99]
+  PIN dout_b[100]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 41.146 19.740 41.780 ;
+    END
+  END dout_b[100]
+  PIN dout_b[101]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 39.697 19.740 40.331 ;
+    END
+  END dout_b[101]
+  PIN dout_b[102]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 38.248 19.740 38.882 ;
+    END
+  END dout_b[102]
+  PIN dout_b[103]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 36.799 19.740 37.433 ;
+    END
+  END dout_b[103]
+  PIN dout_b[104]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 35.350 19.740 35.984 ;
+    END
+  END dout_b[104]
+  PIN dout_b[105]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 33.901 19.740 34.535 ;
+    END
+  END dout_b[105]
+  PIN dout_b[106]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 32.452 19.740 33.086 ;
+    END
+  END dout_b[106]
+  PIN dout_b[107]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 31.003 19.740 31.637 ;
+    END
+  END dout_b[107]
+  PIN dout_b[108]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 29.554 19.740 30.188 ;
+    END
+  END dout_b[108]
+  PIN dout_b[109]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 28.105 19.740 28.739 ;
+    END
+  END dout_b[109]
+  PIN dout_b[110]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 26.656 19.740 27.290 ;
+    END
+  END dout_b[110]
+  PIN dout_b[111]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 25.207 19.740 25.841 ;
+    END
+  END dout_b[111]
+  PIN dout_b[112]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 23.758 19.740 24.392 ;
+    END
+  END dout_b[112]
+  PIN dout_b[113]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 22.309 19.740 22.943 ;
+    END
+  END dout_b[113]
+  PIN dout_b[114]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 20.860 19.740 21.494 ;
+    END
+  END dout_b[114]
+  PIN dout_b[115]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 19.411 19.740 20.045 ;
+    END
+  END dout_b[115]
+  PIN dout_b[116]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 17.962 19.740 18.596 ;
+    END
+  END dout_b[116]
+  PIN dout_b[117]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 16.513 19.740 17.147 ;
+    END
+  END dout_b[117]
+  PIN dout_b[118]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 15.064 19.740 15.698 ;
+    END
+  END dout_b[118]
+  PIN dout_b[119]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 13.615 19.740 14.249 ;
+    END
+  END dout_b[119]
+  PIN dout_b[120]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 12.166 19.740 12.800 ;
+    END
+  END dout_b[120]
+  PIN dout_b[121]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 10.717 19.740 11.351 ;
+    END
+  END dout_b[121]
+  PIN dout_b[122]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 9.268 19.740 9.902 ;
+    END
+  END dout_b[122]
+  PIN dout_b[123]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 7.819 19.740 8.453 ;
+    END
+  END dout_b[123]
+  PIN dout_b[124]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 6.370 19.740 7.004 ;
+    END
+  END dout_b[124]
+  PIN dout_b[125]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 4.921 19.740 5.555 ;
+    END
+  END dout_b[125]
+  PIN dout_b[126]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 3.472 19.740 4.106 ;
+    END
+  END dout_b[126]
+  PIN dout_b[127]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 2.023 19.740 2.657 ;
+    END
+  END dout_b[127]
+  PIN rm_a[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 20.370 105.566 20.410 106.200 ;
+    END
+  END rm_a[0]
+  PIN rm_a[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 20.510 105.486 20.530 106.120 ;
+    END
+  END rm_a[1]
+  PIN rm_a[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 20.640 105.406 20.660 106.040 ;
+    END
+  END rm_a[2]
+  PIN rm_a[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 104.892 19.610 105.526 ;
+    END
+  END rm_a[3]
+  PIN rm_b[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.810 105.406 19.860 106.040 ;
+    END
+  END rm_b[0]
+  PIN rm_b[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.820 105.566 20.020 106.200 ;
+    END
+  END rm_b[1]
+  PIN rm_b[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 20.100 105.486 20.140 106.120 ;
+    END
+  END rm_b[2]
+  PIN rm_b[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 20.100 105.406 20.260 106.040 ;
+    END
+  END rm_b[3]
+  PIN a_off
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 102.044 19.620 102.678 ;
+    END
+  END a_off
+  PIN ds_i
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 20.100 106.834 20.140 107.468 ;
+    END
+  END ds_i
+  PIN ls_
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.820 106.240 20.020 106.874 ;
+    END
+  END ls_
+  PIN me_a
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 20.100 106.080 20.260 106.714 ;
+    END
+  END me_a
+  PIN me_b
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 20.100 106.160 20.140 106.794 ;
+    END
+  END me_b
+  PIN p_off
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 101.964 19.740 102.598 ;
+    END
+  END p_off
+  PIN rme_a
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 105.486 19.740 106.120 ;
+    END
+  END rme_a
+  PIN rme_bb
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 105.566 19.610 106.200 ;
+    END
+  END rme_bb
+  PIN rop_ds
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.550 0.654 19.610 1.288 ;
+    END
+  END rop_ds
+  PIN rop_sd
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 0.574 19.740 1.208 ;
+    END
+  END rop_sd
+  PIN sd
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 104.812 19.740 105.446 ;
+    END
+  END sd
+  PIN test1_a
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.820 104.892 20.015 105.526 ;
+    END
+  END test1_a
+  PIN test1_b
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.810 104.732 19.860 105.366 ;
+    END
+  END test1_b
+  PIN test_rnm_a
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 20.100 104.812 20.146 105.446 ;
+    END
+  END test_rnm_a
+  PIN tpr_a
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 20.370 104.892 20.410 105.526 ;
+    END
+  END tpr_a
+  PIN tpr_b
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 20.100 104.732 20.260 105.366 ;
+    END
+  END tpr_b
+  PIN we_a
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M6 ;
+      RECT 19.650 104.138 19.740 104.772 ;
+    END
+  END we_a
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER M5 ;
+      RECT 0.000 209.976 19.552 210.030 ;
+    END
+  END VDD
+  PIN VDDA
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER M5 ;
+      RECT 0.000 210.164 19.552 210.218 ;
+    END
+  END VDDA
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER M5 ;
+      RECT 0.000 210.070 19.552 210.124 ;
+    END
+  END VSS
+  OBS
+    LAYER M1 ;
+    RECT -0.108 -0.108 46.593 210.374 ;
+    LAYER M2 ;
+    RECT -0.07 -0.07 46.555 210.336 ;
+    LAYER M3 ;
+    RECT -0.06 -0.06 46.545 210.326 ;
+    LAYER M4 ;
+    RECT -0.087 -0.087 46.572 210.353 ;
+    LAYER M5 ;
+    RECT -0.087 -0.087 46.572 210.353 ;
+    LAYER M6 ;
+    RECT 19.2025 -0.26 21.253 210.526 ;
+  END
+END ss_dpsram_128x64
+
+END LIBRARY
+(* blackbox *)
+module ss_dpsram_128x64 (
+    input clk_b,
+    input [8:0] addr_a,
+    input [8:0] addr_b,
+    input [127:0] din_a,
+    input [127:0] dout_b,
+    input [3:0] rm_a,
+    input [3:0] rm_b,
+    input a_off,
+    input ds_i,
+    input ls_,
+    input me_a,
+    input me_b,
+    input p_off,
+    input rme_a,
+    input rme_bb,
+    input rop_ds,
+    input rop_sd,
+    input sd,
+    input test1_a,
+    input test1_b,
+    input test_rnm_a,
+    input tpr_a,
+    input tpr_b,
+    input we_a
+);
+endmodule
+(* blackbox *)
+module ss_dpsram_128x64 (
+    input clk_b,
+    input [8:0] addr_a,
+    input [8:0] addr_b,
+    input [127:0] din_a,
+    input [127:0] dout_b,
+    input [3:0] rm_a,
+    input [3:0] rm_b,
+    input a_off,
+    input ds_i,
+    input ls_,
+    input me_a,
+    input me_b,
+    input p_off,
+    input rme_a,
+    input rme_bb,
+    input rop_ds,
+    input rop_sd,
+    input sd,
+    input test1_a,
+    input test1_b,
+    input test_rnm_a,
+    input tpr_a,
+    input tpr_b,
+    input we_a
+);
+endmodule
+library(ss_dpsram_128x64) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 0.7;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 0.7;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.227;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(ss_dpsram_128x64_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(ss_dpsram_128x64_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(ss_dpsram_128x64_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(ss_dpsram_128x64_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(ss_dpsram_128x64_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (ss_dpsram_128x64_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 64;
+        bit_from : 63;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (ss_dpsram_128x64_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 7;
+        bit_from : 6;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (ss_dpsram_128x64_addr_a) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 9;
+        bit_from : 8;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (ss_dpsram_128x64_addr_b) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 9;
+        bit_from : 8;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (ss_dpsram_128x64_din_a) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 128;
+        bit_from : 127;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (ss_dpsram_128x64_dout_b) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 128;
+        bit_from : 127;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (ss_dpsram_128x64_rm_a) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 4;
+        bit_from : 3;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (ss_dpsram_128x64_rm_b) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 4;
+        bit_from : 3;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(ss_dpsram_128x64) {
+    area : 9902.475;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 7;
+        word_width : 64;
+    }
+    pin(clk_b)   {
+        direction : input;
+        capacitance : 0.005;
+        clock : true;
+        min_period           : 0.456 ;
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("2.150, 2.150")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("2.150, 2.150")
+            }
+        }
+    }
+
+    bus(addr_a)   {
+        bus_type : ss_dpsram_128x64_addr_a;
+        direction : input;
+        capacitance : 0.001;
+        timing() {
+            related_pin : clk_b;
+            timing_type : setup_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+        }
+        timing() {
+            related_pin : clk_b;
+            timing_type : hold_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+        }
+    }
+    bus(addr_b)   {
+        bus_type : ss_dpsram_128x64_addr_b;
+        direction : input;
+        capacitance : 0.001;
+        timing() {
+            related_pin : clk_b;
+            timing_type : setup_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+        }
+        timing() {
+            related_pin : clk_b;
+            timing_type : hold_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+        }
+    }
+    bus(din_a)   {
+        bus_type : ss_dpsram_128x64_din_a;
+        direction : input;
+        capacitance : 0.001;
+        timing() {
+            related_pin : clk_b;
+            timing_type : setup_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+        }
+        timing() {
+            related_pin : clk_b;
+            timing_type : hold_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+        }
+    }
+    bus(dout_b)   {
+        bus_type : ss_dpsram_128x64_dout_b;
+        direction : input;
+        capacitance : 0.001;
+        timing() {
+            related_pin : clk_b;
+            timing_type : setup_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+        }
+        timing() {
+            related_pin : clk_b;
+            timing_type : hold_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+        }
+    }
+    bus(rm_a)   {
+        bus_type : ss_dpsram_128x64_rm_a;
+        direction : input;
+        capacitance : 0.001;
+        timing() {
+            related_pin : clk_b;
+            timing_type : setup_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+        }
+        timing() {
+            related_pin : clk_b;
+            timing_type : hold_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+        }
+    }
+    bus(rm_b)   {
+        bus_type : ss_dpsram_128x64_rm_b;
+        direction : input;
+        capacitance : 0.001;
+        timing() {
+            related_pin : clk_b;
+            timing_type : setup_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+        }
+        timing() {
+            related_pin : clk_b;
+            timing_type : hold_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+        }
+    }
+    pin(a_off){
+        direction : input;
+        capacitance : 0.001;
+        timing() {
+            related_pin : clk_b;
+            timing_type : setup_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+        }
+        timing() {
+            related_pin : clk_b;
+            timing_type : hold_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+        }
+    }
+    pin(ds_i){
+        direction : input;
+        capacitance : 0.001;
+        timing() {
+            related_pin : clk_b;
+            timing_type : setup_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+        }
+        timing() {
+            related_pin : clk_b;
+            timing_type : hold_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+        }
+    }
+    pin(ls_){
+        direction : input;
+        capacitance : 0.001;
+        timing() {
+            related_pin : clk_b;
+            timing_type : setup_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+        }
+        timing() {
+            related_pin : clk_b;
+            timing_type : hold_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+        }
+    }
+    pin(me_a){
+        direction : input;
+        capacitance : 0.001;
+        timing() {
+            related_pin : clk_b;
+            timing_type : setup_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+        }
+        timing() {
+            related_pin : clk_b;
+            timing_type : hold_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+        }
+    }
+    pin(me_b){
+        direction : input;
+        capacitance : 0.001;
+        timing() {
+            related_pin : clk_b;
+            timing_type : setup_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+        }
+        timing() {
+            related_pin : clk_b;
+            timing_type : hold_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+        }
+    }
+    pin(p_off){
+        direction : input;
+        capacitance : 0.001;
+        timing() {
+            related_pin : clk_b;
+            timing_type : setup_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+        }
+        timing() {
+            related_pin : clk_b;
+            timing_type : hold_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+        }
+    }
+    pin(rme_a){
+        direction : input;
+        capacitance : 0.001;
+        timing() {
+            related_pin : clk_b;
+            timing_type : setup_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+        }
+        timing() {
+            related_pin : clk_b;
+            timing_type : hold_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+        }
+    }
+    pin(rme_bb){
+        direction : input;
+        capacitance : 0.001;
+        timing() {
+            related_pin : clk_b;
+            timing_type : setup_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+        }
+        timing() {
+            related_pin : clk_b;
+            timing_type : hold_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+        }
+    }
+    pin(rop_ds){
+        direction : input;
+        capacitance : 0.001;
+        timing() {
+            related_pin : clk_b;
+            timing_type : setup_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+        }
+        timing() {
+            related_pin : clk_b;
+            timing_type : hold_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+        }
+    }
+    pin(rop_sd){
+        direction : input;
+        capacitance : 0.001;
+        timing() {
+            related_pin : clk_b;
+            timing_type : setup_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+        }
+        timing() {
+            related_pin : clk_b;
+            timing_type : hold_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+        }
+    }
+    pin(sd){
+        direction : input;
+        capacitance : 0.001;
+        timing() {
+            related_pin : clk_b;
+            timing_type : setup_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+        }
+        timing() {
+            related_pin : clk_b;
+            timing_type : hold_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+        }
+    }
+    pin(test1_a){
+        direction : input;
+        capacitance : 0.001;
+        timing() {
+            related_pin : clk_b;
+            timing_type : setup_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+        }
+        timing() {
+            related_pin : clk_b;
+            timing_type : hold_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+        }
+    }
+    pin(test1_b){
+        direction : input;
+        capacitance : 0.001;
+        timing() {
+            related_pin : clk_b;
+            timing_type : setup_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+        }
+        timing() {
+            related_pin : clk_b;
+            timing_type : hold_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+        }
+    }
+    pin(test_rnm_a){
+        direction : input;
+        capacitance : 0.001;
+        timing() {
+            related_pin : clk_b;
+            timing_type : setup_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+        }
+        timing() {
+            related_pin : clk_b;
+            timing_type : hold_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+        }
+    }
+    pin(tpr_a){
+        direction : input;
+        capacitance : 0.001;
+        timing() {
+            related_pin : clk_b;
+            timing_type : setup_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+        }
+        timing() {
+            related_pin : clk_b;
+            timing_type : hold_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+        }
+    }
+    pin(tpr_b){
+        direction : input;
+        capacitance : 0.001;
+        timing() {
+            related_pin : clk_b;
+            timing_type : setup_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+        }
+        timing() {
+            related_pin : clk_b;
+            timing_type : hold_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+        }
+    }
+    pin(we_a){
+        direction : input;
+        capacitance : 0.001;
+        timing() {
+            related_pin : clk_b;
+            timing_type : setup_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.079, 0.079", \
+                  "0.079, 0.079" \
+                )
+            }
+        }
+        timing() {
+            related_pin : clk_b;
+            timing_type : hold_rising ;
+            rise_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+            fall_constraint(ss_dpsram_128x64_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.221, 0.221", \
+                  "0.221, 0.221" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+            fall_power(ss_dpsram_128x64_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.021, 0.021")
+            }
+        }
+    }
+    cell_leakage_power : 123.400;
+}
+
+}
diff --git a/test/cfg/ss_dpsram_128x64_physical.csv b/test/cfg/ss_dpsram_128x64_physical.csv
new file mode 100644
index 0000000..ea8f89a
--- /dev/null
+++ b/test/cfg/ss_dpsram_128x64_physical.csv
@@ -0,0 +1,311 @@
+MACRO,SIZE_WIDTH,SIZE_HEIGHT,SOURCE,PIN,USE,LAYER,x1,y1,x2,y2
+ss_dpsram_128x64,49.5,200.05,PIN,addr_a[0],SIGNAL,M6,20.37,102.87,20.41,103.504
+ss_dpsram_128x64,49.5,200.05,PIN,addr_a[1],SIGNAL,M6,20.51,102.79,20.53,103.424
+ss_dpsram_128x64,49.5,200.05,PIN,addr_a[2],SIGNAL,M6,20.1,103.384,20.26,104.018
+ss_dpsram_128x64,49.5,200.05,PIN,addr_a[3],SIGNAL,M6,20.37,103.544,20.41,104.178
+ss_dpsram_128x64,49.5,200.05,PIN,addr_a[4],SIGNAL,M6,20.51,103.464,20.53,104.098
+ss_dpsram_128x64,49.5,200.05,PIN,addr_a[5],SIGNAL,M6,20.64,103.384,20.66,104.018
+ss_dpsram_128x64,49.5,200.05,PIN,addr_a[6],SIGNAL,M6,19.55,102.87,19.62,103.504
+ss_dpsram_128x64,49.5,200.05,PIN,addr_a[7],SIGNAL,M6,19.65,102.79,19.743,103.424
+ss_dpsram_128x64,49.5,200.05,PIN,addr_a[8],SIGNAL,M6,19.81,102.71,19.86,103.344
+ss_dpsram_128x64,49.5,200.05,PIN,addr_b[0],SIGNAL,M6,20.10,102.79,20.14,103.424
+ss_dpsram_128x64,49.5,200.05,PIN,addr_b[1],SIGNAL,M6,20.1,102.71,20.26,103.344
+ss_dpsram_128x64,49.5,200.05,PIN,addr_b[2],SIGNAL,M6,20.37,104.218,20.41,104.852
+ss_dpsram_128x64,49.5,200.05,PIN,addr_b[3],SIGNAL,M6,20.51,104.138,20.53,104.772
+ss_dpsram_128x64,49.5,200.05,PIN,addr_b[4],SIGNAL,M6,20.64,104.058,20.66,104.692
+ss_dpsram_128x64,49.5,200.05,PIN,addr_b[5],SIGNAL,M6,19.55,103.544,19.62,104.178
+ss_dpsram_128x64,49.5,200.05,PIN,addr_b[6],SIGNAL,M6,19.65,103.464,19.743,104.098
+ss_dpsram_128x64,49.5,200.05,PIN,addr_b[7],SIGNAL,M6,19.81,103.384,19.86,104.018
+ss_dpsram_128x64,49.5,200.05,PIN,addr_b[8],SIGNAL,M6,19.82,103.544,20.02,104.178
+ss_dpsram_128x64,49.5,200.05,PIN,a_off,SIGNAL,M6,19.55,102.044,19.62,102.678
+ss_dpsram_128x64,49.5,200.05,PIN,clk_a,CLOCK,M6,19.65,106.834,19.74,107.468
+ss_dpsram_128x64,49.5,200.05,PIN,clk_b,CLOCK,M6,19.55,106.914,19.62,107.548
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[0],SIGNAL,M6,19.55,208.344,19.62,208.978
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[1],SIGNAL,M6,19.55,206.895,19.62,207.529
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[2],SIGNAL,M6,19.55,205.446,19.62,206.08
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[3],SIGNAL,M6,19.55,203.997,19.62,204.631
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[4],SIGNAL,M6,19.55,202.548,19.62,203.182
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[5],SIGNAL,M6,19.55,201.099,19.62,201.733
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[6],SIGNAL,M6,19.55,199.65,19.62,200.284
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[7],SIGNAL,M6,19.55,198.201,19.62,198.835
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[8],SIGNAL,M6,19.55,196.752,19.62,197.386
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[9],SIGNAL,M6,19.55,195.303,19.62,195.937
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[10],SIGNAL,M6,19.55,193.854,19.62,194.488
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[11],SIGNAL,M6,19.55,192.405,19.62,193.039
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[12],SIGNAL,M6,19.55,190.956,19.62,191.59
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[13],SIGNAL,M6,19.55,189.507,19.62,190.141
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[14],SIGNAL,M6,19.55,188.058,19.62,188.692
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[15],SIGNAL,M6,19.55,186.609,19.62,187.243
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[16],SIGNAL,M6,19.55,185.16,19.62,185.794
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[17],SIGNAL,M6,19.55,183.711,19.62,184.345
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[18],SIGNAL,M6,19.55,182.262,19.62,182.896
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[19],SIGNAL,M6,19.55,180.813,19.62,181.447
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[20],SIGNAL,M6,19.55,179.364,19.62,179.998
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[21],SIGNAL,M6,19.55,177.915,19.62,178.549
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[22],SIGNAL,M6,19.55,176.466,19.62,177.1
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[23],SIGNAL,M6,19.55,175.017,19.62,175.651
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[24],SIGNAL,M6,19.55,173.568,19.62,174.202
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[25],SIGNAL,M6,19.55,172.119,19.62,172.753
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[26],SIGNAL,M6,19.55,170.67,19.62,171.304
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[27],SIGNAL,M6,19.55,169.221,19.62,169.855
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[28],SIGNAL,M6,19.55,167.772,19.62,168.406
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[29],SIGNAL,M6,19.55,166.323,19.62,166.957
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[30],SIGNAL,M6,19.55,164.874,19.62,165.508
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[31],SIGNAL,M6,19.55,163.425,19.62,164.059
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[32],SIGNAL,M6,19.55,156.824,19.62,157.458
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[33],SIGNAL,M6,19.55,155.375,19.62,156.009
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[34],SIGNAL,M6,19.55,153.926,19.62,154.56
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[35],SIGNAL,M6,19.55,152.477,19.62,153.111
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[36],SIGNAL,M6,19.55,151.028,19.62,151.662
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[37],SIGNAL,M6,19.55,149.579,19.62,150.213
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[38],SIGNAL,M6,19.55,148.13,19.62,148.764
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[39],SIGNAL,M6,19.55,146.681,19.62,147.315
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[40],SIGNAL,M6,19.55,145.232,19.62,145.866
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[41],SIGNAL,M6,19.55,143.783,19.62,144.417
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[42],SIGNAL,M6,19.55,142.334,19.62,142.968
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[43],SIGNAL,M6,19.55,140.885,19.62,141.519
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[44],SIGNAL,M6,19.55,139.436,19.62,140.07
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[45],SIGNAL,M6,19.55,137.987,19.62,138.621
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[46],SIGNAL,M6,19.55,136.538,19.62,137.172
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[47],SIGNAL,M6,19.55,135.089,19.62,135.723
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[48],SIGNAL,M6,19.55,133.64,19.62,134.274
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[49],SIGNAL,M6,19.55,132.191,19.62,132.825
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[50],SIGNAL,M6,19.55,130.742,19.62,131.376
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[51],SIGNAL,M6,19.55,129.293,19.62,129.927
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[52],SIGNAL,M6,19.55,127.844,19.62,128.478
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[53],SIGNAL,M6,19.55,126.395,19.62,127.029
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[54],SIGNAL,M6,19.55,124.946,19.62,125.58
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[55],SIGNAL,M6,19.55,123.497,19.62,124.131
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[56],SIGNAL,M6,19.55,122.048,19.62,122.682
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[57],SIGNAL,M6,19.55,120.599,19.62,121.233
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[58],SIGNAL,M6,19.55,119.15,19.62,119.784
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[59],SIGNAL,M6,19.55,117.701,19.62,118.335
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[60],SIGNAL,M6,19.55,116.252,19.62,116.886
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[61],SIGNAL,M6,19.55,114.803,19.62,115.437
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[62],SIGNAL,M6,19.55,113.354,19.62,113.988
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[63],SIGNAL,M6,19.55,111.905,19.62,112.539
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[64],SIGNAL,M6,19.55,98.542,19.62,99.176
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[65],SIGNAL,M6,19.55,97.093,19.62,97.727
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[66],SIGNAL,M6,19.55,95.644,19.62,96.278
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[67],SIGNAL,M6,19.55,94.195,19.62,94.829
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[68],SIGNAL,M6,19.55,92.746,19.62,93.38
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[69],SIGNAL,M6,19.55,91.297,19.62,91.931
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[70],SIGNAL,M6,19.55,89.848,19.62,90.482
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[71],SIGNAL,M6,19.55,88.399,19.62,89.033
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[72],SIGNAL,M6,19.55,86.95,19.62,87.584
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[73],SIGNAL,M6,19.55,85.501,19.62,86.135
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[74],SIGNAL,M6,19.55,84.052,19.62,84.686
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[75],SIGNAL,M6,19.55,82.603,19.62,83.237
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[76],SIGNAL,M6,19.55,81.154,19.62,81.788
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[77],SIGNAL,M6,19.55,79.705,19.62,80.339
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[78],SIGNAL,M6,19.55,78.256,19.62,78.89
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[79],SIGNAL,M6,19.55,76.807,19.62,77.441
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[80],SIGNAL,M6,19.55,75.358,19.62,75.992
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[81],SIGNAL,M6,19.55,73.909,19.62,74.543
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[82],SIGNAL,M6,19.55,72.46,19.62,73.094
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[83],SIGNAL,M6,19.55,71.011,19.62,71.645
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[84],SIGNAL,M6,19.55,69.562,19.62,70.196
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[85],SIGNAL,M6,19.55,68.113,19.62,68.747
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[86],SIGNAL,M6,19.55,66.664,19.62,67.298
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[87],SIGNAL,M6,19.55,65.215,19.62,65.849
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[88],SIGNAL,M6,19.55,63.766,19.62,64.4
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[89],SIGNAL,M6,19.55,62.317,19.62,62.951
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[90],SIGNAL,M6,19.55,60.868,19.62,61.502
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[91],SIGNAL,M6,19.55,59.419,19.62,60.053
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[92],SIGNAL,M6,19.55,57.97,19.62,58.604
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[93],SIGNAL,M6,19.55,56.521,19.62,57.155
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[94],SIGNAL,M6,19.55,55.072,19.62,55.706
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[95],SIGNAL,M6,19.55,53.623,19.62,54.257
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[96],SIGNAL,M6,19.55,47.022,19.62,47.656
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[97],SIGNAL,M6,19.55,45.573,19.62,46.207
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[98],SIGNAL,M6,19.55,44.124,19.62,44.758
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[99],SIGNAL,M6,19.55,42.675,19.62,43.309
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[100],SIGNAL,M6,19.55,41.226,19.62,41.86
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[101],SIGNAL,M6,19.55,39.777,19.62,40.411
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[102],SIGNAL,M6,19.55,38.328,19.62,38.962
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[103],SIGNAL,M6,19.55,36.879,19.62,37.513
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[104],SIGNAL,M6,19.55,35.43,19.62,36.064
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[105],SIGNAL,M6,19.55,33.981,19.62,34.615
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[106],SIGNAL,M6,19.55,32.532,19.62,33.166
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[107],SIGNAL,M6,19.55,31.083,19.62,31.717
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[108],SIGNAL,M6,19.55,29.634,19.62,30.268
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[109],SIGNAL,M6,19.55,28.185,19.62,28.819
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[110],SIGNAL,M6,19.55,26.736,19.62,27.37
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[111],SIGNAL,M6,19.55,25.287,19.62,25.921
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[112],SIGNAL,M6,19.55,23.838,19.62,24.472
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[113],SIGNAL,M6,19.55,22.389,19.62,23.023
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[114],SIGNAL,M6,19.55,20.94,19.62,21.574
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[115],SIGNAL,M6,19.55,19.491,19.62,20.125
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[116],SIGNAL,M6,19.55,18.042,19.62,18.676
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[117],SIGNAL,M6,19.55,16.593,19.62,17.227
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[118],SIGNAL,M6,19.55,15.144,19.62,15.778
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[119],SIGNAL,M6,19.55,13.695,19.62,14.329
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[120],SIGNAL,M6,19.55,12.246,19.62,12.88
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[121],SIGNAL,M6,19.55,10.797,19.62,11.431
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[122],SIGNAL,M6,19.55,9.348,19.62,9.982
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[123],SIGNAL,M6,19.55,7.899,19.62,8.533
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[124],SIGNAL,M6,19.55,6.45,19.62,7.084
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[125],SIGNAL,M6,19.55,5.001,19.62,5.635
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[126],SIGNAL,M6,19.55,3.552,19.62,4.186
+ss_dpsram_128x64,49.5,200.05,PIN,din_a[127],SIGNAL,M6,19.55,2.103,19.62,2.737
+ss_dpsram_128x64,49.5,200.05,PIN,ds_i,SIGNAL,M6,20.10,106.834,20.14,107.468
+ss_dpsram_128x64,49.5,200.05,PIN,ls_,SIGNAL,M6,19.82,106.24,20.02,106.874
+ss_dpsram_128x64,49.5,200.05,PIN,me_a,SIGNAL,M6,20.1,106.08,20.26,106.714
+ss_dpsram_128x64,49.5,200.05,PIN,me_b,SIGNAL,M6,20.10,106.16,20.14,106.794
+ss_dpsram_128x64,49.5,200.05,PIN,p_off,SIGNAL,M6,19.65,101.964,19.74,102.598
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[0],SIGNAL,M6,19.65,208.264,19.74,208.898
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[1],SIGNAL,M6,19.65,206.815,19.74,207.449
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[2],SIGNAL,M6,19.65,205.366,19.74,206
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[3],SIGNAL,M6,19.65,203.917,19.74,204.551
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[4],SIGNAL,M6,19.65,202.468,19.74,203.102
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[5],SIGNAL,M6,19.65,201.019,19.74,201.653
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[6],SIGNAL,M6,19.65,199.57,19.74,200.204
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[7],SIGNAL,M6,19.65,198.121,19.74,198.755
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[8],SIGNAL,M6,19.65,196.672,19.74,197.306
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[9],SIGNAL,M6,19.65,195.223,19.74,195.857
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[10],SIGNAL,M6,19.65,193.774,19.74,194.408
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[11],SIGNAL,M6,19.65,192.325,19.74,192.959
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[12],SIGNAL,M6,19.65,190.876,19.74,191.51
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[13],SIGNAL,M6,19.65,189.427,19.74,190.061
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[14],SIGNAL,M6,19.65,187.978,19.74,188.612
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[15],SIGNAL,M6,19.65,186.529,19.74,187.163
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[16],SIGNAL,M6,19.65,185.08,19.74,185.714
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[17],SIGNAL,M6,19.65,183.631,19.74,184.265
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[18],SIGNAL,M6,19.65,182.182,19.74,182.816
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[19],SIGNAL,M6,19.65,180.733,19.74,181.367
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[20],SIGNAL,M6,19.65,179.284,19.74,179.918
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[21],SIGNAL,M6,19.65,177.835,19.74,178.469
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[22],SIGNAL,M6,19.65,176.386,19.74,177.02
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[23],SIGNAL,M6,19.65,174.937,19.74,175.571
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[24],SIGNAL,M6,19.65,173.488,19.74,174.122
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[25],SIGNAL,M6,19.65,172.039,19.74,172.673
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[26],SIGNAL,M6,19.65,170.59,19.74,171.224
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[27],SIGNAL,M6,19.65,169.141,19.74,169.775
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[28],SIGNAL,M6,19.65,167.692,19.74,168.326
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[29],SIGNAL,M6,19.65,166.243,19.74,166.877
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[30],SIGNAL,M6,19.65,164.794,19.74,165.428
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[31],SIGNAL,M6,19.65,163.345,19.74,163.979
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[32],SIGNAL,M6,19.65,156.744,19.74,157.378
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[33],SIGNAL,M6,19.65,155.295,19.74,155.929
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[34],SIGNAL,M6,19.65,153.846,19.74,154.48
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[35],SIGNAL,M6,19.65,152.397,19.74,153.031
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[36],SIGNAL,M6,19.65,150.948,19.74,151.582
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[37],SIGNAL,M6,19.65,149.499,19.74,150.133
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[38],SIGNAL,M6,19.65,148.05,19.74,148.684
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[39],SIGNAL,M6,19.65,146.601,19.74,147.235
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[40],SIGNAL,M6,19.65,145.152,19.74,145.786
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[41],SIGNAL,M6,19.65,143.703,19.74,144.337
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[42],SIGNAL,M6,19.65,142.254,19.74,142.888
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[43],SIGNAL,M6,19.65,140.805,19.74,141.439
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[44],SIGNAL,M6,19.65,139.356,19.74,139.99
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[45],SIGNAL,M6,19.65,137.907,19.74,138.541
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[46],SIGNAL,M6,19.65,136.458,19.74,137.092
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[47],SIGNAL,M6,19.65,135.009,19.74,135.643
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[48],SIGNAL,M6,19.65,133.56,19.74,134.194
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[49],SIGNAL,M6,19.65,132.111,19.74,132.745
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[50],SIGNAL,M6,19.65,130.662,19.74,131.296
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[51],SIGNAL,M6,19.65,129.213,19.74,129.847
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[52],SIGNAL,M6,19.65,127.764,19.74,128.398
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[53],SIGNAL,M6,19.65,126.315,19.74,126.949
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[54],SIGNAL,M6,19.65,124.866,19.74,125.5
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[55],SIGNAL,M6,19.65,123.417,19.74,124.051
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[56],SIGNAL,M6,19.65,121.968,19.74,122.602
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[57],SIGNAL,M6,19.65,120.519,19.74,121.153
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[58],SIGNAL,M6,19.65,119.07,19.74,119.704
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[59],SIGNAL,M6,19.65,117.621,19.74,118.255
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[60],SIGNAL,M6,19.65,116.172,19.74,116.806
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[61],SIGNAL,M6,19.65,114.723,19.74,115.357
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[62],SIGNAL,M6,19.65,113.274,19.74,113.908
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[63],SIGNAL,M6,19.65,111.825,19.74,112.459
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[64],SIGNAL,M6,19.65,98.462,19.74,99.096
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[65],SIGNAL,M6,19.65,97.013,19.74,97.647
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[66],SIGNAL,M6,19.65,95.564,19.74,96.198
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[67],SIGNAL,M6,19.65,94.115,19.74,94.749
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[68],SIGNAL,M6,19.65,92.666,19.74,93.3
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[69],SIGNAL,M6,19.65,91.217,19.74,91.851
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[70],SIGNAL,M6,19.65,89.768,19.74,90.402
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[71],SIGNAL,M6,19.65,88.319,19.74,88.953
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[72],SIGNAL,M6,19.65,86.87,19.74,87.504
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[73],SIGNAL,M6,19.65,85.421,19.74,86.055
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[74],SIGNAL,M6,19.65,83.972,19.74,84.606
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[75],SIGNAL,M6,19.65,82.523,19.74,83.157
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[76],SIGNAL,M6,19.65,81.074,19.74,81.708
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[77],SIGNAL,M6,19.65,79.625,19.74,80.259
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[78],SIGNAL,M6,19.65,78.176,19.74,78.81
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[79],SIGNAL,M6,19.65,76.727,19.74,77.361
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[80],SIGNAL,M6,19.65,75.278,19.74,75.912
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[81],SIGNAL,M6,19.65,73.829,19.74,74.463
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[82],SIGNAL,M6,19.65,72.38,19.74,73.014
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[83],SIGNAL,M6,19.65,70.931,19.74,71.565
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[84],SIGNAL,M6,19.65,69.482,19.74,70.116
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[85],SIGNAL,M6,19.65,68.033,19.74,68.667
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[86],SIGNAL,M6,19.65,66.584,19.74,67.218
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[87],SIGNAL,M6,19.65,65.135,19.74,65.769
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[88],SIGNAL,M6,19.65,63.686,19.74,64.32
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[89],SIGNAL,M6,19.65,62.237,19.74,62.871
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[90],SIGNAL,M6,19.65,60.788,19.74,61.422
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[91],SIGNAL,M6,19.65,59.339,19.74,59.973
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[92],SIGNAL,M6,19.65,57.89,19.74,58.524
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[93],SIGNAL,M6,19.65,56.441,19.74,57.075
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[94],SIGNAL,M6,19.65,54.992,19.74,55.626
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[95],SIGNAL,M6,19.65,53.543,19.74,54.177
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[96],SIGNAL,M6,19.65,46.942,19.74,47.576
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[97],SIGNAL,M6,19.65,45.493,19.74,46.127
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[98],SIGNAL,M6,19.65,44.044,19.74,44.678
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[99],SIGNAL,M6,19.65,42.595,19.74,43.229
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[100],SIGNAL,M6,19.65,41.146,19.74,41.78
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[101],SIGNAL,M6,19.65,39.697,19.74,40.331
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[102],SIGNAL,M6,19.65,38.248,19.74,38.882
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[103],SIGNAL,M6,19.65,36.799,19.74,37.433
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[104],SIGNAL,M6,19.65,35.35,19.74,35.984
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[105],SIGNAL,M6,19.65,33.901,19.74,34.535
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[106],SIGNAL,M6,19.65,32.452,19.74,33.086
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[107],SIGNAL,M6,19.65,31.003,19.74,31.637
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[108],SIGNAL,M6,19.65,29.554,19.74,30.188
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[109],SIGNAL,M6,19.65,28.105,19.74,28.739
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[110],SIGNAL,M6,19.65,26.656,19.74,27.29
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[111],SIGNAL,M6,19.65,25.207,19.74,25.841
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[112],SIGNAL,M6,19.65,23.758,19.74,24.392
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[113],SIGNAL,M6,19.65,22.309,19.74,22.943
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[114],SIGNAL,M6,19.65,20.86,19.74,21.494
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[115],SIGNAL,M6,19.65,19.411,19.74,20.045
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[116],SIGNAL,M6,19.65,17.962,19.74,18.596
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[117],SIGNAL,M6,19.65,16.513,19.74,17.147
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[118],SIGNAL,M6,19.65,15.064,19.74,15.698
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[119],SIGNAL,M6,19.65,13.615,19.74,14.249
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[120],SIGNAL,M6,19.65,12.166,19.74,12.8
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[121],SIGNAL,M6,19.65,10.717,19.74,11.351
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[122],SIGNAL,M6,19.65,9.268,19.74,9.902
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[123],SIGNAL,M6,19.65,7.819,19.74,8.453
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[124],SIGNAL,M6,19.65,6.37,19.74,7.004
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[125],SIGNAL,M6,19.65,4.921,19.74,5.555
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[126],SIGNAL,M6,19.65,3.472,19.74,4.106
+ss_dpsram_128x64,49.5,200.05,PIN,dout_b[127],SIGNAL,M6,19.65,2.023,19.74,2.657
+ss_dpsram_128x64,49.5,200.05,PIN,rm_a[0],SIGNAL,M6,20.37,105.566,20.41,106.2
+ss_dpsram_128x64,49.5,200.05,PIN,rm_a[1],SIGNAL,M6,20.51,105.486,20.53,106.12
+ss_dpsram_128x64,49.5,200.05,PIN,rm_a[2],SIGNAL,M6,20.64,105.406,20.66,106.04
+ss_dpsram_128x64,49.5,200.05,PIN,rm_a[3],SIGNAL,M6,19.55,104.892,19.61,105.526
+ss_dpsram_128x64,49.5,200.05,PIN,rm_b[0],SIGNAL,M6,19.81,105.406,19.86,106.04
+ss_dpsram_128x64,49.5,200.05,PIN,rm_b[1],SIGNAL,M6,19.82,105.566,20.02,106.2
+ss_dpsram_128x64,49.5,200.05,PIN,rm_b[2],SIGNAL,M6,20.10,105.486,20.14,106.12
+ss_dpsram_128x64,49.5,200.05,PIN,rm_b[3],SIGNAL,M6,20.1,105.406,20.26,106.04
+ss_dpsram_128x64,49.5,200.05,PIN,rme_a,SIGNAL,M6,19.65,105.486,19.74,106.12
+ss_dpsram_128x64,49.5,200.05,PIN,rme_bb,SIGNAL,M6,19.55,105.566,19.61,106.2
+ss_dpsram_128x64,49.5,200.05,PIN,rop_ds,SIGNAL,M6,19.55,0.654,19.61,1.288
+ss_dpsram_128x64,49.5,200.05,PIN,rop_sd,SIGNAL,M6,19.65,0.574,19.74,1.208
+ss_dpsram_128x64,49.5,200.05,PIN,sd,SIGNAL,M6,19.65,104.812,19.74,105.446
+ss_dpsram_128x64,49.5,200.05,PIN,test1_a,SIGNAL,M6,19.82,104.892,20.0145,105.526
+ss_dpsram_128x64,49.5,200.05,PIN,test1_b,SIGNAL,M6,19.81,104.732,19.86,105.366
+ss_dpsram_128x64,49.5,200.05,PIN,test_rnm_a,SIGNAL,M6,20.10,104.812,20.1465,105.446
+ss_dpsram_128x64,49.5,200.05,PIN,tpr_a,SIGNAL,M6,20.37,104.892,20.41,105.526
+ss_dpsram_128x64,49.5,200.05,PIN,tpr_b,SIGNAL,M6,20.1,104.732,20.26,105.366
+ss_dpsram_128x64,49.5,200.05,PIN,we_a,SIGNAL,M6,19.65,104.138,19.74,104.772
+ss_dpsram_128x64,49.5,200.05,PIN,VDD,POWER,M5,0,209.976,19.5525,210.03
+ss_dpsram_128x64,49.5,200.05,PIN,VDDA,POWER,M5,0,210.164,19.5525,210.218
+ss_dpsram_128x64,49.5,200.05,PIN,VSS,GROUND,M5,0,210.07,19.5525,210.124
+ss_dpsram_128x64,49.5,200.05,OBS,,,M6,19.2025,-0.26,21.2525,210.526
+ss_dpsram_128x64,49.5,200.05,OBS,,,M1,-0.108,-0.108,46.593,210.374
+ss_dpsram_128x64,49.5,200.05,OBS,,,M4,-0.087,-0.087,46.572,210.353
+ss_dpsram_128x64,49.5,200.05,OBS,,,M2,-0.07,-0.07,46.555,210.336
+ss_dpsram_128x64,49.5,200.05,OBS,,,M5,-0.087,-0.087,46.572,210.353
+ss_dpsram_128x64,49.5,200.05,OBS,,,M3,-0.06,-0.06,46.545,210.326
diff --git a/test/cfg/ss_metrics.csv b/test/cfg/ss_metrics.csv
index a127664..5ff2e64 100644
--- a/test/cfg/ss_metrics.csv
+++ b/test/cfg/ss_metrics.csv
@@ -1,4 +1,4 @@
 NumWords,NumBits,compiler_name,memory_name,NumBanks,area_x (microns),area_y (microns),pin cap (pf),setup time (ns),hold time (ns),access time (ns),cycle time (ns),static power (uW),dynamic power (uW/MHz)
 64,256,fake_compiler,sssram_64x256_b2,2,22.7,65.9,0.000754,0.034,0.098,0.201,0.590,1.312,3.339
 ,,fake_compiler,sssram_64x256,1,13.7,140.0,0.005,0.053,0.075,0.319,0.456,1.639,3.456
-
+128,64,fake_compiler,ss_dpsram_128x64,8,49.5,200.05,0.000912,0.079,0.221,0.412,0.456,123.4,2.15
\ No newline at end of file
diff --git a/test/dpsram_ss_flow_test.py b/test/dpsram_ss_flow_test.py
new file mode 100755
index 0000000..0b9c1eb
--- /dev/null
+++ b/test/dpsram_ss_flow_test.py
@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+
+import os
+import shutil
+import unittest
+import subprocess
+from test_utils import TestUtils
+from ss_flow_test_base import SSFlowTestBase
+
+
+class SSDPSRAMFlowTest(SSFlowTestBase):
+    """Flow test for spreadsheet input dual port RAM"""
+
+    def setUp(self):
+        """Sets up paths to validate results"""
+        self._tag = "dpsram"
+        SSFlowTestBase.set_up(self, self._tag)
+
+    def test_example_input(self):
+        """Tests the example input run"""
+
+        test_config = {
+            "ss_dpsram_128x64": {
+                "physical_csv": "ss_dpsram_128x64_physical.csv",
+                "metrics_csv": "ss_metrics.csv",
+                "mapping_file": "csv_map.py",
+            },
+        }
+        for test_name, file_config in test_config.items():
+            self._execute_run(
+                self._tag,
+                file_config["physical_csv"],
+                file_config["metrics_csv"],
+                file_config["mapping_file"],
+                [test_name],
+            )
+
+
+if __name__ == "__main__":
+    unittest.main()
diff --git a/utils/lef_exporter.py b/utils/lef_exporter.py
index 3fd330b..f2cbae0 100644
--- a/utils/lef_exporter.py
+++ b/utils/lef_exporter.py
@@ -132,11 +132,19 @@ def write_signals(self, fid, rw_port_group):
         """Writes rw signal bundle, comprised of dout, din, addr busses"""
 
         bits = self.get_memory().get_width()
-        self.write_signal_bus(fid, rw_port_group.get_data_output_bus_name(), 0, bits)
-        self.write_signal_bus(fid, rw_port_group.get_data_input_bus_name(), 0, bits)
-        self.write_signal_bus(
-            fid, rw_port_group.get_address_bus_name(), 0, self._memory.get_addr_width()
-        )
+        if rw_port_group.get_data_output_bus_name():
+            self.write_signal_bus(
+                fid, rw_port_group.get_data_output_bus_name(), 0, bits
+            )
+        if rw_port_group.get_data_input_bus_name():
+            self.write_signal_bus(fid, rw_port_group.get_data_input_bus_name(), 0, bits)
+        if rw_port_group.get_address_bus_name():
+            self.write_signal_bus(
+                fid,
+                rw_port_group.get_address_bus_name(),
+                0,
+                self._memory.get_addr_width(),
+            )
 
     def write_signal_pins(self, fid):
         """LEF SIGNAL PINS"""
@@ -145,10 +153,12 @@ def write_signal_pins(self, fid):
         for rw_port_group in mem.get_rw_port_groups():
             self.write_signals(fid, rw_port_group)
         for rw_port_group in mem.get_rw_port_groups():
-            port = mem.get_port(rw_port_group.get_write_enable_name())
-            self.write_pin(fid, port)
-            port = mem.get_port(rw_port_group.get_clock_name())
-            self.write_pin(fid, port)
+            if rw_port_group.get_write_enable_name():
+                port = mem.get_port(rw_port_group.get_write_enable_name())
+                self.write_pin(fid, port)
+            if rw_port_group.get_clock_name():
+                port = mem.get_port(rw_port_group.get_clock_name())
+                self.write_pin(fid, port)
         for bus_name, bus_data in mem.get_misc_busses().items():
             self.write_signal_bus(fid, bus_name, bus_data["lsb"], bus_data["msb"] + 1)
         for port_name in sorted(mem.get_misc_ports()):
diff --git a/utils/liberty_exporter.py b/utils/liberty_exporter.py
index 46d136e..c7f5c28 100644
--- a/utils/liberty_exporter.py
+++ b/utils/liberty_exporter.py
@@ -407,21 +407,32 @@ def write_rw_pin_set(self, out_fh, name, rw_port_group, is_ram):
         """Writes the rw port group to the output stream"""
 
         clk_pin_name = rw_port_group.get_clock_name()
-        self.write_pin(
-            out_fh, name, rw_port_group.get_write_enable_name(), clk_pin_name
-        )
-        self.write_address_bus(
-            out_fh, name, rw_port_group.get_address_bus_name(), clk_pin_name
-        )
-        self.write_data_bus(
-            out_fh,
-            name,
-            rw_port_group.get_data_input_bus_name(),
-            rw_port_group.get_write_enable_name(),
-            clk_pin_name,
-            is_ram,
-        )
-        self.write_output_bus(
-            out_fh, name, rw_port_group.get_data_output_bus_name(), clk_pin_name, is_ram
-        )
+        if rw_port_group.get_write_enable_name():
+            self.write_pin(
+                out_fh, name, rw_port_group.get_write_enable_name(), clk_pin_name
+            )
+        if rw_port_group.get_address_bus_name():
+            self.write_address_bus(
+                out_fh, name, rw_port_group.get_address_bus_name(), clk_pin_name
+            )
+        if (
+            rw_port_group.get_data_input_bus_name()
+            and rw_port_group.get_write_enable_name()
+        ):
+            self.write_data_bus(
+                out_fh,
+                name,
+                rw_port_group.get_data_input_bus_name(),
+                rw_port_group.get_write_enable_name(),
+                clk_pin_name,
+                is_ram,
+            )
+        if rw_port_group.get_data_output_bus_name():
+            self.write_output_bus(
+                out_fh,
+                name,
+                rw_port_group.get_data_output_bus_name(),
+                clk_pin_name,
+                is_ram,
+            )
         self.write_clk_pin(out_fh, clk_pin_name)
diff --git a/utils/rw_port_group.py b/utils/rw_port_group.py
index b40f5f1..018e256 100644
--- a/utils/rw_port_group.py
+++ b/utils/rw_port_group.py
@@ -36,6 +36,14 @@ def __init__(self, suffix=None):
             self._data_output_bus_name = None
             self._clk_name = None
 
+    def set_suffix(self, suffix):
+        """
+        Sets the suffix, but does not apply it to the rest of the names.
+
+        If you call it this way, it's basically a tag
+        """
+        self._suffix = suffix
+
     def set_clock_name(self, name):
         """Sets the clock port name"""
         self._clk_name = name
diff --git a/utils/ss_port_organizer.py b/utils/ss_port_organizer.py
new file mode 100644
index 0000000..eb653c4
--- /dev/null
+++ b/utils/ss_port_organizer.py
@@ -0,0 +1,106 @@
+#!/usr/bin/env python3
+
+import re
+import sys
+
+
+class SSPortOrganizer:
+    def __init__(self, pin_type_map):
+        self._rw_groups = {}
+        self._misc_busses = []
+        self._misc_ports = []
+        self._port_dict = {}
+        self._bus_name_re = re.compile("^(\S+)\[(\d+)\]")
+        self._pin_type_map = pin_type_map
+
+    def get_rw_groups(self):
+        return self._rw_groups
+
+    def get_misc_busses(self):
+        return self._misc_busses
+
+    def get_misc_ports(self):
+        return self._misc_ports
+
+    def _consolidate_ports(self, macro_data):
+        for pin_name, pin_data in macro_data["pin_data"].items():
+            result = self._bus_name_re.match(pin_name)
+            if result:
+                bus_name = result.group(1)
+                bit_num = int(result.group(2))
+                if bus_name in self._port_dict:
+                    self._port_dict[bus_name]["lsb"] = min(
+                        bit_num, self._port_dict[bus_name]["lsb"]
+                    )
+                    self._port_dict[bus_name]["msb"] = max(
+                        bit_num, self._port_dict[bus_name]["msb"]
+                    )
+                else:
+                    self._port_dict[bus_name] = {
+                        "name": bus_name,
+                        "msb": bit_num,
+                        "lsb": bit_num,
+                        "type": self.classify_pin(bus_name),
+                    }
+            else:
+                if pin_name in self._port_dict:  # pragma: no cover
+                    raise Exception(f"pin {pin_name} appears twice")
+                pin_type = self.classify_pin(pin_name)
+                # if the scalar port gets classified as a bus, that's not
+                # correct, so set it to None
+                if pin_type and pin_type.endswith("_bus"):
+                    pin_type = None
+                self._port_dict[pin_name] = {"name": pin_name, "type": pin_type}
+
+    def classify_pin(self, pin_name):
+        """
+        Returns the pin classification to help identify whether the pin or bus
+        is the address, data in, data out, write enable, clock or power pin or
+        bus
+        """
+        if pin_name in self._pin_type_map:
+            return self._pin_type_map[pin_name]
+        for prefix, pin_type in self._pin_type_map.items():
+            if pin_name.startswith(prefix):
+                return pin_type
+        return None
+
+    def organize_ports(self, macro_data):
+        self._consolidate_ports(macro_data)
+        address_busses = [
+            v for v in self._port_dict.values() if v.get("type") == "address_bus"
+        ]
+        if len(address_busses) > 1:
+            for address_bus in address_busses:
+                last_char = address_bus["name"][-1]
+                self._rw_groups[last_char] = {}
+            for port_name, port_data in self._port_dict.items():
+                if port_data["type"] in [
+                    "address_bus",
+                    "clock",
+                    "write_enable",
+                    "output_bus",
+                    "data_bus",
+                ]:
+                    last_char = port_data["name"][-1]
+                    self._rw_groups[last_char][port_data["type"]] = port_data
+                elif "msb" in port_data:
+                    self._misc_busses.append(port_data)
+                else:
+                    self._misc_ports.append(port_data)
+        else:
+            rw_group = {}
+            self._rw_groups[""] = rw_group
+            for port_name, port_data in self._port_dict.items():
+                if port_data["type"] in [
+                    "address_bus",
+                    "clock",
+                    "write_enable",
+                    "output_bus",
+                    "data_bus",
+                ]:
+                    rw_group[port_data["type"]] = port_data
+                elif "msb" in port_data:
+                    self._misc_busses.append(port_data)
+                else:
+                    self._misc_ports.append(port_data)
diff --git a/utils/verilog_exporter.py b/utils/verilog_exporter.py
index ee71d6e..30f22d4 100644
--- a/utils/verilog_exporter.py
+++ b/utils/verilog_exporter.py
@@ -81,11 +81,16 @@ def write_rw_port_decl_set(self, rw_port_group, out_fh, index):
 
         if index != 0:
             out_fh.write(",\n")
-        out_fh.write(f"    {rw_port_group.get_write_enable_name()},\n")
-        out_fh.write(f"    {rw_port_group.get_address_bus_name()},\n")
-        out_fh.write(f"    {rw_port_group.get_data_input_bus_name()},\n")
-        out_fh.write(f"    {rw_port_group.get_data_output_bus_name()},\n")
-        out_fh.write(f"    {rw_port_group.get_clock_name()}")
+        if rw_port_group.get_write_enable_name():
+            out_fh.write(f"    {rw_port_group.get_write_enable_name()},\n")
+        if rw_port_group.get_address_bus_name():
+            out_fh.write(f"    {rw_port_group.get_address_bus_name()},\n")
+        if rw_port_group.get_data_input_bus_name():
+            out_fh.write(f"    {rw_port_group.get_data_input_bus_name()},\n")
+        if rw_port_group.get_data_output_bus_name():
+            out_fh.write(f"    {rw_port_group.get_data_output_bus_name()},\n")
+        if rw_port_group.get_clock_name():
+            out_fh.write(f"    {rw_port_group.get_clock_name()}")
 
     def write_misc_decl_set(self, mem, out_fh):
         """Write the misc bus/port declarations"""
@@ -100,21 +105,26 @@ def write_rw_port_defn_set(self, rw_port_group, out_fh):
 
         suffix = rw_port_group.get_suffix()
         out_fh.write(f"    // Port {suffix.upper()}\n")
-        out_fh.write(
-            f"    input  wire                     {rw_port_group.get_write_enable_name()};\n"
-        )
-        out_fh.write(
-            f"    input  wire [ADDR_WIDTH-1:0]    {rw_port_group.get_address_bus_name()};\n"
-        )
-        out_fh.write(
-            f"    input  wire [DATA_WIDTH-1:0]    {rw_port_group.get_data_input_bus_name()};\n"
-        )
-        out_fh.write(
-            f"    output reg  [DATA_WIDTH-1:0]    {rw_port_group.get_data_output_bus_name()};\n"
-        )
-        out_fh.write(
-            f"    input  wire                     {rw_port_group.get_clock_name()};\n"
-        )
+        if rw_port_group.get_write_enable_name():
+            out_fh.write(
+                f"    input  wire                     {rw_port_group.get_write_enable_name()};\n"
+            )
+        if rw_port_group.get_address_bus_name():
+            out_fh.write(
+                f"    input  wire [ADDR_WIDTH-1:0]    {rw_port_group.get_address_bus_name()};\n"
+            )
+        if rw_port_group.get_data_input_bus_name():
+            out_fh.write(
+                f"    input  wire [DATA_WIDTH-1:0]    {rw_port_group.get_data_input_bus_name()};\n"
+            )
+        if rw_port_group.get_data_output_bus_name():
+            out_fh.write(
+                f"    output reg  [DATA_WIDTH-1:0]    {rw_port_group.get_data_output_bus_name()};\n"
+            )
+        if rw_port_group.get_clock_name():
+            out_fh.write(
+                f"    input  wire                     {rw_port_group.get_clock_name()};\n"
+            )
         out_fh.write("\n")
 
     def write_misc_defn_set(self, mem, out_fh):
@@ -147,17 +157,22 @@ def export_bb_port_decl_set(self, rw_port_group, out_fh, index):
         data_bus_msb = mem.get_data_bus_msb()
         if index != 0:
             out_fh.write(",\n")
-        out_fh.write(f"    input {rw_port_group.get_write_enable_name()},\n")
-        out_fh.write(
-            f"    input [{addr_bus_msb}:0] {rw_port_group.get_address_bus_name()},\n"
-        )
-        out_fh.write(
-            f"    input [{data_bus_msb}:0] {rw_port_group.get_data_input_bus_name()},\n"
-        )
-        out_fh.write(
-            f"    output reg [{data_bus_msb}:0] {rw_port_group.get_data_output_bus_name()},\n"
-        )
-        out_fh.write(f"    input {rw_port_group.get_clock_name()}")
+        if rw_port_group.get_write_enable_name():
+            out_fh.write(f"    input {rw_port_group.get_write_enable_name()},\n")
+        if rw_port_group.get_address_bus_name():
+            out_fh.write(
+                f"    input [{addr_bus_msb}:0] {rw_port_group.get_address_bus_name()},\n"
+            )
+        if rw_port_group.get_data_input_bus_name():
+            out_fh.write(
+                f"    input [{data_bus_msb}:0] {rw_port_group.get_data_input_bus_name()},\n"
+            )
+        if rw_port_group.get_data_output_bus_name():
+            out_fh.write(
+                f"    output reg [{data_bus_msb}:0] {rw_port_group.get_data_output_bus_name()},\n"
+            )
+        if rw_port_group.get_clock_name():
+            out_fh.write(f"    input {rw_port_group.get_clock_name()}")
 
     def export_blackbox(self, out_fh):
         """Writes the blackbox content to the output stream"""