Fix write logic in SP model

The simulation model for SP memories wasn't describing a functional
memory as on a write it was only setting bits, never clearing them.
Fix the write statement.

The bitwise OR operation may have been a remnant of a write mask. Before
commit 0fb7f8c ("Re-factored fakeram to support sp/dp ram/regfile")
there was a commented-out line:

    # V_file.write('            mem[addr_in] <= (wd_in & w_mask_in) | (mem[addr_in] & ~w_mask_in);\n')

Signed-off-by: Martin Povišer <povik@cutebit.org>

Author: povik

utils/single_port_ram_verilog_exporter.py

@@ -60,7 +60,7 @@ def export_module(self, out_fh):
         out_fh.write(f"         else if ({we_pin})\n")
         out_fh.write("         begin\n")
         out_fh.write(
-            f"            mem[{addr_bus}] <= ({din_bus}) | (mem[{addr_bus}]);\n"
+            f"            mem[{addr_bus}] <= {din_bus};\n"
         )
         out_fh.write("         end\n")
         out_fh.write("         // read\n")