diff --git a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml index b95435bd6a9b5f..970e1f6de3102a 100644 --- a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml +++ b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml @@ -24,6 +24,7 @@ description: | properties: compatible: enum: + - mediatek,mt6320-keys - mediatek,mt6323-keys - mediatek,mt6328-keys - mediatek,mt6331-keys diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml index 6a89b479d10fad..e1d581688d6a6a 100644 --- a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml @@ -34,6 +34,7 @@ properties: compatible: oneOf: - enum: + - mediatek,mt6320 - mediatek,mt6323 - mediatek,mt6331 # "mediatek,mt6331" for PMIC MT6331 and MT6332. - mediatek,mt6328 @@ -64,6 +65,7 @@ properties: compatible: oneOf: - enum: + - mediatek,mt6320-rtc - mediatek,mt6323-rtc - mediatek,mt6331-rtc - mediatek,mt6358-rtc @@ -88,6 +90,7 @@ properties: compatible: oneOf: - enum: + - mediatek,mt6320-regulator - mediatek,mt6323-regulator - mediatek,mt6328-regulator - mediatek,mt6358-regulator diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml index 19270dd0fec1bb..335bb019cd472b 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -17,6 +17,7 @@ properties: enum: - mediatek,mt2701-pinctrl - mediatek,mt2712-pinctrl + - mediatek,mt6320-pinctrl - mediatek,mt6397-pinctrl - mediatek,mt6589-pinctrl - mediatek,mt7623-pinctrl diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt6320-regulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt6320-regulator.yaml new file mode 100644 index 00000000000000..fb4cb5d1b0a24c --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/mediatek,mt6320-regulator.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/mediatek,mt6320-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6320 Regulator + +maintainers: + - Akari Tsuyukusa + +description: + Regulator function of MT6320 PMIC. + +properties: + compatible: + items: + - const: mediatek,mt6320-regulator + +patternProperties: + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include + + mt6320_regulators: regulators { + compatible = "mediatek,mt6320-regulator"; + }; diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml index 4737e5f45d5410..1162d3f96f101a 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml @@ -19,7 +19,7 @@ description: IP Pairing - On MT8135 the pins of some SoC internal peripherals can be on the PMIC. + On MT6589 and MT8135 the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. In the binding description below the properties needed for bridging are marked with "IP Pairing". These are optional on SoCs which do not support @@ -31,6 +31,7 @@ properties: - items: - enum: - mediatek,mt2701-pwrap + - mediatek,mt6589-pwrap - mediatek,mt6765-pwrap - mediatek,mt6779-pwrap - mediatek,mt6795-pwrap diff --git a/arch/arm/boot/dts/mediatek/mt6320.dtsi b/arch/arm/boot/dts/mediatek/mt6320.dtsi new file mode 100644 index 00000000000000..3f2ae84f36fadc --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt6320.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2026 Akari Tsuyukusa + */ + +#include + +&pwrap { + pmic: mt6320 { + compatible = "mediatek,mt6320"; + + interrupt-parent = <&pio>; + interrupts = <43 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + pio6320: pinctrl { + compatible = "mediatek,mt6320-pinctrl"; + gpio-controller; + #gpio-cells = <2>; + }; + + power-controller { + compatible = "mediatek,mt6323-pwrc"; + }; + + rtc { + compatible = "mediatek,mt6320-rtc"; + }; + + mt6320keys: keys { + compatible = "mediatek,mt6320-keys"; + + power { + linux,keycodes = ; + wakeup-source; + }; + + home { + linux,keycodes = ; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi index af86a0f261488d..f9b13b960413c2 100644 --- a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi @@ -5,6 +5,7 @@ /dts-v1/; #include "mt6589.dtsi" +#include "mt6320.dtsi" / { #address-cells = <1>; diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index 1c627bbe78cf79..73ac7b4d2f157d 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -178,6 +179,20 @@ clock-names = "system-clk", "rtc-clk"; }; + pwrap: pwrap@1000f000 { + compatible = "mediatek,mt6589-pwrap"; + reg = <0x1000f000 0x1000>, + <0x11017000 0x1000>; + reg-names = "pwrap", "pwrap-bridge"; + interrupts = ; + clocks = <&infracfg CLK_INFRA_PMICSPI>, + <&infracfg CLK_INFRA_PMICWRAP>; + clock-names = "spi", "wrap"; + resets = <&infracfg MT6589_INFRA_PMIC_WRAP_RST>, + <&pericfg MT6589_PERI_PWRAP_BRIDGE_SW_RST>; + reset-names = "pwrap", "pwrap-bridge"; + }; + sysirq: interrupt-controller@10200100 { compatible = "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq"; diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig index 13cbcc326d43cf..c5b8951e0a548a 100644 --- a/arch/arm/configs/lenovo-blade_defconfig +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -80,6 +80,7 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_MTK=y CONFIG_EINT_MTK=y CONFIG_PINCTRL_MT6589=y +CONFIG_PINCTRL_MT6320=y ## GPIO @@ -105,14 +106,21 @@ CONFIG_MMC_MTK=y #CONFIG_TOUCHSCREEN_S7300=y # not ported ## PMIC -#CONFIG_MTK_PMIC_WRAP=y +CONFIG_MTK_PMIC_WRAP=y +CONFIG_MFD_MT6397=y +CONFIG_REGULATOR_MT6320=y -## Power ? -#CONFIG_POWER_RESET=y +## Power +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_MT6323=y ## Reset #CONFIG_RESET_CONTROLLER +## Input +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_MTK_PMIC=y + ## Battery ## Audio @@ -138,8 +146,8 @@ CONFIG_MMC_MTK=y #CONFIG_PWM_MTK_DISP=y ## RTC -#CONFIG_RTC_CLASS=y -#CONFIG_RTC_DRV_MT7622=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MT6397=y ## Android #CONFIG_ANDROID_BINDER_IPC=y diff --git a/drivers/input/keyboard/mtk-pmic-keys.c b/drivers/input/keyboard/mtk-pmic-keys.c index 061d48350df661..f8339b1211311e 100644 --- a/drivers/input/keyboard/mtk-pmic-keys.c +++ b/drivers/input/keyboard/mtk-pmic-keys.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -56,6 +57,17 @@ struct mtk_pmic_regs { u32 rst_lprst_mask; /* Long-press reset timeout bitmask */ }; +static const struct mtk_pmic_regs mt6320_regs = { + .keys_regs[MTK_PMIC_PWRKEY_INDEX] = + MTK_PMIC_KEYS_REGS(MT6320_CHRSTATUS, + 0x8, MT6320_INT_RSV, 0x10, MTK_PMIC_PWRKEY_RST), + .keys_regs[MTK_PMIC_HOMEKEY_INDEX] = + MTK_PMIC_KEYS_REGS(MT6320_OCSTATUS2, + 0x10, MT6320_INT_RSV, 0x8, MTK_PMIC_HOMEKEY_RST), + .pmic_rst_reg = MT6320_TOP_RST_MISC, + .rst_lprst_mask = MTK_PMIC_RST_DU_MASK, +}; + static const struct mtk_pmic_regs mt6397_regs = { .keys_regs[MTK_PMIC_PWRKEY_INDEX] = MTK_PMIC_KEYS_REGS(MT6397_CHRSTATUS, @@ -282,6 +294,9 @@ static DEFINE_SIMPLE_DEV_PM_OPS(mtk_pmic_keys_pm_ops, mtk_pmic_keys_suspend, static const struct of_device_id of_mtk_pmic_keys_match_tbl[] = { { + .compatible = "mediatek,mt6320-keys", + .data = &mt6320_regs, + }, { .compatible = "mediatek,mt6397-keys", .data = &mt6397_regs, }, { diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c index 5f8ed898890783..db2e1a954aee1c 100644 --- a/drivers/mfd/mt6397-core.c +++ b/drivers/mfd/mt6397-core.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -19,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -27,6 +29,9 @@ #include #include +#define MT6320_RTC_BASE 0xe000 +#define MT6320_RTC_SIZE 0x3f + #define MT6323_RTC_BASE 0x8000 #define MT6323_RTC_SIZE 0x40 @@ -45,6 +50,11 @@ #define MT6323_PWRC_BASE 0x8000 #define MT6323_PWRC_SIZE 0x40 +static const struct resource mt6320_rtc_resources[] = { + DEFINE_RES_MEM(MT6320_RTC_BASE, MT6320_RTC_SIZE), + DEFINE_RES_IRQ(MT6320_IRQ_RTC), +}; + static const struct resource mt6323_rtc_resources[] = { DEFINE_RES_MEM(MT6323_RTC_BASE, MT6323_RTC_SIZE), DEFINE_RES_IRQ(MT6323_IRQ_STATUS_RTC), @@ -70,6 +80,11 @@ static const struct resource mt6397_rtc_resources[] = { DEFINE_RES_IRQ(MT6397_IRQ_RTC), }; +static const struct resource mt6320_keys_resources[] = { + DEFINE_RES_IRQ_NAMED(MT6320_IRQ_PWRKEY, "powerkey"), + DEFINE_RES_IRQ_NAMED(MT6320_IRQ_HOMEKEY, "homekey"), +}; + static const struct resource mt6358_keys_resources[] = { DEFINE_RES_IRQ_NAMED(MT6358_IRQ_PWRKEY, "powerkey"), DEFINE_RES_IRQ_NAMED(MT6358_IRQ_HOMEKEY, "homekey"), @@ -123,6 +138,23 @@ static const struct resource mt6323_pwrc_resources[] = { DEFINE_RES_MEM(MT6323_PWRC_BASE, MT6323_PWRC_SIZE), }; +static const struct mfd_cell mt6320_devs[] = { + { + .name = "mt6320-rtc", + .num_resources = ARRAY_SIZE(mt6320_rtc_resources), + .resources = mt6320_rtc_resources, + .of_compatible = "mediatek,mt6320-rtc", + }, { + .name = "mt6320-regulator", + .of_compatible = "mediatek,mt6320-regulator" + }, { + .name = "mtk-pmic-keys", + .num_resources = ARRAY_SIZE(mt6320_keys_resources), + .resources = mt6320_keys_resources, + .of_compatible = "mediatek,mt6320-keys", + }, +}; + static const struct mfd_cell mt6323_devs[] = { { .name = "mt6323-rtc", @@ -287,6 +319,14 @@ struct chip_data { int (*irq_init)(struct mt6397_chip *chip); }; +static const struct chip_data mt6320_core = { + .cid_addr = MT6320_CID, + .cid_shift = 0, + .cells = mt6320_devs, + .cell_size = ARRAY_SIZE(mt6320_devs), + .irq_init = mt6397_irq_init, +}; + static const struct chip_data mt6323_core = { .cid_addr = MT6323_CID, .cid_shift = 0, @@ -297,7 +337,7 @@ static const struct chip_data mt6323_core = { static const struct chip_data mt6328_core = { .cid_addr = MT6328_HWCID, - .cid_shift = 0, + .cid_shift = 8, .cells = mt6328_devs, .cell_size = ARRAY_SIZE(mt6328_devs), .irq_init = mt6397_irq_init, @@ -313,7 +353,7 @@ static const struct chip_data mt6357_core = { static const struct chip_data mt6331_mt6332_core = { .cid_addr = MT6331_HWCID, - .cid_shift = 0, + .cid_shift = 8, .cells = mt6331_mt6332_devs, .cell_size = ARRAY_SIZE(mt6331_mt6332_devs), .irq_init = mt6397_irq_init, @@ -399,6 +439,9 @@ static int mt6397_probe(struct platform_device *pdev) static const struct of_device_id mt6397_of_match[] = { { + .compatible = "mediatek,mt6320", + .data = &mt6320_core, + }, { .compatible = "mediatek,mt6323", .data = &mt6323_core, }, { diff --git a/drivers/mfd/mt6397-irq.c b/drivers/mfd/mt6397-irq.c index badc614b434527..aa913a496fd976 100644 --- a/drivers/mfd/mt6397-irq.c +++ b/drivers/mfd/mt6397-irq.c @@ -9,6 +9,8 @@ #include #include #include +#include +#include #include #include #include @@ -176,6 +178,12 @@ int mt6397_irq_init(struct mt6397_chip *chip) mutex_init(&chip->irqlock); switch (chip->chip_id) { + case MT6320_CHIP_ID: + chip->int_con[0] = MT6320_INT_CON0; + chip->int_con[1] = MT6320_INT_CON1; + chip->int_status[0] = MT6320_INT_STATUS0; + chip->int_status[1] = MT6320_INT_STATUS1; + break; case MT6323_CHIP_ID: chip->int_con[0] = MT6323_INT_CON0; chip->int_con[1] = MT6323_INT_CON1; diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 8d9f84701793ac..b227df6df76dfd 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -307,6 +307,13 @@ config PINCTRL_MT8516 select PINCTRL_MTK # For PMIC +config PINCTRL_MT6320 + bool "MediaTek MT6320 pin control" + depends on MFD_MT6397 || COMPILE_TEST + depends on OF + default MFD_MT6397 + select PINCTRL_MTK + config PINCTRL_MT6397 bool "MediaTek MT6397 pin control" depends on MFD_MT6397 || COMPILE_TEST diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6320.c b/drivers/pinctrl/mediatek/pinctrl-mt6320.c new file mode 100644 index 00000000000000..319190676ad4f4 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt6320.c @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Hongzhou.Yang + * + * Copyright (c) 2026 Akari Tsuyukusa + * + * MediaTek MT6320 PMIC Pinctrl Driver based on pinctrl-mt6397.c + */ + +#include +#include +#include +#include +#include +#include + +#include "pinctrl-mtk-common.h" +#include "pinctrl-mtk-mt6320.h" + +#define MT6320_PIN_REG_BASE 0xc000 + +static const struct mtk_pinctrl_devdata mt6320_pinctrl_data = { + .pins = mtk_pins_mt6320, + .npins = ARRAY_SIZE(mtk_pins_mt6320), + .dir_offset = (MT6320_PIN_REG_BASE + 0x000), + .ies_offset = MTK_PINCTRL_NOT_SUPPORT, + .smt_offset = MTK_PINCTRL_NOT_SUPPORT, + .pullen_offset = (MT6320_PIN_REG_BASE + 0x020), + .pullsel_offset = (MT6320_PIN_REG_BASE + 0x040), + .dout_offset = (MT6320_PIN_REG_BASE + 0x080), + .din_offset = (MT6320_PIN_REG_BASE + 0x0a0), + .pinmux_offset = (MT6320_PIN_REG_BASE + 0x0c0), + .type1_start = 49, + .type1_end = 49, + .port_shf = 3, + .port_mask = 0x3, + .port_align = 2, + .mode_mask = 0xf, + .mode_per_reg = 5, + .mode_shf = 4, +}; + +static int mt6320_pinctrl_probe(struct platform_device *pdev) +{ + struct mt6397_chip *mt6320; + + mt6320 = dev_get_drvdata(pdev->dev.parent); + return mtk_pctrl_init(pdev, &mt6320_pinctrl_data, mt6320->regmap); +} + +static const struct of_device_id mt6320_pctrl_match[] = { + { .compatible = "mediatek,mt6320-pinctrl", }, + { }, +}; + +static struct platform_driver mtk_pinctrl_driver = { + .probe = mt6320_pinctrl_probe, + .driver = { + .name = "mediatek-mt6320-pinctrl", + .of_match_table = mt6320_pctrl_match, + }, +}; + +builtin_platform_driver(mtk_pinctrl_driver); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6320.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6320.h new file mode 100644 index 00000000000000..1525f3f88c387e --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6320.h @@ -0,0 +1,368 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Akari Tsuyukusa + */ + +#ifndef __PINCTRL_MTK_MT6320_H +#define __PINCTRL_MTK_MT6320_H + +#include +#include "pinctrl-mtk-common.h" + +static const struct mtk_desc_pin mtk_pins_mt6320[] = { + MTK_PIN(PINCTRL_PIN(0, "GPIO0"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "INT") + ), + MTK_PIN(PINCTRL_PIN(1, "GPIO1"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "SRCVOLTEN") + ), + MTK_PIN(PINCTRL_PIN(2, "GPIO2"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "SRCLKEN_PERI") + ), + MTK_PIN(PINCTRL_PIN(3, "GPIO3"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "SRCLKEN_MD2") + ), + MTK_PIN(PINCTRL_PIN(4, "GPIO4"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "RTC_32K1V8") + ), + MTK_PIN(PINCTRL_PIN(5, "GPIO5"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "WRAP_EVENT") + ), + MTK_PIN(PINCTRL_PIN(6, "GPIO6"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "SPI_CLK") + ), + MTK_PIN(PINCTRL_PIN(7, "GPIO7"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "SPI_CSN") + ), + MTK_PIN(PINCTRL_PIN(8, "GPIO8"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "SPI_MOSI") + ), + MTK_PIN(PINCTRL_PIN(9, "GPIO9"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "SPI_MISO") + ), + MTK_PIN(PINCTRL_PIN(10, "GPIO10"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "ADC_CK") + ), + MTK_PIN(PINCTRL_PIN(11, "GPIO11"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "ADC_WS") + ), + MTK_PIN(PINCTRL_PIN(12, "GPIO12"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "ADC_DAT") + ), + MTK_PIN(PINCTRL_PIN(13, "GPIO13"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "DAC_CK") + ), + MTK_PIN(PINCTRL_PIN(14, "GPIO14"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "DAC_WS") + ), + MTK_PIN(PINCTRL_PIN(15, "GPIO15"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "DAC_DAT") + ), + MTK_PIN(PINCTRL_PIN(16, "GPIO16"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 10), + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "COL0_USBDL"), + MTK_FUNCTION(2, "EINT10"), + MTK_FUNCTION(3, "PWM1_3X") + ), + MTK_PIN(PINCTRL_PIN(17, "GPIO17"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 11), + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "COL1"), + MTK_FUNCTION(2, "EINT11"), + MTK_FUNCTION(3, "SCL0_2X") + ), + MTK_PIN(PINCTRL_PIN(18, "GPIO18"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 12), + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "COL2"), + MTK_FUNCTION(2, "EINT12"), + MTK_FUNCTION(3, "SDA0_2X") + ), + MTK_PIN(PINCTRL_PIN(19, "GPIO19"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 13), + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "COL3"), + MTK_FUNCTION(2, "EINT13"), + MTK_FUNCTION(3, "SCL1_2X") + ), + MTK_PIN(PINCTRL_PIN(20, "GPIO20"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 14), + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "COL4"), + MTK_FUNCTION(2, "EINT14"), + MTK_FUNCTION(3, "SDA1_2X") + ), + MTK_PIN(PINCTRL_PIN(21, "GPIO21"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 15), + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "COL5"), + MTK_FUNCTION(2, "EINT15"), + MTK_FUNCTION(3, "SCL2_2X") + ), + MTK_PIN(PINCTRL_PIN(22, "GPIO22"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 16), + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "COL6"), + MTK_FUNCTION(2, "EINT16"), + MTK_FUNCTION(3, "SDA2_2X"), + MTK_FUNCTION(4, "GPIO32K_0"), + MTK_FUNCTION(5, "GPIO26M_0") + ), + MTK_PIN(PINCTRL_PIN(23, "GPIO23"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 17), + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(1, "COL7"), + MTK_FUNCTION(2, "EINT17"), + MTK_FUNCTION(3, "PWM2_3X"), + MTK_FUNCTION(4, "GPIO32K_1"), + MTK_FUNCTION(5, "GPIO26M_1") + ), + MTK_PIN(PINCTRL_PIN(24, "GPIO24"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 18), + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "ROW0"), + MTK_FUNCTION(2, "EINT18"), + MTK_FUNCTION(3, "SCL0_3X") + ), + MTK_PIN(PINCTRL_PIN(25, "GPIO25"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 19), + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "ROW1"), + MTK_FUNCTION(2, "EINT19"), + MTK_FUNCTION(3, "SDA0_3X") + ), + MTK_PIN(PINCTRL_PIN(26, "GPIO26"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 20), + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "ROW2"), + MTK_FUNCTION(2, "EINT20"), + MTK_FUNCTION(3, "SCL1_3X") + ), + MTK_PIN(PINCTRL_PIN(27, "GPIO27"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 21), + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "ROW3"), + MTK_FUNCTION(2, "EINT21"), + MTK_FUNCTION(3, "SDA1_3X") + ), + MTK_PIN(PINCTRL_PIN(28, "GPIO28"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 22), + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "ROW4"), + MTK_FUNCTION(2, "EINT22"), + MTK_FUNCTION(3, "SCL2_3X") + ), + MTK_PIN(PINCTRL_PIN(29, "GPIO29"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 23), + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "ROW5"), + MTK_FUNCTION(2, "EINT23"), + MTK_FUNCTION(3, "SDA2_3X") + ), + MTK_PIN(PINCTRL_PIN(30, "GPIO30"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 24), + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "ROW6"), + MTK_FUNCTION(2, "EINT24"), + MTK_FUNCTION(3, "PWM3_3X"), + MTK_FUNCTION(4, "GPIO32K_2"), + MTK_FUNCTION(5, "GPIO26M_2") + ), + MTK_PIN(PINCTRL_PIN(31, "GPIO31"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 3), + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "ROW7"), + MTK_FUNCTION(2, "EINT3"), + MTK_FUNCTION(4, "GPIO32K_3"), + MTK_FUNCTION(5, "GPIO26M_3") + ), + MTK_PIN(PINCTRL_PIN(32, "GPIO32"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 4), + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "PWM1"), + MTK_FUNCTION(2, "EINT4"), + MTK_FUNCTION(4, "GPIO32K_4"), + MTK_FUNCTION(5, "GPIO26M_4") + ), + MTK_PIN(PINCTRL_PIN(33, "GPIO33"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 5), + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "PWM2"), + MTK_FUNCTION(2, "EINT5"), + MTK_FUNCTION(4, "GPIO32K_5"), + MTK_FUNCTION(5, "GPIO26M_5") + ), + MTK_PIN(PINCTRL_PIN(34, "GPIO34"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 6), + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "PWM3"), + MTK_FUNCTION(2, "EINT6"), + MTK_FUNCTION(3, "COL0"), + MTK_FUNCTION(4, "GPIO32K_6"), + MTK_FUNCTION(5, "GPIO26M_6") + ), + MTK_PIN(PINCTRL_PIN(35, "GPIO35"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 7), + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "SCL0"), + MTK_FUNCTION(2, "EINT7"), + MTK_FUNCTION(3, "PWM1_2X") + ), + MTK_PIN(PINCTRL_PIN(36, "GPIO36"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 8), + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "SDA0"), + MTK_FUNCTION(2, "EINT8") + ), + MTK_PIN(PINCTRL_PIN(37, "GPIO37"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 9), + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "SCL1"), + MTK_FUNCTION(2, "EINT9"), + MTK_FUNCTION(3, "PWM2_2X") + ), + MTK_PIN(PINCTRL_PIN(38, "GPIO38"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 0), + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "SDA1"), + MTK_FUNCTION(2, "EINT0") + ), + MTK_PIN(PINCTRL_PIN(39, "GPIO39"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 1), + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "SCL2"), + MTK_FUNCTION(2, "EINT1"), + MTK_FUNCTION(3, "PWM3_2X") + ), + MTK_PIN(PINCTRL_PIN(40, "GPIO40"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 2), + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "SDA2"), + MTK_FUNCTION(2, "EINT2") + ), + MTK_PIN(PINCTRL_PIN(41, "GPIO41"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "SIM1_AP_SCLK") + ), + MTK_PIN(PINCTRL_PIN(42, "GPIO42"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "SIM1_AP_SRST") + ), + MTK_PIN(PINCTRL_PIN(43, "GPIO43"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "SIM2_AP_SCLK") + ), + MTK_PIN(PINCTRL_PIN(44, "GPIO44"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "SIM2_AP_SRST") + ), + MTK_PIN(PINCTRL_PIN(45, "GPIO45"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "SIMLS1_SCLK") + ), + MTK_PIN(PINCTRL_PIN(46, "GPIO46"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "SIMLS1_SRST") + ), + MTK_PIN(PINCTRL_PIN(47, "GPIO47"), + NULL, "mt6320", + MTK_EINT_FUNCTION(5, 10), + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "SIMLS2_SCLK"), + MTK_FUNCTION(5, "EINT10") + ), + MTK_PIN(PINCTRL_PIN(48, "GPIO48"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "SIMLS2_SRST") + ), +}; + +#endif /* __PINCTRL_MTK_MT6320_H */ diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 6d8988387da459..442484847fa93e 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -864,6 +864,15 @@ config REGULATOR_MT6315 This driver supports the control of different power rails of device through regulator interface. +config REGULATOR_MT6320 + tristate "MediaTek MT6320 PMIC" + depends on MFD_MT6397 + help + Say y here to select this option to enable the power regulator of + MediaTek MT6320 PMIC. + This driver supports the control of different power rails of device + through regulator interface. + config REGULATOR_MT6323 tristate "MediaTek MT6323 PMIC" depends on MFD_MT6397 diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index c0bc7a0f4e6709..e75a5565813f0c 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -103,6 +103,7 @@ obj-$(CONFIG_REGULATOR_MP886X) += mp886x.o obj-$(CONFIG_REGULATOR_MPQ7920) += mpq7920.o obj-$(CONFIG_REGULATOR_MT6311) += mt6311-regulator.o obj-$(CONFIG_REGULATOR_MT6315) += mt6315-regulator.o +obj-$(CONFIG_REGULATOR_MT6320) += mt6320-regulator.o obj-$(CONFIG_REGULATOR_MT6323) += mt6323-regulator.o obj-$(CONFIG_REGULATOR_MT6331) += mt6331-regulator.o obj-$(CONFIG_REGULATOR_MT6332) += mt6332-regulator.o diff --git a/drivers/regulator/mt6320-regulator.c b/drivers/regulator/mt6320-regulator.c new file mode 100644 index 00000000000000..a590cbf341879d --- /dev/null +++ b/drivers/regulator/mt6320-regulator.c @@ -0,0 +1,388 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026 Akari Tsuyukusa + * + * based on mt6320-regulator.c + * Copyright (c) 2016 MediaTek Inc. + * Author: Chen Zhong + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* TODO: are they in mt6320? */ +#define MT6320_LDO_MODE_NORMAL 0 +#define MT6320_LDO_MODE_LP 1 + +/* + * MT6320 regulators' information + * + * @desc: standard fields of regulator description. + * @qi: Mask for query enable signal status of regulators + * @vselon_reg: Register sections for hardware control mode of bucks + * @vselctrl_reg: Register for controlling the buck control mode. + * @vselctrl_mask: Mask for query buck's voltage control mode. + */ +struct mt6320_regulator_info { + struct regulator_desc desc; + u32 qi; + u32 vselon_reg; + u32 vselctrl_reg; + u32 vselctrl_mask; + u32 modeset_reg; + u32 modeset_mask; +}; + +/* +TODO: check .enable_mask, .vselctrl_mask +*/ + +#define MT6320_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \ + vosel, vosel_mask, voselon, vosel_ctrl) \ +[MT6320_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .ops = &mt6320_volt_range_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MT6320_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = (max - min)/step + 1, \ + .linear_ranges = volt_ranges, \ + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ + .vsel_reg = vosel, \ + .vsel_mask = vosel_mask, \ + .enable_reg = enreg, \ + .enable_mask = BIT(0), \ + }, \ + .qi = BIT(13), \ + .vselon_reg = voselon, \ + .vselctrl_reg = vosel_ctrl, \ + .vselctrl_mask = BIT(1), \ +} + +#define MT6320_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ + vosel_mask, _modeset_reg, _modeset_mask) \ +[MT6320_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .ops = &mt6320_volt_table_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MT6320_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = ARRAY_SIZE(ldo_volt_table), \ + .volt_table = ldo_volt_table, \ + .vsel_reg = vosel, \ + .vsel_mask = vosel_mask, \ + .enable_reg = enreg, \ + .enable_mask = BIT(enbit), \ + }, \ + .qi = BIT(15), \ + .modeset_reg = _modeset_reg, \ + .modeset_mask = _modeset_mask, \ +} + +#define MT6320_REG_FIXED(match, vreg, enreg, enbit, volt, \ + _modeset_reg, _modeset_mask) \ +[MT6320_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .ops = &mt6320_volt_fixed_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MT6320_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = 1, \ + .enable_reg = enreg, \ + .enable_mask = BIT(enbit), \ + .min_uV = volt, \ + }, \ + .qi = BIT(15), \ + .modeset_reg = _modeset_reg, \ + .modeset_mask = _modeset_mask, \ +} + +static const struct linear_range buck_volt_range1[] = { + REGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250), +}; + +static const struct linear_range buck_volt_range2[] = { + REGULATOR_LINEAR_RANGE(1500000, 0, 0x1f, 20000), +}; + +static const struct linear_range buck_volt_range3[] = { + REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000), +}; + +static const struct linear_range buck_volt_range4[] = { + REGULATOR_LINEAR_RANGE(1050000, 0, 0x1f, 25000), +}; + +static const unsigned int ldo_volt_table1[] = { + 1800000, 3300000, +}; + +static const unsigned int ldo_volt_table2[] = { + 3000000, 3300000, +}; + +static const unsigned int ldo_volt_table3[] = { + 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000, +}; + +static const unsigned int ldo_volt_table4[] = { + 1200000, 1100000, 1000000, 900000, +}; + +static const unsigned int ldo_volt_table5[] = { + 1800000, 2800000, +}; + +static const unsigned int ldo_volt_table6[] = { + 1800000, 2500000, +}; + +static const unsigned int ldo_volt_table7[] = { + 1500000, 1800000, 2500000, 2800000, +}; + +static int mt6320_get_status(struct regulator_dev *rdev) +{ + int ret; + u32 regval; + struct mt6320_regulator_info *info = rdev_get_drvdata(rdev); + + ret = regmap_read(rdev->regmap, info->desc.enable_reg, ®val); + if (ret != 0) { + dev_err(&rdev->dev, "Failed to get enable reg: %d\n", ret); + return ret; + } + + return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF; +} + +static int mt6320_ldo_set_mode(struct regulator_dev *rdev, unsigned int mode) +{ + int ret, val = 0; + struct mt6320_regulator_info *info = rdev_get_drvdata(rdev); + + if (!info->modeset_mask) { + dev_err(&rdev->dev, "regulator %s doesn't support set_mode\n", + info->desc.name); + return -EINVAL; + } + + switch (mode) { + case REGULATOR_MODE_STANDBY: + val = MT6320_LDO_MODE_LP; + break; + case REGULATOR_MODE_NORMAL: + val = MT6320_LDO_MODE_NORMAL; + break; + default: + return -EINVAL; + } + + val <<= ffs(info->modeset_mask) - 1; + + ret = regmap_update_bits(rdev->regmap, info->modeset_reg, + info->modeset_mask, val); + + return ret; +} + +static unsigned int mt6320_ldo_get_mode(struct regulator_dev *rdev) +{ + unsigned int val; + unsigned int mode; + int ret; + struct mt6320_regulator_info *info = rdev_get_drvdata(rdev); + + if (!info->modeset_mask) { + dev_err(&rdev->dev, "regulator %s doesn't support get_mode\n", + info->desc.name); + return -EINVAL; + } + + ret = regmap_read(rdev->regmap, info->modeset_reg, &val); + if (ret < 0) + return ret; + + val &= info->modeset_mask; + val >>= ffs(info->modeset_mask) - 1; + + if (val & 0x1) + mode = REGULATOR_MODE_STANDBY; + else + mode = REGULATOR_MODE_NORMAL; + + return mode; +} + +static const struct regulator_ops mt6320_volt_range_ops = { + .list_voltage = regulator_list_voltage_linear_range, + .map_voltage = regulator_map_voltage_linear_range, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_time_sel = regulator_set_voltage_time_sel, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .get_status = mt6320_get_status, +}; + +static const struct regulator_ops mt6320_volt_table_ops = { + .list_voltage = regulator_list_voltage_table, + .map_voltage = regulator_map_voltage_iterate, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_time_sel = regulator_set_voltage_time_sel, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .get_status = mt6320_get_status, + .set_mode = mt6320_ldo_set_mode, + .get_mode = mt6320_ldo_get_mode, +}; + +static const struct regulator_ops mt6320_volt_fixed_ops = { + .list_voltage = regulator_list_voltage_linear, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .get_status = mt6320_get_status, + .set_mode = mt6320_ldo_set_mode, + .get_mode = mt6320_ldo_get_mode, +}; + +/* The array is indexed by id(MT6320_ID_XXX) */ +static struct mt6320_regulator_info mt6320_regulators[] = { + +/* + BUCK_VPROC + BUCK_VSRAM + BUCK_VCORE + BUCK_VM + BUCK_VIO18 + BUCK_VPA + BUCK_VRF18 + BUCK_VRF18_2 + + //Digital LDO + LDO_VIO28 + LDO_VUSB + LDO_VMC1 + LDO_VMCH1 + LDO_VEMC_3V3 + LDO_VEMC_1V8 + LDO_VGP1 + LDO_VGP2 + LDO_VGP3 + LDO_VGP4 + LDO_VGP5 + LDO_VGP6 + LDO_VSIM1 + LDO_VSIM2 + LDO_VIBR + LDO_VRTC + LDO_VAST + + //Analog LDO + LDO_VRF28 + LDO_VRF28_2 + LDO_VTCXO + LDO_VTCXO_2 + LDO_VA + LDO_VA28 + LDO_VCAMA +*/ +}; + +static int mt6320_set_buck_vosel_reg(struct platform_device *pdev) +{ + struct mt6397_chip *mt6320 = dev_get_drvdata(pdev->dev.parent); + int i; + u32 regval; + + for (i = 0; i < MT6320_MAX_REGULATOR; i++) { + if (mt6320_regulators[i].vselctrl_reg) { + if (regmap_read(mt6320->regmap, + mt6320_regulators[i].vselctrl_reg, + ®val) < 0) { + dev_err(&pdev->dev, + "Failed to read buck ctrl\n"); + return -EIO; + } + + if (regval & mt6320_regulators[i].vselctrl_mask) { + mt6320_regulators[i].desc.vsel_reg = + mt6320_regulators[i].vselon_reg; + } + } + } + + return 0; +} + +static int mt6320_regulator_probe(struct platform_device *pdev) +{ + struct mt6397_chip *mt6320 = dev_get_drvdata(pdev->dev.parent); + struct regulator_config config = {}; + struct regulator_dev *rdev; + int i; + u32 reg_value; + + /* Query buck controller to select activated voltage register part */ + if (mt6320_set_buck_vosel_reg(pdev)) + return -EIO; + + /* Read PMIC chip revision to update constraints and voltage table */ + if (regmap_read(mt6320->regmap, MT6320_CID, ®_value) < 0) { + dev_err(&pdev->dev, "Failed to read Chip ID\n"); + return -EIO; + } + dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value); + + for (i = 0; i < MT6320_MAX_REGULATOR; i++) { + config.dev = &pdev->dev; + config.driver_data = &mt6320_regulators[i]; + config.regmap = mt6320->regmap; + rdev = devm_regulator_register(&pdev->dev, + &mt6320_regulators[i].desc, &config); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register %s\n", + mt6320_regulators[i].desc.name); + return PTR_ERR(rdev); + } + } + return 0; +} + +static const struct platform_device_id mt6320_platform_ids[] = { + {"mt6320-regulator", 0}, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(platform, mt6320_platform_ids); + +static struct platform_driver mt6320_regulator_driver = { + .driver = { + .name = "mt6320-regulator", + .probe_type = PROBE_PREFER_ASYNCHRONOUS, + }, + .probe = mt6320_regulator_probe, + .id_table = mt6320_platform_ids, +}; + +module_platform_driver(mt6320_regulator_driver); + +MODULE_AUTHOR("Akari Tsuyukusa "); +MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6320 PMIC"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/rtc/rtc-mt6397.c b/drivers/rtc/rtc-mt6397.c index 692c00ff544b22..8170eeb33e7eb8 100644 --- a/drivers/rtc/rtc-mt6397.c +++ b/drivers/rtc/rtc-mt6397.c @@ -331,6 +331,7 @@ static const struct mtk_rtc_data mt6397_rtc_data = { }; static const struct of_device_id mt6397_rtc_of_match[] = { + { .compatible = "mediatek,mt6320-rtc", .data = &mt6397_rtc_data }, { .compatible = "mediatek,mt6323-rtc", .data = &mt6397_rtc_data }, { .compatible = "mediatek,mt6357-rtc", .data = &mt6358_rtc_data }, { .compatible = "mediatek,mt6358-rtc", .data = &mt6358_rtc_data }, diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c index 0bcd8582637550..bbf8a7f2d6a39b 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -17,15 +17,31 @@ #define PWRAP_POLL_DELAY_US 10 #define PWRAP_POLL_TIMEOUT_US 10000 -#define PWRAP_MT8135_BRIDGE_IORD_ARB_EN 0x4 -#define PWRAP_MT8135_BRIDGE_WACS3_EN 0x10 -#define PWRAP_MT8135_BRIDGE_INIT_DONE3 0x14 -#define PWRAP_MT8135_BRIDGE_WACS4_EN 0x24 -#define PWRAP_MT8135_BRIDGE_INIT_DONE4 0x28 -#define PWRAP_MT8135_BRIDGE_INT_EN 0x38 -#define PWRAP_MT8135_BRIDGE_TIMER_EN 0x48 -#define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x50 -#define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54 +/* MT6589 and MT8135 specific PWARP Bridge registers */ +#define PWRAP_BRIDGE_IARB_INIT 0x0 +#define PWRAP_BRIDGE_IORD_ARB_EN 0x4 +#define PWRAP_BRIDGE_IARB_STA0 0x8 +#define PWRAP_BRIDGE_IARB_STA1 0xc +#define PWRAP_BRIDGE_WACS3_EN 0x10 +#define PWRAP_BRIDGE_INIT_DONE3 0x14 +#define PWRAP_BRIDGE_WACS3_CMD 0x18 +#define PWRAP_BRIDGE_WACS3_RDATA 0x1c +#define PWRAP_BRIDGE_WACS3_VLDCLR 0x20 +#define PWRAP_BRIDGE_WACS4_EN 0x24 +#define PWRAP_BRIDGE_INIT_DONE4 0x28 +#define PWRAP_BRIDGE_WACS4_CMD 0x2c +#define PWRAP_BRIDGE_WACS4_RDATA 0x30 +#define PWRAP_BRIDGE_WACS4_VLDCLR 0x34 +#define PWRAP_BRIDGE_INT_EN 0x38 +#define PWRAP_BRIDGE_INT_FLG_RAW 0x3c +#define PWRAP_BRIDGE_INT_FLG 0x40 +#define PWRAP_BRIDGE_INT_CLR 0x44 +#define PWRAP_BRIDGE_TIMER_EN 0x48 +#define PWRAP_BRIDGE_TIMER_STA 0x4c +#define PWRAP_BRIDGE_WDT_UNIT 0x50 +#define PWRAP_BRIDGE_WDT_SRC_EN 0x54 +#define PWRAP_BRIDGE_WDT_FLG 0x58 +#define PWRAP_BRIDGE_DEBUG_INT_SEL 0x5c /* macro for wrapper status */ #define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff) @@ -100,6 +116,24 @@ enum dew_regs { PWRAP_DEW_CIPHER_MODE, PWRAP_DEW_CIPHER_SWRST, + /* MT6320 only regs */ + PWRAP_DEW_CIPHER_IV0, + PWRAP_DEW_CIPHER_IV1, + PWRAP_DEW_CIPHER_IV2, + PWRAP_DEW_CIPHER_IV3, + PWRAP_DEW_CIPHER_IV4, + PWRAP_DEW_CIPHER_IV5, + + /* MT6320 and MT6397 only regs */ + PWRAP_DEW_EVENT_OUT_EN, + PWRAP_DEW_EVENT_SRC_EN, + PWRAP_DEW_EVENT_SRC, + PWRAP_DEW_EVENT_FLAG, + PWRAP_DEW_MON_FLAG_SEL, + PWRAP_DEW_EVENT_TEST, + PWRAP_DEW_CIPHER_LOAD, + PWRAP_DEW_CIPHER_START, + /* MT6323 only regs */ PWRAP_DEW_CIPHER_EN, PWRAP_DEW_RDDMY_NO, @@ -142,16 +176,34 @@ enum dew_regs { PWRAP_DEW_RG_WDATA_MASK, PWRAP_DEW_RG_SPI_RECORD_CLR, PWRAP_DEW_RG_CMD_ALERT_CLR, +}; - /* MT6397 only regs */ - PWRAP_DEW_EVENT_OUT_EN, - PWRAP_DEW_EVENT_SRC_EN, - PWRAP_DEW_EVENT_SRC, - PWRAP_DEW_EVENT_FLAG, - PWRAP_DEW_MON_FLAG_SEL, - PWRAP_DEW_EVENT_TEST, - PWRAP_DEW_CIPHER_LOAD, - PWRAP_DEW_CIPHER_START, +static const u32 mt6320_regs[] = { + [PWRAP_DEW_EVENT_OUT_EN] = 0x0000, + [PWRAP_DEW_DIO_EN] = 0x0002, + [PWRAP_DEW_EVENT_SRC_EN] = 0x0004, + [PWRAP_DEW_EVENT_SRC] = 0x0006, + [PWRAP_DEW_EVENT_FLAG] = 0x0008, + [PWRAP_DEW_READ_TEST] = 0x000a, + [PWRAP_DEW_WRITE_TEST] = 0x000c, + [PWRAP_DEW_CRC_EN] = 0x000e, + [PWRAP_DEW_CRC_VAL] = 0x0010, + [PWRAP_DEW_MON_GRP_SEL] = 0x0012, + [PWRAP_DEW_MON_FLAG_SEL] = 0x0014, + [PWRAP_DEW_EVENT_TEST] = 0x0016, + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0018, + [PWRAP_DEW_CIPHER_IV_SEL] = 0x001a, + [PWRAP_DEW_CIPHER_LOAD] = 0x001c, + [PWRAP_DEW_CIPHER_START] = 0x001e, + [PWRAP_DEW_CIPHER_RDY] = 0x0020, + [PWRAP_DEW_CIPHER_MODE] = 0x0022, + [PWRAP_DEW_CIPHER_SWRST] = 0x0024, + [PWRAP_DEW_CIPHER_IV0] = 0x0026, + [PWRAP_DEW_CIPHER_IV1] = 0x0028, + [PWRAP_DEW_CIPHER_IV2] = 0x002a, + [PWRAP_DEW_CIPHER_IV3] = 0x002c, + [PWRAP_DEW_CIPHER_IV4] = 0x002e, + [PWRAP_DEW_CIPHER_IV5] = 0x0030, }; static const u32 mt6323_regs[] = { @@ -386,6 +438,22 @@ enum pwrap_regs { PWRAP_EINT_STA1_ADR, PWRAP_SWINF_2_WDATA_31_0, PWRAP_SWINF_2_RDATA_31_0, + PWRAP_DVFS_ADR0, + PWRAP_DVFS_WDATA0, + PWRAP_DVFS_ADR1, + PWRAP_DVFS_WDATA1, + PWRAP_DVFS_ADR2, + PWRAP_DVFS_WDATA2, + PWRAP_DVFS_ADR3, + PWRAP_DVFS_WDATA3, + PWRAP_DVFS_ADR4, + PWRAP_DVFS_WDATA4, + PWRAP_DVFS_ADR5, + PWRAP_DVFS_WDATA5, + PWRAP_DVFS_ADR6, + PWRAP_DVFS_WDATA6, + PWRAP_DVFS_ADR7, + PWRAP_DVFS_WDATA7, /* MT2701 only regs */ PWRAP_ADC_CMD_ADDR, @@ -394,6 +462,24 @@ enum pwrap_regs { PWRAP_ADC_RDATA_ADDR1, PWRAP_ADC_RDATA_ADDR2, + /* MT6589 only regs */ + PWRAP_CIPHER_IV0, + PWRAP_CIPHER_IV1, + PWRAP_CIPHER_IV2, + + /* MT6589 and MT8135 only regs */ + PWRAP_CSHEXT, + PWRAP_EVENT_IN_EN, + PWRAP_EVENT_DST_EN, + PWRAP_RRARB_INIT, + PWRAP_RRARB_EN, + PWRAP_RRARB_STA0, + PWRAP_RRARB_STA1, + PWRAP_EVENT_STA, + PWRAP_EVENT_STACLR, + PWRAP_CIPHER_LOAD, + PWRAP_CIPHER_START, + /* MT7622 only regs */ PWRAP_STA, PWRAP_CLR, @@ -422,38 +508,9 @@ enum pwrap_regs { PWRAP_DVFS_STEP_CTRL2, PWRAP_SPI2_CTRL, - /* MT8135 only regs */ - PWRAP_CSHEXT, - PWRAP_EVENT_IN_EN, - PWRAP_EVENT_DST_EN, - PWRAP_RRARB_INIT, - PWRAP_RRARB_EN, - PWRAP_RRARB_STA0, - PWRAP_RRARB_STA1, - PWRAP_EVENT_STA, - PWRAP_EVENT_STACLR, - PWRAP_CIPHER_LOAD, - PWRAP_CIPHER_START, - /* MT8173 only regs */ PWRAP_RDDMY, PWRAP_SI_CK_CON, - PWRAP_DVFS_ADR0, - PWRAP_DVFS_WDATA0, - PWRAP_DVFS_ADR1, - PWRAP_DVFS_WDATA1, - PWRAP_DVFS_ADR2, - PWRAP_DVFS_WDATA2, - PWRAP_DVFS_ADR3, - PWRAP_DVFS_WDATA3, - PWRAP_DVFS_ADR4, - PWRAP_DVFS_WDATA4, - PWRAP_DVFS_ADR5, - PWRAP_DVFS_WDATA5, - PWRAP_DVFS_ADR6, - PWRAP_DVFS_WDATA6, - PWRAP_DVFS_ADR7, - PWRAP_DVFS_WDATA7, PWRAP_SPMINF_STA, PWRAP_CIPHER_EN, @@ -569,6 +626,98 @@ static const int mt2701_regs[] = { [PWRAP_ADC_RDATA_ADDR2] = 0x154, }; +static const int mt6589_regs[] = { + [PWRAP_MUX_SEL] = 0x0, + [PWRAP_WRAP_EN] = 0x4, + [PWRAP_DIO_EN] = 0x8, + [PWRAP_SIDLY] = 0xc, + [PWRAP_CSHEXT] = 0x10, + [PWRAP_CSHEXT_WRITE] = 0x14, + [PWRAP_CSHEXT_READ] = 0x18, + [PWRAP_CSLEXT_START] = 0x1c, + [PWRAP_CSLEXT_END] = 0x20, + [PWRAP_STAUPD_PRD] = 0x24, + [PWRAP_STAUPD_GRPEN] = 0x28, + [PWRAP_STAUPD_MAN_TRIG] = 0x2c, + [PWRAP_STAUPD_STA] = 0x30, + [PWRAP_EVENT_IN_EN] = 0x34, + [PWRAP_EVENT_DST_EN] = 0x38, + [PWRAP_WRAP_STA] = 0x3c, + [PWRAP_RRARB_INIT] = 0x40, + [PWRAP_RRARB_EN] = 0x44, + [PWRAP_RRARB_STA0] = 0x48, + [PWRAP_RRARB_STA1] = 0x4c, + [PWRAP_HARB_INIT] = 0x50, + [PWRAP_HARB_HPRIO] = 0x54, + [PWRAP_HIPRIO_ARB_EN] = 0x58, + [PWRAP_HARB_STA0] = 0x5c, + [PWRAP_HARB_STA1] = 0x60, + [PWRAP_MAN_EN] = 0x64, + [PWRAP_MAN_CMD] = 0x68, + [PWRAP_MAN_RDATA] = 0x6c, + [PWRAP_MAN_VLDCLR] = 0x70, + [PWRAP_WACS0_EN] = 0x74, + [PWRAP_INIT_DONE0] = 0x78, + [PWRAP_WACS0_CMD] = 0x7c, + [PWRAP_WACS0_RDATA] = 0x80, + [PWRAP_WACS0_VLDCLR] = 0x84, + [PWRAP_WACS1_EN] = 0x88, + [PWRAP_INIT_DONE1] = 0x8c, + [PWRAP_WACS1_CMD] = 0x90, + [PWRAP_WACS1_RDATA] = 0x94, + [PWRAP_WACS1_VLDCLR] = 0x98, + [PWRAP_WACS2_EN] = 0x9c, + [PWRAP_INIT_DONE2] = 0xa0, + [PWRAP_WACS2_CMD] = 0xa4, + [PWRAP_WACS2_RDATA] = 0xa8, + [PWRAP_WACS2_VLDCLR] = 0xac, + [PWRAP_INT_EN] = 0xb0, + [PWRAP_INT_FLG_RAW] = 0xb4, + [PWRAP_INT_FLG] = 0xb8, + [PWRAP_INT_CLR] = 0xbc, + [PWRAP_SIG_ADR] = 0xc0, + [PWRAP_SIG_MODE] = 0xc4, + [PWRAP_SIG_VALUE] = 0xc8, + [PWRAP_SIG_ERRVAL] = 0xcc, + [PWRAP_CRC_EN] = 0xd0, + [PWRAP_EVENT_STA] = 0xd4, + [PWRAP_EVENT_STACLR] = 0xd8, + [PWRAP_TIMER_EN] = 0xdc, + [PWRAP_TIMER_STA] = 0xe0, + [PWRAP_WDT_UNIT] = 0xe4, + [PWRAP_WDT_SRC_EN] = 0xe8, + [PWRAP_WDT_FLG] = 0xec, + [PWRAP_DEBUG_INT_SEL] = 0xf0, + [PWRAP_DVFS_ADR0] = 0xf4, + [PWRAP_DVFS_WDATA0] = 0xf8, + [PWRAP_DVFS_ADR1] = 0xfc, + [PWRAP_DVFS_WDATA1] = 0x100, + [PWRAP_DVFS_ADR2] = 0x104, + [PWRAP_DVFS_WDATA2] = 0x108, + [PWRAP_DVFS_ADR3] = 0x10c, + [PWRAP_DVFS_WDATA3] = 0x110, + [PWRAP_DVFS_ADR4] = 0x114, + [PWRAP_DVFS_WDATA4] = 0x118, + [PWRAP_DVFS_ADR5] = 0x11c, + [PWRAP_DVFS_WDATA5] = 0x120, + [PWRAP_DVFS_ADR6] = 0x124, + [PWRAP_DVFS_WDATA6] = 0x128, + [PWRAP_DVFS_ADR7] = 0x12c, + [PWRAP_DVFS_WDATA7] = 0x130, + [PWRAP_CIPHER_KEY_SEL] = 0x134, + [PWRAP_CIPHER_IV_SEL] = 0x138, + [PWRAP_CIPHER_LOAD] = 0x13c, + [PWRAP_CIPHER_START] = 0x140, + [PWRAP_CIPHER_RDY] = 0x144, + [PWRAP_CIPHER_MODE] = 0x148, + [PWRAP_CIPHER_SWRST] = 0x14c, + [PWRAP_CIPHER_IV0] = 0x150, + [PWRAP_CIPHER_IV1] = 0x154, + [PWRAP_CIPHER_IV2] = 0x158, + [PWRAP_DCM_EN] = 0x15c, + [PWRAP_DCM_DBC_PRD] = 0x160, +}; + static const int mt6765_regs[] = { [PWRAP_MUX_SEL] = 0x0, [PWRAP_WRAP_EN] = 0x4, @@ -1301,6 +1450,7 @@ static const int mt8186_regs[] = { }; enum pmic_type { + PMIC_MT6320, PMIC_MT6323, PMIC_MT6331, PMIC_MT6332, @@ -1314,6 +1464,7 @@ enum pmic_type { enum pwrap_type { PWRAP_MT2701, + PWRAP_MT6589, PWRAP_MT6765, PWRAP_MT6779, PWRAP_MT6795, @@ -1750,6 +1901,7 @@ static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp) case PWRAP_MT8173: pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2); break; + case PWRAP_MT6589: case PWRAP_MT8135: pwrap_writel(wrp, 0x4, PWRAP_CSHEXT); pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0); @@ -1834,6 +1986,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL); switch (wrp->master->type) { + case PWRAP_MT6589: case PWRAP_MT8135: pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD); pwrap_writel(wrp, 1, PWRAP_CIPHER_START); @@ -1866,6 +2019,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) pwrap_config_cipher(wrp, wrp->slave->comp_dew_regs); switch (wrp->slave->type) { + case PMIC_MT6320: case PMIC_MT6397: pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD], 0x1); @@ -1960,13 +2114,13 @@ static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp) /* enable pwrap events and pwrap bridge in AP side */ pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN); pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN); - writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN); - writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN); - writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN); - writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT); - writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN); - writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN); - writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN); + writel(0x7f, wrp->bridge_base + PWRAP_BRIDGE_IORD_ARB_EN); + writel(0x1, wrp->bridge_base + PWRAP_BRIDGE_WACS3_EN); + writel(0x1, wrp->bridge_base + PWRAP_BRIDGE_WACS4_EN); + writel(0x1, wrp->bridge_base + PWRAP_BRIDGE_WDT_UNIT); + writel(0xffff, wrp->bridge_base + PWRAP_BRIDGE_WDT_SRC_EN); + writel(0x1, wrp->bridge_base + PWRAP_BRIDGE_TIMER_EN); + writel(0x7ff, wrp->bridge_base + PWRAP_BRIDGE_INT_EN); /* enable PMIC event out and sources */ if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN], @@ -2012,6 +2166,31 @@ static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp) return 0; } +static int pwrap_mt6589_init_soc_specific(struct pmic_wrapper *wrp) +{ + /* enable pwrap events and pwrap bridge in AP side */ + pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN); + pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN); + writel(0x7f, wrp->bridge_base + PWRAP_BRIDGE_IORD_ARB_EN); + writel(0x1, wrp->bridge_base + PWRAP_BRIDGE_WACS3_EN); + writel(0x1, wrp->bridge_base + PWRAP_BRIDGE_WACS4_EN); + writel(0xf, wrp->bridge_base + PWRAP_BRIDGE_WDT_UNIT); + writel(0xffff, wrp->bridge_base + PWRAP_BRIDGE_WDT_SRC_EN); + writel(0x1, wrp->bridge_base + PWRAP_BRIDGE_TIMER_EN); + writel(0x7ff, wrp->bridge_base + PWRAP_BRIDGE_INT_EN); + + /* enable PMIC event out and sources */ + if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN], + 0x1) || + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN], + 0xffff)) { + dev_err(wrp->dev, "enable dewrap fail\n"); + return -EFAULT; + } + + return 0; +} + static int pwrap_mt6795_init_soc_specific(struct pmic_wrapper *wrp) { pwrap_writel(wrp, 0xf, PWRAP_STAUPD_GRPEN); @@ -2110,7 +2289,8 @@ static int pwrap_init(struct pmic_wrapper *wrp) return ret; } - if (wrp->master->type == PWRAP_MT8135) + if (wrp->master->type == PWRAP_MT8135 || + wrp->master->type == PWRAP_MT6589) pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN); pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN); @@ -2131,8 +2311,8 @@ static int pwrap_init(struct pmic_wrapper *wrp) pwrap_writel(wrp, 1, PWRAP_INIT_DONE1); if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) { - writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3); - writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4); + writel(1, wrp->bridge_base + PWRAP_BRIDGE_INIT_DONE3); + writel(1, wrp->bridge_base + PWRAP_BRIDGE_INIT_DONE4); } return 0; @@ -2186,6 +2366,14 @@ static const struct pwrap_slv_regops pwrap_regops32 = { .regmap = &pwrap_regmap_config32, }; +static const struct pwrap_slv_type pmic_mt6320 = { + .dew_regs = mt6320_regs, + .type = PMIC_MT6320, + .regops = &pwrap_regops16, + .caps = PWRAP_SLV_CAP_SPI | PWRAP_DEW_DIO_EN | + PWRAP_SLV_CAP_SECURITY, +}; + static const struct pwrap_slv_type pmic_mt6323 = { .dew_regs = mt6323_regs, .type = PMIC_MT6323, @@ -2248,6 +2436,7 @@ static const struct pwrap_slv_type pmic_mt6397 = { }; static const struct of_device_id of_slave_match_tbl[] = { + { .compatible = "mediatek,mt6320", .data = &pmic_mt6320 }, { .compatible = "mediatek,mt6323", .data = &pmic_mt6323 }, { .compatible = "mediatek,mt6331", .data = &pmic_mt6331 }, { .compatible = "mediatek,mt6351", .data = &pmic_mt6351 }, @@ -2277,6 +2466,19 @@ static const struct pmic_wrapper_type pwrap_mt2701 = { .init_soc_specific = pwrap_mt2701_init_soc_specific, }; +static const struct pmic_wrapper_type pwrap_mt6589 = { + .regs = mt6589_regs, + .type = PWRAP_MT6589, + .arb_en_all = 0x1ff, + .int_en_all = 0x7ffffffd, + .int1_en_all = 0, + .spi_w = PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src = PWRAP_WDT_SRC_MASK_ALL, + .caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM, + .init_reg_clock = pwrap_common_init_reg_clock, + .init_soc_specific = pwrap_mt6589_init_soc_specific, +}; + static const struct pmic_wrapper_type pwrap_mt6765 = { .regs = mt6765_regs, .type = PWRAP_MT6765, @@ -2446,6 +2648,7 @@ static const struct pmic_wrapper_type pwrap_mt8186 = { static const struct of_device_id of_pwrap_match_tbl[] = { { .compatible = "mediatek,mt2701-pwrap", .data = &pwrap_mt2701 }, + { .compatible = "mediatek,mt6589-pwrap", .data = &pwrap_mt6589 }, { .compatible = "mediatek,mt6765-pwrap", .data = &pwrap_mt6765 }, { .compatible = "mediatek,mt6779-pwrap", .data = &pwrap_mt6779 }, { .compatible = "mediatek,mt6795-pwrap", .data = &pwrap_mt6795 }, diff --git a/include/dt-bindings/clock/mt6589-clk.h b/include/dt-bindings/clock/mt6589-clk.h index 67e6b75118522c..645c18148848fe 100644 --- a/include/dt-bindings/clock/mt6589-clk.h +++ b/include/dt-bindings/clock/mt6589-clk.h @@ -163,68 +163,68 @@ /* INFRACFG */ -#define CLK_INFRA_MUX1 1 - -#define CLK_INFRA_DBGCLK 64 -#define CLK_INFRA_SMI 65 -#define CLK_INFRA_SPI0 66 -#define CLK_INFRA_AUDIO 69 -#define CLK_INFRA_DEVAPC 70 -#define CLK_INFRA_MFGAXI 71 -#define CLK_INFRA_M4U 72 -#define CLK_INFRA_MD1MCUAXI 73 -#define CLK_INFRA_MD1HWMIXAXI 74 -#define CLK_INFRA_MD1AHB 75 -#define CLK_INFRA_MD2MCUAXI 76 -#define CLK_INFRA_MD2HWMIXAXI 77 -#define CLK_INFRA_MD2AHB 78 -#define CLK_INFRA_CPUM 79 -#define CLK_INFRA_KP 80 -#define CLK_INFRA_CCIF0 84 -#define CLK_INFRA_CCIF1 85 -#define CLK_INFRA_PMICSPI 86 -#define CLK_INFRA_PMICWRAP 87 +#define CLK_INFRA_MUX1 0 + +#define CLK_INFRA_DBGCLK 1 +#define CLK_INFRA_SMI 2 +#define CLK_INFRA_SPI0 3 +#define CLK_INFRA_AUDIO 4 +#define CLK_INFRA_DEVAPC 5 +#define CLK_INFRA_MFGAXI 6 +#define CLK_INFRA_M4U 7 +#define CLK_INFRA_MD1MCUAXI 8 +#define CLK_INFRA_MD1HWMIXAXI 9 +#define CLK_INFRA_MD1AHB 10 +#define CLK_INFRA_MD2MCUAXI 11 +#define CLK_INFRA_MD2HWMIXAXI 12 +#define CLK_INFRA_MD2AHB 13 +#define CLK_INFRA_CPUM 14 +#define CLK_INFRA_KP 15 +#define CLK_INFRA_CCIF0 16 +#define CLK_INFRA_CCIF1 17 +#define CLK_INFRA_PMICSPI 18 +#define CLK_INFRA_PMICWRAP 19 /* PERICFG */ -#define CLK_PERI0_NFI 0 -#define CLK_PERI0_THERM 1 -#define CLK_PERI0_PWM1 2 -#define CLK_PERI0_PWM2 3 -#define CLK_PERI0_PWM3 4 -#define CLK_PERI0_PWM4 5 -#define CLK_PERI0_PWM5 6 -#define CLK_PERI0_PWM6 7 -#define CLK_PERI0_PWM7 8 -#define CLK_PERI0_PWM 9 -#define CLK_PERI0_USB0 10 -#define CLK_PERI0_USB1 11 -#define CLK_PERI0_APDMA 12 -#define CLK_PERI0_MSDC0 13 -#define CLK_PERI0_MSDC1 14 -#define CLK_PERI0_MSDC2 15 -#define CLK_PERI0_MSDC3 16 -#define CLK_PERI0_MSDC4 17 -#define CLK_PERI0_APHIF 18 -#define CLK_PERI0_MDHIF 19 -#define CLK_PERI0_NLI 20 -#define CLK_PERI0_IRDA 21 -#define CLK_PERI0_UART0 22 -#define CLK_PERI0_UART1 23 -#define CLK_PERI0_UART2 24 -#define CLK_PERI0_UART3 25 -#define CLK_PERI0_I2C0 26 -#define CLK_PERI0_I2C1 27 -#define CLK_PERI0_I2C2 28 -#define CLK_PERI0_I2C3 29 -#define CLK_PERI0_I2C4 30 -#define CLK_PERI0_I2C5 31 - -#define CLK_PERI1_I2C6 32 -#define CLK_PERI1_PWRAP 33 +#define CLK_PERI0_NFI 0 +#define CLK_PERI0_THERM 1 +#define CLK_PERI0_PWM1 2 +#define CLK_PERI0_PWM2 3 +#define CLK_PERI0_PWM3 4 +#define CLK_PERI0_PWM4 5 +#define CLK_PERI0_PWM5 6 +#define CLK_PERI0_PWM6 7 +#define CLK_PERI0_PWM7 8 +#define CLK_PERI0_PWM 9 +#define CLK_PERI0_USB0 10 +#define CLK_PERI0_USB1 11 +#define CLK_PERI0_APDMA 12 +#define CLK_PERI0_MSDC0 13 +#define CLK_PERI0_MSDC1 14 +#define CLK_PERI0_MSDC2 15 +#define CLK_PERI0_MSDC3 16 +#define CLK_PERI0_MSDC4 17 +#define CLK_PERI0_APHIF 18 +#define CLK_PERI0_MDHIF 19 +#define CLK_PERI0_NLI 20 +#define CLK_PERI0_IRDA 21 +#define CLK_PERI0_UART0 22 +#define CLK_PERI0_UART1 23 +#define CLK_PERI0_UART2 24 +#define CLK_PERI0_UART3 25 +#define CLK_PERI0_I2C0 26 +#define CLK_PERI0_I2C1 27 +#define CLK_PERI0_I2C2 28 +#define CLK_PERI0_I2C3 29 +#define CLK_PERI0_I2C4 30 +#define CLK_PERI0_I2C5 31 + +#define CLK_PERI1_I2C6 32 +#define CLK_PERI1_PWRAP 33 #define CLK_PERI1_AUXADC 34 -#define CLK_PERI1_SPI1 35 -#define CLK_PERI1_FHCTL 36 +#define CLK_PERI1_SPI1 35 +#define CLK_PERI1_FHCTL 36 #define CLK_PERI_MUX_UART0 37 #define CLK_PERI_MUX_UART1 38 @@ -233,76 +233,76 @@ /* DISP */ -#define CLK_DISP0_LARB2_SMI 128 -#define CLK_DISP0_ROT_ENGINE 129 -#define CLK_DISP0_ROT_SMI 130 -#define CLK_DISP0_SCL 131 -#define CLK_DISP0_OVL_ENGINE 132 -#define CLK_DISP0_OVL_SMI 133 -#define CLK_DISP0_COLOR 134 -#define CLK_DISP0_2DSHP 135 -#define CLK_DISP0_BLS 136 -#define CLK_DISP0_WDMA0_ENGINE 137 -#define CLK_DISP0_WDMA0_SMI 138 -#define CLK_DISP0_WDMA1_ENGINE 139 -#define CLK_DISP0_WDMA1_SMI 140 -#define CLK_DISP0_RDMA0_ENGINE 141 -#define CLK_DISP0_RDMA0_SMI 142 -#define CLK_DISP0_RDMA0_OUTPUT 143 -#define CLK_DISP0_RDMA1_ENGINE 144 -#define CLK_DISP0_RDMA1_SMI 145 -#define CLK_DISP0_RDMA1_OUTPUT 146 -#define CLK_DISP0_GAMMA_ENGINE 147 -#define CLK_DISP0_GAMMA_PIXEL 148 -#define CLK_DISP0_CMDQ_ENGINE 149 -#define CLK_DISP0_CMDQ_SMI 150 -#define CLK_DISP0_G2D_ENGINE 151 -#define CLK_DISP0_G2D_SMI 152 - -#define CLK_DISP1_DBI_ENGINE 160 -#define CLK_DISP1_DBI_SMI 161 -#define CLK_DISP1_DBI_OUTPUT 162 -#define CLK_DISP1_DSI_ENGINE 163 -#define CLK_DISP1_DSI_DIGITAL 164 -#define CLK_DISP1_DSI_DIGITAL_LANE 165 -#define CLK_DISP1_DPI0 166 -#define CLK_DISP1_DPI1 167 -#define CLK_DISP1_LCD 168 -#define CLK_DISP1_SLCD 169 +#define CLK_DISP0_LARB2_SMI 0 +#define CLK_DISP0_ROT_ENGINE 1 +#define CLK_DISP0_ROT_SMI 2 +#define CLK_DISP0_SCL 3 +#define CLK_DISP0_OVL_ENGINE 4 +#define CLK_DISP0_OVL_SMI 5 +#define CLK_DISP0_COLOR 6 +#define CLK_DISP0_2DSHP 7 +#define CLK_DISP0_BLS 8 +#define CLK_DISP0_WDMA0_ENGINE 9 +#define CLK_DISP0_WDMA0_SMI 10 +#define CLK_DISP0_WDMA1_ENGINE 11 +#define CLK_DISP0_WDMA1_SMI 12 +#define CLK_DISP0_RDMA0_ENGINE 13 +#define CLK_DISP0_RDMA0_SMI 14 +#define CLK_DISP0_RDMA0_OUTPUT 15 +#define CLK_DISP0_RDMA1_ENGINE 16 +#define CLK_DISP0_RDMA1_SMI 17 +#define CLK_DISP0_RDMA1_OUTPUT 18 +#define CLK_DISP0_GAMMA_ENGINE 19 +#define CLK_DISP0_GAMMA_PIXEL 20 +#define CLK_DISP0_CMDQ_ENGINE 21 +#define CLK_DISP0_CMDQ_SMI 21 +#define CLK_DISP0_G2D_ENGINE 22 +#define CLK_DISP0_G2D_SMI 23 + +#define CLK_DISP1_DBI_ENGINE 24 +#define CLK_DISP1_DBI_SMI 25 +#define CLK_DISP1_DBI_OUTPUT 26 +#define CLK_DISP1_DSI_ENGINE 27 +#define CLK_DISP1_DSI_DIGITAL 28 +#define CLK_DISP1_DSI_DIGITAL_LANE 29 +#define CLK_DISP1_DPI0 30 +#define CLK_DISP1_DPI1 31 +#define CLK_DISP1_LCD 32 +#define CLK_DISP1_SLCD 33 /* IMG */ -#define CLK_IMAGE_LARB3_SMI 192 -#define CLK_IMAGE_LARB4_SMI 194 -#define CLK_IMAGE_COMMN_SMI 196 -#define CLK_IMAGE_CAM_SMI 197 -#define CLK_IMAGE_CAM_CAM 198 -#define CLK_IMAGE_SEN_TG 199 -#define CLK_IMAGE_SEN_CAM 200 -#define CLK_IMAGE_JPGD_SMI 201 -#define CLK_IMAGE_JPGD_JPG 202 -#define CLK_IMAGE_JPGE_SMI 203 -#define CLK_IMAGE_JPGE_JPG 204 -#define CLK_IMAGE_FPC 205 +#define CLK_IMAGE_LARB3_SMI 0 +#define CLK_IMAGE_LARB4_SMI 1 +#define CLK_IMAGE_COMMN_SMI 2 +#define CLK_IMAGE_CAM_SMI 3 +#define CLK_IMAGE_CAM_CAM 4 +#define CLK_IMAGE_SEN_TG 5 +#define CLK_IMAGE_SEN_CAM 6 +#define CLK_IMAGE_JPGD_SMI 7 +#define CLK_IMAGE_JPGD_JPG 8 +#define CLK_IMAGE_JPGE_SMI 9 +#define CLK_IMAGE_JPGE_JPG 10 +#define CLK_IMAGE_FPC 11 /* MFG */ -#define CLK_MFG_AXI 224 -#define CLK_MFG_MEM 225 -#define CLK_MFG_G3D 226 -#define CLK_MFG_HYD 227 +#define CLK_MFG_AXI 0 +#define CLK_MFG_MEM 1 +#define CLK_MFG_G3D 2 +#define CLK_MFG_HYD 3 /* AUD */ -#define CLK_AUDIO_AFE 258 -#define CLK_AUDIO_I2S 262 +#define CLK_AUDIO_AFE 0 +#define CLK_AUDIO_I2S 1 /* VDEC */ -#define CLK_VDEC0_VDE 288 +#define CLK_VDEC0_VDE 0 -#define CLK_VDEC1_SMI 320 +#define CLK_VDEC1_SMI 1 /* VENC */ -#define CLK_VENC_VEN 352 +#define CLK_VENC_VEN 0 diff --git a/include/dt-bindings/pinctrl/mt6320-pinfunc.h b/include/dt-bindings/pinctrl/mt6320-pinfunc.h new file mode 100644 index 00000000000000..173a11f12b9183 --- /dev/null +++ b/include/dt-bindings/pinctrl/mt6320-pinfunc.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DTS_MT6320_PINFUNC_H +#define __DTS_MT6320_PINFUNC_H + +#include + + +#define MT6320_PIN_0_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT6320_PIN_0_GPIO0__FUNC_INT (MTK_PIN_NO(0) | 1) + +#define MT6320_PIN_1_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT6320_PIN_1_GPIO1__FUNC_SRCVOLTEN (MTK_PIN_NO(1) | 1) + +#define MT6320_PIN_2_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT6320_PIN_2_GPIO2__FUNC_SRCLKEN_PERI (MTK_PIN_NO(2) | 1) + +#define MT6320_PIN_3_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT6320_PIN_3_GPIO3__FUNC_SRCLKEN_MD2 (MTK_PIN_NO(3) | 1) + +#define MT6320_PIN_4_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT6320_PIN_4_GPIO4__FUNC_RTC_32K1V8 (MTK_PIN_NO(4) | 1) + +#define MT6320_PIN_5_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT6320_PIN_5_GPIO5__FUNC_WRAP_EVENT (MTK_PIN_NO(5) | 1) + +#define MT6320_PIN_6_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT6320_PIN_6_GPIO6__FUNC_SPI_CLK (MTK_PIN_NO(6) | 1) + +#define MT6320_PIN_7_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT6320_PIN_7_GPIO7__FUNC_SPI_CSN (MTK_PIN_NO(7) | 1) + +#define MT6320_PIN_8_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT6320_PIN_8_GPIO8__FUNC_SPI_MOSI (MTK_PIN_NO(8) | 1) + +#define MT6320_PIN_9_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT6320_PIN_9_GPIO9__FUNC_SPI_MISO (MTK_PIN_NO(9) | 1) + +#define MT6320_PIN_10_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT6320_PIN_10_GPIO10__FUNC_ADC_CK (MTK_PIN_NO(10) | 1) + +#define MT6320_PIN_11_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT6320_PIN_11_GPIO11__FUNC_ADC_WS (MTK_PIN_NO(11) | 1) + +#define MT6320_PIN_12_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT6320_PIN_12_GPIO12__FUNC_ADC_DAT (MTK_PIN_NO(12) | 1) + +#define MT6320_PIN_13_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT6320_PIN_13_GPIO13__FUNC_DAC_CK (MTK_PIN_NO(13) | 1) + +#define MT6320_PIN_14_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT6320_PIN_14_GPIO14__FUNC_DAC_WS (MTK_PIN_NO(14) | 1) + +#define MT6320_PIN_15_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT6320_PIN_15_GPIO15__FUNC_DAC_DAT (MTK_PIN_NO(15) | 1) + +#define MT6320_PIN_16_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define MT6320_PIN_16_GPIO16__FUNC_COL0_USBDL (MTK_PIN_NO(16) | 1) +#define MT6320_PIN_16_GPIO16__FUNC_EINT10 (MTK_PIN_NO(16) | 2) +#define MT6320_PIN_16_GPIO16__FUNC_PWM1_3X (MTK_PIN_NO(16) | 3) + +#define MT6320_PIN_17_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define MT6320_PIN_17_GPIO17__FUNC_COL1 (MTK_PIN_NO(17) | 1) +#define MT6320_PIN_17_GPIO17__FUNC_EINT11 (MTK_PIN_NO(17) | 2) +#define MT6320_PIN_17_GPIO17__FUNC_SCL0_2X (MTK_PIN_NO(17) | 3) + +#define MT6320_PIN_18_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT6320_PIN_18_GPIO18__FUNC_COL2 (MTK_PIN_NO(18) | 1) +#define MT6320_PIN_18_GPIO18__FUNC_EINT12 (MTK_PIN_NO(18) | 2) +#define MT6320_PIN_18_GPIO18__FUNC_SDA0_2X (MTK_PIN_NO(18) | 3) + +#define MT6320_PIN_19_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT6320_PIN_19_GPIO19__FUNC_COL3 (MTK_PIN_NO(19) | 1) +#define MT6320_PIN_19_GPIO19__FUNC_EINT13 (MTK_PIN_NO(19) | 2) +#define MT6320_PIN_19_GPIO19__FUNC_SCL1_2X (MTK_PIN_NO(19) | 3) + +#define MT6320_PIN_20_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT6320_PIN_20_GPIO20__FUNC_COL4 (MTK_PIN_NO(20) | 1) +#define MT6320_PIN_20_GPIO20__FUNC_EINT14 (MTK_PIN_NO(20) | 2) +#define MT6320_PIN_20_GPIO20__FUNC_SDA1_2X (MTK_PIN_NO(20) | 3) + +#define MT6320_PIN_21_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT6320_PIN_21_GPIO21__FUNC_COL5 (MTK_PIN_NO(21) | 1) +#define MT6320_PIN_21_GPIO21__FUNC_EINT15 (MTK_PIN_NO(21) | 2) +#define MT6320_PIN_21_GPIO21__FUNC_SCL2_2X (MTK_PIN_NO(21) | 3) + +#define MT6320_PIN_22_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT6320_PIN_22_GPIO22__FUNC_COL6 (MTK_PIN_NO(22) | 1) +#define MT6320_PIN_22_GPIO22__FUNC_EINT16 (MTK_PIN_NO(22) | 2) +#define MT6320_PIN_22_GPIO22__FUNC_SDA2_2X (MTK_PIN_NO(22) | 3) +#define MT6320_PIN_22_GPIO22__FUNC_GPIO32K_0 (MTK_PIN_NO(22) | 4) +#define MT6320_PIN_22_GPIO22__FUNC_GPIO26M_0 (MTK_PIN_NO(22) | 5) + +#define MT6320_PIN_23_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT6320_PIN_23_GPIO23__FUNC_COL7 (MTK_PIN_NO(23) | 1) +#define MT6320_PIN_23_GPIO23__FUNC_EINT17 (MTK_PIN_NO(23) | 2) +#define MT6320_PIN_23_GPIO23__FUNC_PWM2_3X (MTK_PIN_NO(23) | 3) +#define MT6320_PIN_23_GPIO23__FUNC_GPIO32K_1 (MTK_PIN_NO(23) | 4) +#define MT6320_PIN_23_GPIO23__FUNC_GPIO26M_1 (MTK_PIN_NO(23) | 5) + +#define MT6320_PIN_24_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT6320_PIN_24_GPIO24__FUNC_ROW0 (MTK_PIN_NO(24) | 1) +#define MT6320_PIN_24_GPIO24__FUNC_EINT18 (MTK_PIN_NO(24) | 2) +#define MT6320_PIN_24_GPIO24__FUNC_SCL0_3X (MTK_PIN_NO(24) | 3) + +#define MT6320_PIN_25_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT6320_PIN_25_GPIO25__FUNC_ROW1 (MTK_PIN_NO(25) | 1) +#define MT6320_PIN_25_GPIO25__FUNC_EINT19 (MTK_PIN_NO(25) | 2) +#define MT6320_PIN_25_GPIO25__FUNC_SDA0_3X (MTK_PIN_NO(25) | 3) + +#define MT6320_PIN_26_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT6320_PIN_26_GPIO26__FUNC_ROW2 (MTK_PIN_NO(26) | 1) +#define MT6320_PIN_26_GPIO26__FUNC_EINT20 (MTK_PIN_NO(26) | 2) +#define MT6320_PIN_26_GPIO26__FUNC_SCL1_3X (MTK_PIN_NO(26) | 3) + +#define MT6320_PIN_27_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT6320_PIN_27_GPIO27__FUNC_ROW3 (MTK_PIN_NO(27) | 1) +#define MT6320_PIN_27_GPIO27__FUNC_EINT21 (MTK_PIN_NO(27) | 2) +#define MT6320_PIN_27_GPIO27__FUNC_SDA1_3X (MTK_PIN_NO(27) | 3) + +#define MT6320_PIN_28_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT6320_PIN_28_GPIO28__FUNC_ROW4 (MTK_PIN_NO(28) | 1) +#define MT6320_PIN_28_GPIO28__FUNC_EINT22 (MTK_PIN_NO(28) | 2) +#define MT6320_PIN_28_GPIO28__FUNC_SCL2_3X (MTK_PIN_NO(28) | 3) + +#define MT6320_PIN_29_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT6320_PIN_29_GPIO29__FUNC_ROW5 (MTK_PIN_NO(29) | 1) +#define MT6320_PIN_29_GPIO29__FUNC_EINT23 (MTK_PIN_NO(29) | 2) +#define MT6320_PIN_29_GPIO29__FUNC_SDA2_3X (MTK_PIN_NO(29) | 3) + +#define MT6320_PIN_30_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define MT6320_PIN_30_GPIO30__FUNC_ROW6 (MTK_PIN_NO(30) | 1) +#define MT6320_PIN_30_GPIO30__FUNC_EINT24 (MTK_PIN_NO(30) | 2) +#define MT6320_PIN_30_GPIO30__FUNC_PWM3_3X (MTK_PIN_NO(30) | 3) +#define MT6320_PIN_30_GPIO30__FUNC_GPIO32K_2 (MTK_PIN_NO(30) | 4) +#define MT6320_PIN_30_GPIO30__FUNC_GPIO26M_2 (MTK_PIN_NO(30) | 5) + +#define MT6320_PIN_31_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define MT6320_PIN_31_GPIO31__FUNC_ROW7 (MTK_PIN_NO(31) | 1) +#define MT6320_PIN_31_GPIO31__FUNC_EINT3 (MTK_PIN_NO(31) | 2) +#define MT6320_PIN_31_GPIO31__FUNC_GPIO32K_3 (MTK_PIN_NO(31) | 4) +#define MT6320_PIN_31_GPIO31__FUNC_GPIO26M_3 (MTK_PIN_NO(31) | 5) + +#define MT6320_PIN_32_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define MT6320_PIN_32_GPIO32__FUNC_PWM1 (MTK_PIN_NO(32) | 1) +#define MT6320_PIN_32_GPIO32__FUNC_EINT4 (MTK_PIN_NO(32) | 2) +#define MT6320_PIN_32_GPIO32__FUNC_GPIO32K_4 (MTK_PIN_NO(32) | 4) +#define MT6320_PIN_32_GPIO32__FUNC_GPIO26M_4 (MTK_PIN_NO(32) | 5) + +#define MT6320_PIN_33_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT6320_PIN_33_GPIO33__FUNC_PWM2 (MTK_PIN_NO(33) | 1) +#define MT6320_PIN_33_GPIO33__FUNC_EINT5 (MTK_PIN_NO(33) | 2) +#define MT6320_PIN_33_GPIO33__FUNC_GPIO32K_5 (MTK_PIN_NO(33) | 4) +#define MT6320_PIN_33_GPIO33__FUNC_GPIO26M_5 (MTK_PIN_NO(33) | 5) + +#define MT6320_PIN_34_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT6320_PIN_34_GPIO34__FUNC_PWM3 (MTK_PIN_NO(34) | 1) +#define MT6320_PIN_34_GPIO34__FUNC_EINT6 (MTK_PIN_NO(34) | 2) +#define MT6320_PIN_34_GPIO34__FUNC_COL0 (MTK_PIN_NO(34) | 3) +#define MT6320_PIN_34_GPIO34__FUNC_GPIO32K_6 (MTK_PIN_NO(34) | 4) +#define MT6320_PIN_34_GPIO34__FUNC_GPIO26M_6 (MTK_PIN_NO(34) | 5) + +#define MT6320_PIN_35_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT6320_PIN_35_GPIO35__FUNC_SCL0 (MTK_PIN_NO(35) | 1) +#define MT6320_PIN_35_GPIO35__FUNC_EINT7 (MTK_PIN_NO(35) | 2) +#define MT6320_PIN_35_GPIO35__FUNC_PWM1_2X (MTK_PIN_NO(35) | 3) + +#define MT6320_PIN_36_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT6320_PIN_36_GPIO36__FUNC_SDA0 (MTK_PIN_NO(36) | 1) +#define MT6320_PIN_36_GPIO36__FUNC_EINT8 (MTK_PIN_NO(36) | 2) + +#define MT6320_PIN_37_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT6320_PIN_37_GPIO37__FUNC_SCL1 (MTK_PIN_NO(37) | 1) +#define MT6320_PIN_37_GPIO37__FUNC_EINT9 (MTK_PIN_NO(37) | 2) +#define MT6320_PIN_37_GPIO37__FUNC_PWM2_2X (MTK_PIN_NO(37) | 3) + +#define MT6320_PIN_38_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define MT6320_PIN_38_GPIO38__FUNC_SDA1 (MTK_PIN_NO(38) | 1) +#define MT6320_PIN_38_GPIO38__FUNC_EINT0 (MTK_PIN_NO(38) | 2) + +#define MT6320_PIN_39_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT6320_PIN_39_GPIO39__FUNC_SCL2 (MTK_PIN_NO(39) | 1) +#define MT6320_PIN_39_GPIO39__FUNC_EINT1 (MTK_PIN_NO(39) | 2) +#define MT6320_PIN_39_GPIO39__FUNC_PWM3_2X (MTK_PIN_NO(39) | 3) + +#define MT6320_PIN_40_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT6320_PIN_40_GPIO40__FUNC_SDA2 (MTK_PIN_NO(40) | 1) +#define MT6320_PIN_40_GPIO40__FUNC_EINT2 (MTK_PIN_NO(40) | 2) + +#define MT6320_PIN_41_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define MT6320_PIN_41_GPIO41__FUNC_SIM1_AP_SCLK (MTK_PIN_NO(41) | 1) + +#define MT6320_PIN_42_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define MT6320_PIN_42_GPIO42__FUNC_SIM1_AP_SRST (MTK_PIN_NO(42) | 1) + +#define MT6320_PIN_43_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define MT6320_PIN_43_GPIO43__FUNC_SIM2_AP_SCLK (MTK_PIN_NO(43) | 1) + +#define MT6320_PIN_44_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define MT6320_PIN_44_GPIO44__FUNC_SIM2_AP_SRST (MTK_PIN_NO(44) | 1) + +#define MT6320_PIN_45_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define MT6320_PIN_45_GPIO45__FUNC_SIMLS1_SCLK (MTK_PIN_NO(45) | 1) + +#define MT6320_PIN_46_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define MT6320_PIN_46_GPIO46__FUNC_SIMLS1_SRST (MTK_PIN_NO(46) | 1) + +#define MT6320_PIN_47_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define MT6320_PIN_47_GPIO47__FUNC_SIMLS2_SCLK (MTK_PIN_NO(47) | 1) +#define MT6320_PIN_47_GPIO47__FUNC_EINT10 (MTK_PIN_NO(47) | 5) + +#define MT6320_PIN_48_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define MT6320_PIN_48_GPIO48__FUNC_SIMLS2_SRST (MTK_PIN_NO(48) | 1) + +#endif /* __DTS_MT6320_PINFUNC_H */ diff --git a/include/dt-bindings/reset/mt6589-resets.h b/include/dt-bindings/reset/mt6589-resets.h index 54570146ba8bfd..f7960ac04203b5 100644 --- a/include/dt-bindings/reset/mt6589-resets.h +++ b/include/dt-bindings/reset/mt6589-resets.h @@ -34,6 +34,7 @@ #define MT6589_PERI_I2C6_SW_RST 28 #define MT6589_PERI_USB_SW_RST 29 #define MT6589_PERI_SPI0_SW_RST 33 +#define MT6589_PERI_PWRAP_BRIDGE_SW_RST 34 /* INFRA */ #define MT6589_INFRA_EMI_REG_RST 0 diff --git a/include/linux/mfd/mt6320/core.h b/include/linux/mfd/mt6320/core.h new file mode 100644 index 00000000000000..c75c21dd016158 --- /dev/null +++ b/include/linux/mfd/mt6320/core.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2014 Akari Tsuyukusa + */ + +#ifndef __MFD_MT6320_CORE_H__ +#define __MFD_MT6320_CORE_H__ + +enum mt6320_irq_numbers { + MT6320_IRQ_SPKL_AB = 0, + MT6320_IRQ_SPKR_AB, + MT6320_IRQ_SPKL, + MT6320_IRQ_SPKR, + MT6320_IRQ_BAT_L, + MT6320_IRQ_BAT_H, + MT6320_IRQ_FG_BAT_L, + MT6320_IRQ_FG_BAT_H, + MT6320_IRQ_WATCHDOG, + MT6320_IRQ_PWRKEY, + MT6320_IRQ_THR_L, + MT6320_IRQ_THR_H, + MT6320_IRQ_VBATON_UNDET, + MT6320_IRQ_BVALID_DET, + MT6320_IRQ_CHRDET, + MT6320_IRQ_OV, + MT6320_IRQ_LDO = 16, + MT6320_IRQ_HOMEKEY, + MT6320_IRQ_ACCDET, + MT6320_IRQ_AUDIO, + MT6320_IRQ_RTC, + MT6320_IRQ_VPROC = 24, + MT6320_IRQ_VSRAM, + MT6320_IRQ_VCORE, + MT6320_IRQ_VM, + MT6320_IRQ_VIO18, + MT6320_IRQ_VPA, + MT6320_IRQ_VRF18, + MT6320_IRQ_VRF18_2, + MT6320_IRQ_NR, +}; + +#endif /* __MFD_MT6320_CORE_H__ */ diff --git a/include/linux/mfd/mt6320/registers.h b/include/linux/mfd/mt6320/registers.h new file mode 100644 index 00000000000000..32b7a862b8a10d --- /dev/null +++ b/include/linux/mfd/mt6320/registers.h @@ -0,0 +1,505 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2014 MediaTek Inc. + * Copyright (C) 2014 BQ + * Copyright (C) 2026 Akari Tsuyukusa + * + * MT6320 Register Map based on bq Aquaris 5 kernel + */ + +#ifndef __MFD_MT6320_REGISTERS_H__ +#define ___MFD_MT6320_REGISTERS_H__ + +/* PMIC Registers */ +#define MT6320_CHR_CON0 0x0000 +#define MT6320_CHR_CON1 0x0002 +#define MT6320_CHR_CON2 0x0004 +#define MT6320_CHR_CON3 0x0006 +#define MT6320_CHR_CON4 0x0008 +#define MT6320_CHR_CON5 0x000a +#define MT6320_CHR_CON6 0x000c +#define MT6320_CHR_CON7 0x000e +#define MT6320_CHR_CON8 0x0010 +#define MT6320_CHR_CON9 0x0012 +#define MT6320_CHR_CON10 0x0014 +#define MT6320_CHR_CON11 0x0016 +#define MT6320_CHR_CON12 0x0018 +#define MT6320_CHR_CON13 0x001a +#define MT6320_CHR_CON14 0x001c +#define MT6320_CHR_CON15 0x001e +#define MT6320_CHR_CON16 0x0020 +#define MT6320_CHR_CON17 0x0022 +#define MT6320_CHR_CON18 0x0024 +#define MT6320_CHR_CON19 0x0026 +#define MT6320_CHR_CON20 0x0028 +#define MT6320_CHR_CON21 0x002a +#define MT6320_CHR_CON22 0x002c +#define MT6320_CHR_CON23 0x002e +#define MT6320_CHR_CON24 0x0030 +#define MT6320_CHR_CON25 0x0032 +#define MT6320_CHR_CON26 0x0034 +#define MT6320_CHR_CON27 0x0036 +#define MT6320_CHR_CON28 0x0038 +#define MT6320_CHR_CON29 0x003a +#define MT6320_CID 0x0100 +#define MT6320_TOP_CKPDN 0x0102 +#define MT6320_TOP_CKPDN2 0x0108 +#define MT6320_TOP_GPIO_CKPDN 0x010e +#define MT6320_TOP_RST_CON 0x0114 +#define MT6320_WRP_CKPDN 0x011a +#define MT6320_WRP_RST_CON 0x0120 +#define MT6320_TOP_RST_MISC 0x0126 +#define MT6320_TOP_CKCON1 0x0128 +#define MT6320_TOP_CKCON2 0x012a +#define MT6320_TOP_CKTST1 0x012c +#define MT6320_TOP_CKTST2 0x012e +#define MT6320_OC_DEG_EN 0x0130 +#define MT6320_OC_CTL0 0x0132 +#define MT6320_OC_CTL1 0x0134 +#define MT6320_OC_CTL2 0x0136 +#define MT6320_INT_RSV 0x0138 +#define MT6320_TEST_CON0 0x013a +#define MT6320_TEST_CON1 0x013c +#define MT6320_STATUS0 0x013e +#define MT6320_STATUS1 0x0140 +#define MT6320_PGSTATUS 0x0142 +#define MT6320_CHRSTATUS 0x0144 +#define MT6320_OCSTATUS0 0x0146 +#define MT6320_OCSTATUS1 0x0148 +#define MT6320_OCSTATUS2 0x014a +#define MT6320_SIMLS_CON 0x014c +#define MT6320_TEST_OUT_L 0x014e +#define MT6320_TEST_OUT_H 0x0150 +#define MT6320_TDSEL_CON 0x0152 +#define MT6320_RDSEL_CON 0x0154 +#define MT6320_GPIO_SMT_CON0 0x0156 +#define MT6320_GPIO_SMT_CON1 0x0158 +#define MT6320_GPIO_SMT_CON2 0x015a +#define MT6320_GPIO_SMT_CON3 0x015c +#define MT6320_DRV_CON0 0x015e +#define MT6320_DRV_CON1 0x0160 +#define MT6320_DRV_CON2 0x0162 +#define MT6320_DRV_CON3 0x0164 +#define MT6320_DRV_CON4 0x0166 +#define MT6320_DRV_CON5 0x0168 +#define MT6320_DRV_CON6 0x016a +#define MT6320_DRV_CON7 0x016c +#define MT6320_DRV_CON8 0x016e +#define MT6320_DRV_CON9 0x0170 +#define MT6320_DRV_CON10 0x0172 +#define MT6320_DRV_CON11 0x0174 +#define MT6320_DRV_CON12 0x0176 +#define MT6320_INT_CON0 0x0178 +#define MT6320_INT_CON1 0x017e +#define MT6320_INT_STATUS0 0x0184 +#define MT6320_INT_STATUS1 0x0186 +#define MT6320_FQMTR_CON0 0x0188 +#define MT6320_FQMTR_CON1 0x018a +#define MT6320_FQMTR_CON2 0x018c +#define MT6320_EFUSE_CON0 0x018e +#define MT6320_EFUSE_CON1 0x0190 +#define MT6320_EFUSE_CON2 0x0192 +#define MT6320_EFUSE_CON3 0x0194 +#define MT6320_EFUSE_CON4 0x0196 +#define MT6320_EFUSE_CON5 0x0198 +#define MT6320_EFUSE_CON6 0x019a +#define MT6320_EFUSE_VAL_0_15 0x019c +#define MT6320_EFUSE_VAL_16_31 0x019e +#define MT6320_EFUSE_VAL_32_47 0x01a0 +#define MT6320_EFUSE_VAL_48_63 0x01a2 +#define MT6320_EFUSE_VAL_64_79 0x01a4 +#define MT6320_EFUSE_VAL_80_95 0x01a6 +#define MT6320_EFUSE_VAL_96_111 0x01a8 +#define MT6320_EFUSE_VAL_112_127 0x01aa +#define MT6320_EFUSE_VAL_128_143 0x01ac +#define MT6320_EFUSE_VAL_144_159 0x01ae +#define MT6320_EFUSE_VAL_160_175 0x01b0 +#define MT6320_EFUSE_VAL_176_191 0x01b2 +#define MT6320_EFUSE_DOUT_0_15 0x01b4 +#define MT6320_EFUSE_DOUT_16_31 0x01b6 +#define MT6320_EFUSE_DOUT_32_47 0x01b8 +#define MT6320_EFUSE_DOUT_48_63 0x01ba +#define MT6320_EFUSE_DOUT_64_79 0x01bc +#define MT6320_EFUSE_DOUT_80_95 0x01be +#define MT6320_EFUSE_DOUT_96_111 0x01c0 +#define MT6320_EFUSE_DOUT_112_127 0x01c2 +#define MT6320_EFUSE_DOUT_128_143 0x01c4 +#define MT6320_EFUSE_DOUT_144_159 0x01c6 +#define MT6320_EFUSE_DOUT_160_175 0x01c8 +#define MT6320_EFUSE_DOUT_176_191 0x01ca +#define MT6320_SPI_CON 0x01cc +#define MT6320_BUCK_CON0 0x0200 +#define MT6320_BUCK_CON1 0x0202 +#define MT6320_BUCK_CON2 0x0204 +#define MT6320_VPROC_CON0 0x0206 +#define MT6320_VPROC_CON1 0x0208 +#define MT6320_VPROC_CON2 0x020a +#define MT6320_VPROC_CON3 0x020c +#define MT6320_VPROC_CON4 0x020e +#define MT6320_VPROC_CON5 0x0210 +#define MT6320_VPROC_CON6 0x0212 +#define MT6320_VPROC_CON7 0x0214 +#define MT6320_VPROC_CON8 0x0216 +#define MT6320_VPROC_CON9 0x0218 +#define MT6320_VPROC_CON10 0x021a +#define MT6320_VPROC_CON11 0x021c +#define MT6320_VPROC_CON12 0x021e +#define MT6320_VPROC_CON13 0x0220 +#define MT6320_VPROC_CON14 0x0222 +#define MT6320_VPROC_CON15 0x0224 +#define MT6320_VPROC_CON16 0x0226 +#define MT6320_VPROC_CON17 0x0228 +#define MT6320_VPROC_CON18 0x022a +#define MT6320_VSRAM_CON0 0x022c +#define MT6320_VSRAM_CON1 0x022e +#define MT6320_VSRAM_CON2 0x0230 +#define MT6320_VSRAM_CON3 0x0232 +#define MT6320_VSRAM_CON4 0x0234 +#define MT6320_VSRAM_CON5 0x0236 +#define MT6320_VSRAM_CON6 0x0238 +#define MT6320_VSRAM_CON7 0x023a +#define MT6320_VSRAM_CON8 0x023c +#define MT6320_VSRAM_CON9 0x023e +#define MT6320_VSRAM_CON10 0x0240 +#define MT6320_VSRAM_CON11 0x0242 +#define MT6320_VSRAM_CON12 0x0244 +#define MT6320_VSRAM_CON13 0x0246 +#define MT6320_VSRAM_CON14 0x0248 +#define MT6320_VSRAM_CON15 0x024a +#define MT6320_VSRAM_CON16 0x024c +#define MT6320_VSRAM_CON17 0x024e +#define MT6320_VSRAM_CON18 0x0250 +#define MT6320_VSRAM_CON19 0x0252 +#define MT6320_VSRAM_CON20 0x0254 +#define MT6320_VSRAM_CON21 0x0256 +#define MT6320_VCORE_CON0 0x0258 +#define MT6320_VCORE_CON1 0x025a +#define MT6320_VCORE_CON2 0x025c +#define MT6320_VCORE_CON3 0x025e +#define MT6320_VCORE_CON4 0x0260 +#define MT6320_VCORE_CON5 0x0262 +#define MT6320_VCORE_CON6 0x0264 +#define MT6320_VCORE_CON7 0x0266 +#define MT6320_VCORE_CON8 0x0268 +#define MT6320_VCORE_CON9 0x026a +#define MT6320_VCORE_CON10 0x026c +#define MT6320_VCORE_CON11 0x026e +#define MT6320_VCORE_CON12 0x0270 +#define MT6320_VCORE_CON13 0x0272 +#define MT6320_VCORE_CON14 0x0274 +#define MT6320_VCORE_CON15 0x0276 +#define MT6320_VCORE_CON16 0x0278 +#define MT6320_VCORE_CON17 0x027a +#define MT6320_VCORE_CON18 0x027c +#define MT6320_VM_CON0 0x027e +#define MT6320_VM_CON1 0x0280 +#define MT6320_VM_CON2 0x0282 +#define MT6320_VM_CON3 0x0284 +#define MT6320_VM_CON4 0x0286 +#define MT6320_VM_CON5 0x0288 +#define MT6320_VM_CON6 0x028a +#define MT6320_VM_CON7 0x028c +#define MT6320_VM_CON8 0x028e +#define MT6320_VM_CON9 0x0290 +#define MT6320_VM_CON10 0x0292 +#define MT6320_VM_CON11 0x0294 +#define MT6320_VM_CON12 0x0296 +#define MT6320_VM_CON13 0x0298 +#define MT6320_VM_CON14 0x029a +#define MT6320_VM_CON15 0x029c +#define MT6320_VM_CON16 0x029e +#define MT6320_VM_CON17 0x02a0 +#define MT6320_VM_CON18 0x02a2 +#define MT6320_VIO18_CON0 0x0300 +#define MT6320_VIO18_CON1 0x0302 +#define MT6320_VIO18_CON2 0x0304 +#define MT6320_VIO18_CON3 0x0306 +#define MT6320_VIO18_CON4 0x0308 +#define MT6320_VIO18_CON5 0x030a +#define MT6320_VIO18_CON6 0x030c +#define MT6320_VIO18_CON7 0x030e +#define MT6320_VIO18_CON8 0x0310 +#define MT6320_VIO18_CON9 0x0312 +#define MT6320_VIO18_CON10 0x0314 +#define MT6320_VIO18_CON11 0x0316 +#define MT6320_VIO18_CON12 0x0318 +#define MT6320_VIO18_CON13 0x031a +#define MT6320_VIO18_CON14 0x031c +#define MT6320_VIO18_CON15 0x031e +#define MT6320_VIO18_CON16 0x0320 +#define MT6320_VIO18_CON17 0x0322 +#define MT6320_VIO18_CON18 0x0324 +#define MT6320_VPA_CON0 0x0326 +#define MT6320_VPA_CON1 0x0328 +#define MT6320_VPA_CON2 0x032a +#define MT6320_VPA_CON3 0x032c +#define MT6320_VPA_CON4 0x032e +#define MT6320_VPA_CON5 0x0330 +#define MT6320_VPA_CON6 0x0332 +#define MT6320_VPA_CON7 0x0334 +#define MT6320_VPA_CON8 0x0336 +#define MT6320_VPA_CON9 0x0338 +#define MT6320_VPA_CON10 0x033a +#define MT6320_VPA_CON11 0x033c +#define MT6320_VPA_CON12 0x033e +#define MT6320_VPA_CON13 0x0340 +#define MT6320_VPA_CON14 0x0342 +#define MT6320_VPA_CON15 0x0344 +#define MT6320_VPA_CON16 0x0346 +#define MT6320_VPA_CON17 0x0348 +#define MT6320_VPA_CON18 0x034a +#define MT6320_VPA_CON19 0x034c +#define MT6320_VPA_CON20 0x034e +#define MT6320_VRF18_CON0 0x0350 +#define MT6320_VRF18_CON1 0x0352 +#define MT6320_VRF18_CON2 0x0354 +#define MT6320_VRF18_CON3 0x0356 +#define MT6320_VRF18_CON4 0x0358 +#define MT6320_VRF18_CON5 0x035a +#define MT6320_VRF18_CON6 0x035c +#define MT6320_VRF18_CON7 0x035e +#define MT6320_VRF18_CON8 0x0360 +#define MT6320_VRF18_CON9 0x0362 +#define MT6320_VRF18_CON10 0x0364 +#define MT6320_VRF18_CON11 0x0366 +#define MT6320_VRF18_CON12 0x0368 +#define MT6320_VRF18_CON13 0x036a +#define MT6320_VRF18_CON14 0x036c +#define MT6320_VRF18_CON15 0x036e +#define MT6320_VRF18_CON16 0x0370 +#define MT6320_VRF18_CON17 0x0372 +#define MT6320_VRF18_CON18 0x0374 +#define MT6320_VRF18_CON19 0x0376 +#define MT6320_VRF18_CON20 0x0378 +#define MT6320_VRF18_2_CON0 0x037a +#define MT6320_VRF18_2_CON1 0x037c +#define MT6320_VRF18_2_CON2 0x037e +#define MT6320_VRF18_2_CON3 0x0380 +#define MT6320_VRF18_2_CON4 0x0382 +#define MT6320_VRF18_2_CON5 0x0384 +#define MT6320_VRF18_2_CON6 0x0386 +#define MT6320_VRF18_2_CON7 0x0388 +#define MT6320_VRF18_2_CON8 0x038a +#define MT6320_VRF18_2_CON9 0x038c +#define MT6320_VRF18_2_CON10 0x038e +#define MT6320_VRF18_2_CON11 0x0390 +#define MT6320_VRF18_2_CON12 0x0392 +#define MT6320_VRF18_2_CON13 0x0394 +#define MT6320_VRF18_2_CON14 0x0396 +#define MT6320_VRF18_2_CON15 0x0398 +#define MT6320_VRF18_2_CON16 0x039a +#define MT6320_VRF18_2_CON17 0x039c +#define MT6320_VRF18_2_CON18 0x039e +#define MT6320_BUCK_K_CON0 0x03a0 +#define MT6320_BUCK_K_CON1 0x03a2 +#define MT6320_ANALDO_CON0 0x0400 +#define MT6320_ANALDO_CON1 0x0402 +#define MT6320_ANALDO_CON2 0x0404 +#define MT6320_ANALDO_CON3 0x0406 +#define MT6320_ANALDO_CON4 0x0408 +#define MT6320_ANALDO_CON5 0x040a +#define MT6320_ANALDO_CON6 0x040c +#define MT6320_ANALDO_CON7 0x040e +#define MT6320_ANALDO_CON8 0x0410 +#define MT6320_ANALDO_CON9 0x0412 +#define MT6320_ANALDO_CON10 0x0414 +#define MT6320_ANALDO_CON11 0x0416 +#define MT6320_ANALDO_CON12 0x0418 +#define MT6320_ANALDO_CON13 0x041a +#define MT6320_ANALDO_CON14 0x041c +#define MT6320_ANALDO_CON15 0x041e +#define MT6320_DIGLDO_CON0 0x0420 +#define MT6320_DIGLDO_CON2 0x0422 +#define MT6320_DIGLDO_CON3 0x0424 +#define MT6320_DIGLDO_CON5 0x0426 +#define MT6320_DIGLDO_CON6 0x0428 +#define MT6320_DIGLDO_CON7 0x042a +#define MT6320_DIGLDO_CON8 0x042c +#define MT6320_DIGLDO_CON9 0x042e +#define MT6320_DIGLDO_CON10 0x0430 +#define MT6320_DIGLDO_CON11 0x0432 +#define MT6320_DIGLDO_CON12 0x0434 +#define MT6320_DIGLDO_CON13 0x0436 +#define MT6320_DIGLDO_CON14 0x0438 +#define MT6320_DIGLDO_CON15 0x043a +#define MT6320_DIGLDO_CON16 0x043c +#define MT6320_DIGLDO_CON17 0x043e +#define MT6320_DIGLDO_CON18 0x0440 +#define MT6320_DIGLDO_CON19 0x0442 +#define MT6320_DIGLDO_CON20 0x0444 +#define MT6320_DIGLDO_CON21 0x0446 +#define MT6320_DIGLDO_CON23 0x0448 +#define MT6320_DIGLDO_CON24 0x044a +#define MT6320_DIGLDO_CON26 0x044c +#define MT6320_DIGLDO_CON27 0x044e +#define MT6320_DIGLDO_CON28 0x0450 +#define MT6320_DIGLDO_CON29 0x0452 +#define MT6320_DIGLDO_CON30 0x0454 +#define MT6320_DIGLDO_CON31 0x0456 +#define MT6320_DIGLDO_CON32 0x0458 +#define MT6320_DIGLDO_CON33 0x045a +#define MT6320_DIGLDO_CON34 0x045c +#define MT6320_DIGLDO_CON35 0x045e +#define MT6320_DIGLDO_CON36 0x0460 +#define MT6320_DIGLDO_CON37 0x0462 +#define MT6320_DIGLDO_CON38 0x0464 +#define MT6320_DIGLDO_CON39 0x0466 +#define MT6320_DIGLDO_CON40 0x0468 +#define MT6320_DIGLDO_CON41 0x046a +#define MT6320_DIGLDO_CON42 0x046c +#define MT6320_DIGLDO_CON43 0x046e +#define MT6320_DIGLDO_CON44 0x0470 +#define MT6320_STRUP_CON0 0x0500 +#define MT6320_STRUP_CON2 0x0502 +#define MT6320_STRUP_CON3 0x0504 +#define MT6320_STRUP_CON4 0x0506 +#define MT6320_STRUP_CON5 0x0508 +#define MT6320_STRUP_CON6 0x050a +#define MT6320_STRUP_CON7 0x050c +#define MT6320_STRUP_CON8 0x050e +#define MT6320_STRUP_CON9 0x0510 +#define MT6320_AUXADC_ADC0 0x0512 +#define MT6320_AUXADC_ADC1 0x0514 +#define MT6320_AUXADC_ADC2 0x0516 +#define MT6320_AUXADC_ADC3 0x0518 +#define MT6320_AUXADC_ADC4 0x051a +#define MT6320_AUXADC_ADC5 0x051c +#define MT6320_AUXADC_ADC6 0x051e +#define MT6320_AUXADC_ADC7 0x0520 +#define MT6320_AUXADC_ADC8 0x0522 +#define MT6320_AUXADC_ADC9 0x0524 +#define MT6320_AUXADC_ADC10 0x0526 +#define MT6320_AUXADC_ADC11 0x0528 +#define MT6320_AUXADC_ADC12 0x052a +#define MT6320_AUXADC_ADC13 0x052c +#define MT6320_AUXADC_ADC14 0x052e +#define MT6320_AUXADC_ADC15 0x0530 +#define MT6320_AUXADC_ADC16 0x0532 +#define MT6320_AUXADC_ADC17 0x0534 +#define MT6320_AUXADC_ADC18 0x0536 +#define MT6320_AUXADC_ADC19 0x0538 +#define MT6320_AUXADC_ADC20 0x053a +#define MT6320_AUXADC_ADC21 0x053c +#define MT6320_AUXADC_ADC22 0x053e +#define MT6320_AUXADC_CON0 0x0540 +#define MT6320_AUXADC_CON1 0x0542 +#define MT6320_AUXADC_CON2 0x0544 +#define MT6320_AUXADC_CON3 0x0546 +#define MT6320_AUXADC_CON4 0x0548 +#define MT6320_AUXADC_CON5 0x054a +#define MT6320_AUXADC_CON6 0x054c +#define MT6320_AUXADC_CON7 0x054e +#define MT6320_AUXADC_CON8 0x0550 +#define MT6320_AUXADC_CON9 0x0552 +#define MT6320_AUXADC_CON10 0x0554 +#define MT6320_AUXADC_CON11 0x0556 +#define MT6320_AUXADC_CON12 0x0558 +#define MT6320_AUXADC_CON13 0x055a +#define MT6320_AUXADC_CON14 0x055c +#define MT6320_FLASH_CON0 0x055e +#define MT6320_FLASH_CON1 0x0560 +#define MT6320_FLASH_CON2 0x0562 +#define MT6320_KPLED_CON0 0x0564 +#define MT6320_KPLED_CON1 0x0566 +#define MT6320_KPLED_CON2 0x0568 +#define MT6320_ISINKS_CON0 0x056a +#define MT6320_ISINKS_CON1 0x056c +#define MT6320_ISINKS_CON2 0x056e +#define MT6320_ISINKS_CON3 0x0570 +#define MT6320_ISINKS_CON4 0x0572 +#define MT6320_ISINKS_CON5 0x0574 +#define MT6320_ISINKS_CON6 0x0576 +#define MT6320_ISINKS_CON7 0x0578 +#define MT6320_ISINKS_CON8 0x057a +#define MT6320_ISINKS_CON9 0x057c +#define MT6320_ISINKS_CON10 0x057e +#define MT6320_ISINKS_CON11 0x0580 +#define MT6320_ACCDET_CON0 0x0582 +#define MT6320_ACCDET_CON1 0x0584 +#define MT6320_ACCDET_CON2 0x0586 +#define MT6320_ACCDET_CON3 0x0588 +#define MT6320_ACCDET_CON4 0x058a +#define MT6320_ACCDET_CON5 0x058c +#define MT6320_ACCDET_CON6 0x058e +#define MT6320_ACCDET_CON7 0x0590 +#define MT6320_ACCDET_CON8 0x0592 +#define MT6320_ACCDET_CON9 0x0594 +#define MT6320_ACCDET_CON10 0x0596 +#define MT6320_ACCDET_CON11 0x0598 +#define MT6320_ACCDET_CON12 0x059a +#define MT6320_ACCDET_CON13 0x059c +#define MT6320_ACCDET_CON14 0x059e +#define MT6320_ACCDET_CON15 0x05a0 +#define MT6320_ACCDET_CON16 0x05a2 +#define MT6320_SPK_CON0 0x0600 +#define MT6320_SPK_CON1 0x0602 +#define MT6320_SPK_CON2 0x0604 +#define MT6320_SPK_CON3 0x0606 +#define MT6320_SPK_CON4 0x0608 +#define MT6320_SPK_CON5 0x060a +#define MT6320_SPK_CON6 0x060c +#define MT6320_SPK_CON7 0x060e +#define MT6320_SPK_CON8 0x0610 +#define MT6320_SPK_CON9 0x0612 +#define MT6320_SPK_CON10 0x0614 +#define MT6320_SPK_CON11 0x0616 +#define MT6320_FGADC_CON0 0x0618 +#define MT6320_FGADC_CON1 0x061a +#define MT6320_FGADC_CON2 0x061c +#define MT6320_FGADC_CON3 0x061e +#define MT6320_FGADC_CON4 0x0620 +#define MT6320_FGADC_CON5 0x0622 +#define MT6320_FGADC_CON6 0x0624 +#define MT6320_FGADC_CON7 0x0626 +#define MT6320_FGADC_CON8 0x0628 +#define MT6320_FGADC_CON9 0x062a +#define MT6320_FGADC_CON10 0x062c +#define MT6320_FGADC_CON11 0x062e +#define MT6320_FGADC_CON12 0x0630 +#define MT6320_FGADC_CON13 0x0632 +#define MT6320_FGADC_CON14 0x0634 +#define MT6320_FGADC_CON15 0x0636 +#define MT6320_FGADC_CON16 0x0638 +#define MT6320_FGADC_CON17 0x063a +#define MT6320_FGADC_CON18 0x063c +#define MT6320_FGADC_CON19 0x063e +#define MT6320_RTC_MIX_CON0 0x0640 +#define MT6320_RTC_MIX_CON1 0x0642 +#define MT6320_AUDDAC_CON0 0x0700 +#define MT6320_AUDBUF_CFG0 0x0702 +#define MT6320_AUDBUF_CFG1 0x0704 +#define MT6320_AUDBUF_CFG2 0x0706 +#define MT6320_AUDBUF_CFG3 0x0708 +#define MT6320_AUDBUF_CFG4 0x070a +#define MT6320_IBIASDIST_CFG0 0x070c +#define MT6320_AUDACCDEPOP_CFG0 0x070e +#define MT6320_AUD_IV_CFG0 0x0710 +#define MT6320_AUDCLKGEN_CFG0 0x0712 +#define MT6320_AUDLDO_CFG0 0x0714 +#define MT6320_AUDLDO_CFG1 0x0716 +#define MT6320_AUDNVREGGLB_CFG0 0x0718 +#define MT6320_AUD_NCP0 0x071a +#define MT6320_AUDPREAMP_CON0 0x071c +#define MT6320_AUDADC_CON0 0x071e +#define MT6320_AUDADC_CON1 0x0720 +#define MT6320_AUDADC_CON2 0x0722 +#define MT6320_AUDADC_CON3 0x0724 +#define MT6320_AUDADC_CON4 0x0726 +#define MT6320_AUDADC_CON5 0x0728 +#define MT6320_AUDADC_CON6 0x072a +#define MT6320_AUDDIGMI_CON0 0x072c +#define MT6320_AUDLSBUF_CON0 0x072e +#define MT6320_AUDLSBUF_CON1 0x0730 +#define MT6320_AUDENCSPARE_CON0 0x0732 +#define MT6320_AUDENCCLKSQ_CON0 0x0734 +#define MT6320_AUDPREAMPGAIN_CON0 0x0736 +#define MT6320_ZCD_CON0 0x0738 +#define MT6320_ZCD_CON1 0x073a +#define MT6320_ZCD_CON2 0x073c +#define MT6320_ZCD_CON3 0x073e +#define MT6320_ZCD_CON4 0x0740 +#define MT6320_ZCD_CON5 0x0742 +#define MT6320_NCP_CLKDIV_CON0 0x0744 +#define MT6320_NCP_CLKDIV_CON1 0x0746 + +#endif /* __MFD_MT6320_REGISTERS_H__ */ diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h index b774c3a4bb62e5..dadffd3669591d 100644 --- a/include/linux/mfd/mt6397/core.h +++ b/include/linux/mfd/mt6397/core.h @@ -11,10 +11,11 @@ #include enum chip_id { + MT6320_CHIP_ID = 0x20, MT6323_CHIP_ID = 0x23, - MT6328_CHIP_ID = 0x30, - MT6331_CHIP_ID = 0x20, - MT6332_CHIP_ID = 0x20, + MT6328_CHIP_ID = 0x28, + MT6331_CHIP_ID = 0x31, + MT6332_CHIP_ID = 0x32, MT6357_CHIP_ID = 0x57, MT6358_CHIP_ID = 0x58, MT6359_CHIP_ID = 0x59, diff --git a/include/linux/regulator/mt6320-regulator.h b/include/linux/regulator/mt6320-regulator.h new file mode 100644 index 00000000000000..52214dc080545c --- /dev/null +++ b/include/linux/regulator/mt6320-regulator.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2026 Akari Tsuyukusa + * + * based on MT6589 v3.4.67 downstream kernel + * Copyright (c) 2014 BQ + * Copyright (c) 2014 MediaTek Inc. + */ + +#ifndef __LINUX_REGULATOR_MT6320_H +#define __LINUX_REGULATOR_MT6320_H + +enum { + /* Buck */ + MT6320_ID_VPROC, + MT6320_ID_VSRAM, + MT6320_ID_VCORE, + MT6320_ID_VM, + MT6320_ID_VIO18, + MT6320_ID_VPA, + MT6320_ID_VRF18, + MT6320_ID_VRF18_2, + + /* Digital LDO */ + MT6320_ID_VIO28, + MT6320_ID_VUSB, + MT6320_ID_VMC1, + MT6320_ID_VMCH1, + MT6320_ID_VEMC_3V3, + MT6320_ID_VEMC_1V8, + MT6320_ID_VGP1, + MT6320_ID_VGP2, + MT6320_ID_VGP3, + MT6320_ID_VGP4, + MT6320_ID_VGP5, + MT6320_ID_VGP6, + MT6320_ID_VSIM1, + MT6320_ID_VSIM2, + MT6320_ID_VIBR, + MT6320_ID_VRTC, + MT6320_ID_VAST, + + /* Analog LDO */ + MT6320_ID_VRF28, + MT6320_ID_VRF28_2, + MT6320_ID_VTCXO, + MT6320_ID_VTCXO_2, + MT6320_ID_VA, + MT6320_ID_VA28, + MT6320_ID_VCAMA, + + MT6320_ID_RG_MAX, +}; + +#define MT6320_MAX_REGULATOR MT6320_ID_RG_MAX + +#endif /* __LINUX_REGULATOR_MT6320_H */