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112 lines (84 loc) · 4.5 KB
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D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/alu.sv {1 {vlog -work work2 -sv -stats=none D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/alu.sv
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
-- Compiling module ALU
Top level modules:
ALU
} {} {}} D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/instdec.sv {1 {vlog -work work2 -sv -stats=none D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/instdec.sv
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
-- Compiling module instdec
Top level modules:
instdec
} {} {}} D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/shifter_tb.sv {1 {vlog -work work2 -sv -stats=none D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/shifter_tb.sv
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
-- Compiling module shifter_tb
Top level modules:
shifter_tb
} {} {}} D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/FSM_tb.sv {1 {vlog -work work2 -sv -stats=none D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/FSM_tb.sv
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
-- Compiling module FSM_head_tb
-- Compiling module FSM_tb
-- Compiling module FSMout_tb
Top level modules:
FSM_head_tb
FSM_tb
FSMout_tb
} {} {}} D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/datapath_tb.sv {1 {vlog -work work2 -sv -stats=none D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/datapath_tb.sv
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
-- Compiling module datapath_tb
Top level modules:
datapath_tb
} {} {}} D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/shifter.sv {1 {vlog -work work2 -sv -stats=none D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/shifter.sv
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
-- Compiling module shifter
Top level modules:
shifter
} {} {}} D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/regfile.sv {1 {vlog -work work2 -sv -stats=none D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/regfile.sv
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
-- Compiling module regfile
-- Compiling module WriteData
-- Compiling module ReadData
Top level modules:
regfile
} {} {}} D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/alu_tb.sv {1 {vlog -work work2 -sv -stats=none D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/alu_tb.sv
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
-- Compiling module ALU_tb
Top level modules:
ALU_tb
} {} {}} D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/datapath.sv {1 {vlog -work work2 -sv -stats=none D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/datapath.sv
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
-- Compiling module datapath
-- Compiling module Mux4
-- Compiling module Mux2
-- Compiling module minireg
-- Compiling module statusreg
Top level modules:
datapath
} {} {}} D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/instdec_tb.sv {1 {vlog -work work2 -sv -stats=none D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/instdec_tb.sv
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
-- Compiling module instdec_tb
Top level modules:
instdec_tb
} {} {}} D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/lab6_top.sv {1 {vlog -work work2 -sv -stats=none D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/lab6_top.sv
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
-- Compiling module lab6_top
-- Compiling module input_iface
-- Compiling module vDFF
-- Compiling module sseg
Top level modules:
lab6_top
} {} {}} D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/cpu.sv {1 {vlog -work work2 -sv -stats=none D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/cpu.sv
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
-- Compiling module cpu
Top level modules:
cpu
} {} {}} D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/regfile_tb.sv {1 {vlog -work work2 -sv -stats=none D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/regfile_tb.sv
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
-- Compiling module regfile_tb
Top level modules:
regfile_tb
} {} {}} D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/lab6_autograder_check.sv {1 {vlog -work work2 -sv -stats=none D:/UBC/Verilog/Lab6/lab-6-l1d-TZlindra-main/lab6_autograder_check.sv
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
-- Compiling module lab6_check
Top level modules:
lab6_check
} {} {}}