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sample.cfg
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114 lines (105 loc) · 3.01 KB
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sim = {
#periodicStatsInterval = 2000L;
#profileByPc = True;
cycleTimeout = 20; # terminate simulation if stalled on single cycle
taskTimeout = 120; # terminate simulation if no task commits or aborts
gvtTimeout = 180; # terminate simulation if GVT does not update
ffTimeout = 60; # terminate simulation if stuck in fast-forwarding
#ffHeartbeats = 7L;
#maxHeartbeats = 42L;
};
sys = {
lineSize = 64;
frequency = 2000; # MHz
cores = {
cores = 16;
type = "Simple";
dcache = "l1d";
};
robs = {
robs = 4;
gvtUpdatePeriod = 200; # default 200 cycles
maxFrameDepth = 4;
taskQ = {
capacity = 256;
# overflow marker that triggers task spilling
overflow = 224;
# number of tied tasks allowed (must be < overflow and > cq cap)
# FIXME(dsm): With the current sizes, precede_stallers_pls
# deadlocks with anything larger than 176. There seems to be a
# corner case that allows the task queue to fill up...
tiedCapacity = 176;
# number of removable tasks to protect/cache in the queue
# TODO(mcj) rename to something different, like untiedCapacity?
# TODO(dsm): Remove overflowWatcher? tiedCapacity seems to make this irrelevant
#removableCapacity = 16;
#tasksPerSpiller = 16;
};
commitQ = {
# capacity per ROB, including executing and waiting tasks
capacity = 64;
# Admit a task to a full commit queue if it precedes
# {"Any", "Half", "All"} tasks in the CQ.
admissionPolicy = "Half";
};
taskMapper = {
type = "Hint";
};
tieBreakPolicy = "Lazy";
clearTieBreakerOnAbort = true;
serializeSpatialIDs = true;
mayspecSpeculationMode = "Must";
abortHandler = {
stallPolicy = "Never";
selectiveAborts = true;
};
addressSet = {
type = "Precise";
};
};
caches = {
l1d = {
caches = 16;
size = 16384;
array = {
type = "SetAssoc";
ways = 8;
};
latency = 2;
parent = "l2";
};
l2 = {
caches = 4;
banks = 1;
size = 262144;
latency = 7;
array = {
type = "SetAssoc";
ways = 8;
};
linesPerCanary = 1;
parent = "l3";
};
l3 = {
caches = 1;
banks = 16;
size = 4194304;
latency = 20;
array = {
hash = "H3";
type = "SetAssoc";
ways = 16;
};
parent = "mem";
};
};
mem = {
type = "Simple";
controllers = 4;
latency = 120;
nodes = "edges";
};
net = {
nodes = 4;
};
};