RISC_R_dump.vcd

$date
	Thu Apr 20 21:02:48 2023
$end
$version
	ModelSim Version 10.6d
$end
$timescale
	1ns
$end

$scope module RISC_V_tb $end
$var parameter 32 ! CLK_PERIOD $end
$var reg 1 " rst $end
$var reg 1 # clk $end

$scope module RISC_R_instance $end
$var wire 1 $ clk $end
$var wire 1 % rst $end
$var reg 32 & instruction [31:0] $end
$var reg 32 ' wdata_mem [31:0] $end
$var reg 32 ( rdata2 [31:0] $end
$var reg 1 ) reg_wr $end
$var reg 1 * A_sel $end
$var reg 1 + PC_sel $end
$var reg 1 , B_sel $end
$var reg 1 - br_taken $end
$var reg 1 . mem_wr $end
$var reg 3 / load_ctrl [2:0] $end
$var reg 2 0 wb_sel [1:0] $end
$var reg 2 1 mem_col [1:0] $end
$var reg 4 2 ALUctrl [3:0] $end
$var reg 4 3 mask [3:0] $end

$scope module Controller_instance $end
$var parameter 5 4 R_type $end
$var parameter 5 5 I_type $end
$var parameter 5 6 Load_type $end
$var parameter 5 7 S_type $end
$var parameter 5 8 B_type $end
$var parameter 5 9 J_type $end
$var parameter 5 : Jalr_type $end
$var parameter 5 ; lui_type $end
$var parameter 5 < auipc_type $end
$var wire 1 $ clk $end
$var wire 1 % rst $end
$var wire 1 = instruction [31] $end
$var wire 1 > instruction [30] $end
$var wire 1 ? instruction [29] $end
$var wire 1 @ instruction [28] $end
$var wire 1 A instruction [27] $end
$var wire 1 B instruction [26] $end
$var wire 1 C instruction [25] $end
$var wire 1 D instruction [24] $end
$var wire 1 E instruction [23] $end
$var wire 1 F instruction [22] $end
$var wire 1 G instruction [21] $end
$var wire 1 H instruction [20] $end
$var wire 1 I instruction [19] $end
$var wire 1 J instruction [18] $end
$var wire 1 K instruction [17] $end
$var wire 1 L instruction [16] $end
$var wire 1 M instruction [15] $end
$var wire 1 N instruction [14] $end
$var wire 1 O instruction [13] $end
$var wire 1 P instruction [12] $end
$var wire 1 Q instruction [11] $end
$var wire 1 R instruction [10] $end
$var wire 1 S instruction [9] $end
$var wire 1 T instruction [8] $end
$var wire 1 U instruction [7] $end
$var wire 1 V instruction [6] $end
$var wire 1 W instruction [5] $end
$var wire 1 X instruction [4] $end
$var wire 1 Y instruction [3] $end
$var wire 1 Z instruction [2] $end
$var wire 1 [ instruction [1] $end
$var wire 1 \ instruction [0] $end
$var wire 1 ] b_taken $end
$var reg 4 ^ ALUctrl [3:0] $end
$var reg 3 _ load_ctrl [2:0] $end
$var reg 1 ` mem_wr $end
$var reg 1 a A_sel $end
$var reg 1 b B_sel $end
$var reg 1 c reg_wr $end
$var reg 1 d PC_sel $end
$var reg 2 e wb_sel [1:0] $end
$var reg 7 f opcode [6:0] $end
$var reg 1 g func7 $end
$var reg 3 h func3 [2:0] $end
$upscope $end

$scope module data_path_instance $end
$var parameter 5 i I_type $end
$var parameter 5 j Load_type $end
$var parameter 5 k B_type $end
$var parameter 5 l S_type $end
$var parameter 5 m J_type $end
$var parameter 5 n Jalr_type $end
$var parameter 5 o lui_type $end
$var parameter 5 p auipc_type $end
$var wire 1 $ clk $end
$var wire 1 % rst $end
$var wire 1 q reg_wr $end
$var wire 1 r A_sel $end
$var wire 1 s B_sel $end
$var wire 1 t mem_wr $end
$var wire 1 u PC_sel $end
$var wire 1 v wb_sel [1] $end
$var wire 1 w wb_sel [0] $end
$var wire 1 x load_ctrl [2] $end
$var wire 1 y load_ctrl [1] $end
$var wire 1 z load_ctrl [0] $end
$var wire 1 { ALUctrl [3] $end
$var wire 1 | ALUctrl [2] $end
$var wire 1 } ALUctrl [1] $end
$var wire 1 ~ ALUctrl [0] $end
$var reg 32 !! instruction [31:0] $end
$var reg 1 "! b_taken $end
$var reg 32 #! instruction_addr [31:0] $end
$var reg 32 $! wdata [31:0] $end
$var reg 32 %! ALUresult [31:0] $end
$var reg 32 &! ReadData [31:0] $end
$var reg 32 '! rdata1 [31:0] $end
$var reg 32 (! rdata2 [31:0] $end
$var reg 32 )! PC [31:0] $end
$var reg 32 *! PC_mux_o [31:0] $end
$var reg 5 +! raddr1 [4:0] $end
$var reg 5 ,! raddr2 [4:0] $end
$var reg 5 -! waddr [4:0] $end
$var reg 32 .! rd2 [31:0] $end
$var reg 1 /! RegWrite $end
$var reg 3 0! func3 [2:0] $end
$var reg 32 1! ALU_o [31:0] $end
$var reg 32 2! mem_data [31:0] $end
$var reg 32 3! imm [31:0] $end
$var reg 32 4! ALU_op_b [31:0] $end
$var reg 32 5! ALU_op_a [31:0] $end
$var reg 2 6! mem_col [1:0] $end

$scope module Regfile_instance $end
$var wire 1 7! rst $end
$var wire 1 $ clk $end
$var wire 1 q write_en $end
$var wire 1 8! rs1_in [4] $end
$var wire 1 9! rs1_in [3] $end
$var wire 1 :! rs1_in [2] $end
$var wire 1 ;! rs1_in [1] $end
$var wire 1 <! rs1_in [0] $end
$var wire 1 =! rs2_in [4] $end
$var wire 1 >! rs2_in [3] $end
$var wire 1 ?! rs2_in [2] $end
$var wire 1 @! rs2_in [1] $end
$var wire 1 A! rs2_in [0] $end
$var wire 1 B! rd [4] $end
$var wire 1 C! rd [3] $end
$var wire 1 D! rd [2] $end
$var wire 1 E! rd [1] $end
$var wire 1 F! rd [0] $end
$var wire 1 G! write_data [31] $end
$var wire 1 H! write_data [30] $end
$var wire 1 I! write_data [29] $end
$var wire 1 J! write_data [28] $end
$var wire 1 K! write_data [27] $end
$var wire 1 L! write_data [26] $end
$var wire 1 M! write_data [25] $end
$var wire 1 N! write_data [24] $end
$var wire 1 O! write_data [23] $end
$var wire 1 P! write_data [22] $end
$var wire 1 Q! write_data [21] $end
$var wire 1 R! write_data [20] $end
$var wire 1 S! write_data [19] $end
$var wire 1 T! write_data [18] $end
$var wire 1 U! write_data [17] $end
$var wire 1 V! write_data [16] $end
$var wire 1 W! write_data [15] $end
$var wire 1 X! write_data [14] $end
$var wire 1 Y! write_data [13] $end
$var wire 1 Z! write_data [12] $end
$var wire 1 [! write_data [11] $end
$var wire 1 \! write_data [10] $end
$var wire 1 ]! write_data [9] $end
$var wire 1 ^! write_data [8] $end
$var wire 1 _! write_data [7] $end
$var wire 1 `! write_data [6] $end
$var wire 1 a! write_data [5] $end
$var wire 1 b! write_data [4] $end
$var wire 1 c! write_data [3] $end
$var wire 1 d! write_data [2] $end
$var wire 1 e! write_data [1] $end
$var wire 1 f! write_data [0] $end
$var reg 32 g! rs1_out [31:0] $end
$var reg 32 h! rs2_out [31:0] $end
$var reg 32 i! result [31:0] $end
$var reg 1 j! valid_add1 $end
$var reg 1 k! valid_add2 $end
$var reg 1 l! valid_write_en $end
$upscope $end

$scope module ALU_instance $end
$var wire 1 m! a_in [31] $end
$var wire 1 n! a_in [30] $end
$var wire 1 o! a_in [29] $end
$var wire 1 p! a_in [28] $end
$var wire 1 q! a_in [27] $end
$var wire 1 r! a_in [26] $end
$var wire 1 s! a_in [25] $end
$var wire 1 t! a_in [24] $end
$var wire 1 u! a_in [23] $end
$var wire 1 v! a_in [22] $end
$var wire 1 w! a_in [21] $end
$var wire 1 x! a_in [20] $end
$var wire 1 y! a_in [19] $end
$var wire 1 z! a_in [18] $end
$var wire 1 {! a_in [17] $end
$var wire 1 |! a_in [16] $end
$var wire 1 }! a_in [15] $end
$var wire 1 ~! a_in [14] $end
$var wire 1 !" a_in [13] $end
$var wire 1 "" a_in [12] $end
$var wire 1 #" a_in [11] $end
$var wire 1 $" a_in [10] $end
$var wire 1 %" a_in [9] $end
$var wire 1 &" a_in [8] $end
$var wire 1 '" a_in [7] $end
$var wire 1 (" a_in [6] $end
$var wire 1 )" a_in [5] $end
$var wire 1 *" a_in [4] $end
$var wire 1 +" a_in [3] $end
$var wire 1 ," a_in [2] $end
$var wire 1 -" a_in [1] $end
$var wire 1 ." a_in [0] $end
$var wire 1 /" b_in [31] $end
$var wire 1 0" b_in [30] $end
$var wire 1 1" b_in [29] $end
$var wire 1 2" b_in [28] $end
$var wire 1 3" b_in [27] $end
$var wire 1 4" b_in [26] $end
$var wire 1 5" b_in [25] $end
$var wire 1 6" b_in [24] $end
$var wire 1 7" b_in [23] $end
$var wire 1 8" b_in [22] $end
$var wire 1 9" b_in [21] $end
$var wire 1 :" b_in [20] $end
$var wire 1 ;" b_in [19] $end
$var wire 1 <" b_in [18] $end
$var wire 1 =" b_in [17] $end
$var wire 1 >" b_in [16] $end
$var wire 1 ?" b_in [15] $end
$var wire 1 @" b_in [14] $end
$var wire 1 A" b_in [13] $end
$var wire 1 B" b_in [12] $end
$var wire 1 C" b_in [11] $end
$var wire 1 D" b_in [10] $end
$var wire 1 E" b_in [9] $end
$var wire 1 F" b_in [8] $end
$var wire 1 G" b_in [7] $end
$var wire 1 H" b_in [6] $end
$var wire 1 I" b_in [5] $end
$var wire 1 J" b_in [4] $end
$var wire 1 K" b_in [3] $end
$var wire 1 L" b_in [2] $end
$var wire 1 M" b_in [1] $end
$var wire 1 N" b_in [0] $end
$var wire 1 { ALUctrl [3] $end
$var wire 1 | ALUctrl [2] $end
$var wire 1 } ALUctrl [1] $end
$var wire 1 ~ ALUctrl [0] $end
$var reg 32 O" result_o [31:0] $end
$var reg 32 P" and_res [31:0] $end
$var reg 32 Q" or_res [31:0] $end
$var reg 32 R" xor_res [31:0] $end
$var reg 32 S" add_sub_res [31:0] $end
$var reg 32 T" SLT_res [31:0] $end
$var reg 32 U" SLTU_res [31:0] $end
$var reg 32 V" t [31:0] $end
$var reg 32 W" SLL_res [31:0] $end
$var reg 32 X" SRL_res [31:0] $end
$var reg 32 Y" SRA_res [31:0] $end
$var reg 32 Z" mux1_o [31:0] $end
$var reg 1 [" C_out $end
$var reg 1 \" N $end
$var reg 1 ]" V $end
$var reg 1 ^" W $end
$var reg 1 _" C $end

$scope module ALU_mux $end
$var wire 1 `" i1 [31] $end
$var wire 1 a" i1 [30] $end
$var wire 1 b" i1 [29] $end
$var wire 1 c" i1 [28] $end
$var wire 1 d" i1 [27] $end
$var wire 1 e" i1 [26] $end
$var wire 1 f" i1 [25] $end
$var wire 1 g" i1 [24] $end
$var wire 1 h" i1 [23] $end
$var wire 1 i" i1 [22] $end
$var wire 1 j" i1 [21] $end
$var wire 1 k" i1 [20] $end
$var wire 1 l" i1 [19] $end
$var wire 1 m" i1 [18] $end
$var wire 1 n" i1 [17] $end
$var wire 1 o" i1 [16] $end
$var wire 1 p" i1 [15] $end
$var wire 1 q" i1 [14] $end
$var wire 1 r" i1 [13] $end
$var wire 1 s" i1 [12] $end
$var wire 1 t" i1 [11] $end
$var wire 1 u" i1 [10] $end
$var wire 1 v" i1 [9] $end
$var wire 1 w" i1 [8] $end
$var wire 1 x" i1 [7] $end
$var wire 1 y" i1 [6] $end
$var wire 1 z" i1 [5] $end
$var wire 1 {" i1 [4] $end
$var wire 1 |" i1 [3] $end
$var wire 1 }" i1 [2] $end
$var wire 1 ~" i1 [1] $end
$var wire 1 !# i1 [0] $end
$var wire 1 "# i2 [31] $end
$var wire 1 ## i2 [30] $end
$var wire 1 $# i2 [29] $end
$var wire 1 %# i2 [28] $end
$var wire 1 &# i2 [27] $end
$var wire 1 '# i2 [26] $end
$var wire 1 (# i2 [25] $end
$var wire 1 )# i2 [24] $end
$var wire 1 *# i2 [23] $end
$var wire 1 +# i2 [22] $end
$var wire 1 ,# i2 [21] $end
$var wire 1 -# i2 [20] $end
$var wire 1 .# i2 [19] $end
$var wire 1 /# i2 [18] $end
$var wire 1 0# i2 [17] $end
$var wire 1 1# i2 [16] $end
$var wire 1 2# i2 [15] $end
$var wire 1 3# i2 [14] $end
$var wire 1 4# i2 [13] $end
$var wire 1 5# i2 [12] $end
$var wire 1 6# i2 [11] $end
$var wire 1 7# i2 [10] $end
$var wire 1 8# i2 [9] $end
$var wire 1 9# i2 [8] $end
$var wire 1 :# i2 [7] $end
$var wire 1 ;# i2 [6] $end
$var wire 1 <# i2 [5] $end
$var wire 1 =# i2 [4] $end
$var wire 1 ># i2 [3] $end
$var wire 1 ?# i2 [2] $end
$var wire 1 @# i2 [1] $end
$var wire 1 A# i2 [0] $end
$var wire 1 B# i3 [31] $end
$var wire 1 C# i3 [30] $end
$var wire 1 D# i3 [29] $end
$var wire 1 E# i3 [28] $end
$var wire 1 F# i3 [27] $end
$var wire 1 G# i3 [26] $end
$var wire 1 H# i3 [25] $end
$var wire 1 I# i3 [24] $end
$var wire 1 J# i3 [23] $end
$var wire 1 K# i3 [22] $end
$var wire 1 L# i3 [21] $end
$var wire 1 M# i3 [20] $end
$var wire 1 N# i3 [19] $end
$var wire 1 O# i3 [18] $end
$var wire 1 P# i3 [17] $end
$var wire 1 Q# i3 [16] $end
$var wire 1 R# i3 [15] $end
$var wire 1 S# i3 [14] $end
$var wire 1 T# i3 [13] $end
$var wire 1 U# i3 [12] $end
$var wire 1 V# i3 [11] $end
$var wire 1 W# i3 [10] $end
$var wire 1 X# i3 [9] $end
$var wire 1 Y# i3 [8] $end
$var wire 1 Z# i3 [7] $end
$var wire 1 [# i3 [6] $end
$var wire 1 \# i3 [5] $end
$var wire 1 ]# i3 [4] $end
$var wire 1 ^# i3 [3] $end
$var wire 1 _# i3 [2] $end
$var wire 1 `# i3 [1] $end
$var wire 1 a# i3 [0] $end
$var wire 1 b# i4 [31] $end
$var wire 1 c# i4 [30] $end
$var wire 1 d# i4 [29] $end
$var wire 1 e# i4 [28] $end
$var wire 1 f# i4 [27] $end
$var wire 1 g# i4 [26] $end
$var wire 1 h# i4 [25] $end
$var wire 1 i# i4 [24] $end
$var wire 1 j# i4 [23] $end
$var wire 1 k# i4 [22] $end
$var wire 1 l# i4 [21] $end
$var wire 1 m# i4 [20] $end
$var wire 1 n# i4 [19] $end
$var wire 1 o# i4 [18] $end
$var wire 1 p# i4 [17] $end
$var wire 1 q# i4 [16] $end
$var wire 1 r# i4 [15] $end
$var wire 1 s# i4 [14] $end
$var wire 1 t# i4 [13] $end
$var wire 1 u# i4 [12] $end
$var wire 1 v# i4 [11] $end
$var wire 1 w# i4 [10] $end
$var wire 1 x# i4 [9] $end
$var wire 1 y# i4 [8] $end
$var wire 1 z# i4 [7] $end
$var wire 1 {# i4 [6] $end
$var wire 1 |# i4 [5] $end
$var wire 1 }# i4 [4] $end
$var wire 1 ~# i4 [3] $end
$var wire 1 !$ i4 [2] $end
$var wire 1 "$ i4 [1] $end
$var wire 1 #$ i4 [0] $end
$var wire 1 $$ i5 [31] $end
$var wire 1 %$ i5 [30] $end
$var wire 1 &$ i5 [29] $end
$var wire 1 '$ i5 [28] $end
$var wire 1 ($ i5 [27] $end
$var wire 1 )$ i5 [26] $end
$var wire 1 *$ i5 [25] $end
$var wire 1 +$ i5 [24] $end
$var wire 1 ,$ i5 [23] $end
$var wire 1 -$ i5 [22] $end
$var wire 1 .$ i5 [21] $end
$var wire 1 /$ i5 [20] $end
$var wire 1 0$ i5 [19] $end
$var wire 1 1$ i5 [18] $end
$var wire 1 2$ i5 [17] $end
$var wire 1 3$ i5 [16] $end
$var wire 1 4$ i5 [15] $end
$var wire 1 5$ i5 [14] $end
$var wire 1 6$ i5 [13] $end
$var wire 1 7$ i5 [12] $end
$var wire 1 8$ i5 [11] $end
$var wire 1 9$ i5 [10] $end
$var wire 1 :$ i5 [9] $end
$var wire 1 ;$ i5 [8] $end
$var wire 1 <$ i5 [7] $end
$var wire 1 =$ i5 [6] $end
$var wire 1 >$ i5 [5] $end
$var wire 1 ?$ i5 [4] $end
$var wire 1 @$ i5 [3] $end
$var wire 1 A$ i5 [2] $end
$var wire 1 B$ i5 [1] $end
$var wire 1 C$ i5 [0] $end
$var wire 1 D$ i6 [31] $end
$var wire 1 E$ i6 [30] $end
$var wire 1 F$ i6 [29] $end
$var wire 1 G$ i6 [28] $end
$var wire 1 H$ i6 [27] $end
$var wire 1 I$ i6 [26] $end
$var wire 1 J$ i6 [25] $end
$var wire 1 K$ i6 [24] $end
$var wire 1 L$ i6 [23] $end
$var wire 1 M$ i6 [22] $end
$var wire 1 N$ i6 [21] $end
$var wire 1 O$ i6 [20] $end
$var wire 1 P$ i6 [19] $end
$var wire 1 Q$ i6 [18] $end
$var wire 1 R$ i6 [17] $end
$var wire 1 S$ i6 [16] $end
$var wire 1 T$ i6 [15] $end
$var wire 1 U$ i6 [14] $end
$var wire 1 V$ i6 [13] $end
$var wire 1 W$ i6 [12] $end
$var wire 1 X$ i6 [11] $end
$var wire 1 Y$ i6 [10] $end
$var wire 1 Z$ i6 [9] $end
$var wire 1 [$ i6 [8] $end
$var wire 1 \$ i6 [7] $end
$var wire 1 ]$ i6 [6] $end
$var wire 1 ^$ i6 [5] $end
$var wire 1 _$ i6 [4] $end
$var wire 1 `$ i6 [3] $end
$var wire 1 a$ i6 [2] $end
$var wire 1 b$ i6 [1] $end
$var wire 1 c$ i6 [0] $end
$var wire 1 d$ i7 [31] $end
$var wire 1 e$ i7 [30] $end
$var wire 1 f$ i7 [29] $end
$var wire 1 g$ i7 [28] $end
$var wire 1 h$ i7 [27] $end
$var wire 1 i$ i7 [26] $end
$var wire 1 j$ i7 [25] $end
$var wire 1 k$ i7 [24] $end
$var wire 1 l$ i7 [23] $end
$var wire 1 m$ i7 [22] $end
$var wire 1 n$ i7 [21] $end
$var wire 1 o$ i7 [20] $end
$var wire 1 p$ i7 [19] $end
$var wire 1 q$ i7 [18] $end
$var wire 1 r$ i7 [17] $end
$var wire 1 s$ i7 [16] $end
$var wire 1 t$ i7 [15] $end
$var wire 1 u$ i7 [14] $end
$var wire 1 v$ i7 [13] $end
$var wire 1 w$ i7 [12] $end
$var wire 1 x$ i7 [11] $end
$var wire 1 y$ i7 [10] $end
$var wire 1 z$ i7 [9] $end
$var wire 1 {$ i7 [8] $end
$var wire 1 |$ i7 [7] $end
$var wire 1 }$ i7 [6] $end
$var wire 1 ~$ i7 [5] $end
$var wire 1 !% i7 [4] $end
$var wire 1 "% i7 [3] $end
$var wire 1 #% i7 [2] $end
$var wire 1 $% i7 [1] $end
$var wire 1 %% i7 [0] $end
$var wire 1 &% i8 [31] $end
$var wire 1 '% i8 [30] $end
$var wire 1 (% i8 [29] $end
$var wire 1 )% i8 [28] $end
$var wire 1 *% i8 [27] $end
$var wire 1 +% i8 [26] $end
$var wire 1 ,% i8 [25] $end
$var wire 1 -% i8 [24] $end
$var wire 1 .% i8 [23] $end
$var wire 1 /% i8 [22] $end
$var wire 1 0% i8 [21] $end
$var wire 1 1% i8 [20] $end
$var wire 1 2% i8 [19] $end
$var wire 1 3% i8 [18] $end
$var wire 1 4% i8 [17] $end
$var wire 1 5% i8 [16] $end
$var wire 1 6% i8 [15] $end
$var wire 1 7% i8 [14] $end
$var wire 1 8% i8 [13] $end
$var wire 1 9% i8 [12] $end
$var wire 1 :% i8 [11] $end
$var wire 1 ;% i8 [10] $end
$var wire 1 <% i8 [9] $end
$var wire 1 =% i8 [8] $end
$var wire 1 >% i8 [7] $end
$var wire 1 ?% i8 [6] $end
$var wire 1 @% i8 [5] $end
$var wire 1 A% i8 [4] $end
$var wire 1 B% i8 [3] $end
$var wire 1 C% i8 [2] $end
$var wire 1 D% i8 [1] $end
$var wire 1 E% i8 [0] $end
$var wire 1 F% i9 [31] $end
$var wire 1 G% i9 [30] $end
$var wire 1 H% i9 [29] $end
$var wire 1 I% i9 [28] $end
$var wire 1 J% i9 [27] $end
$var wire 1 K% i9 [26] $end
$var wire 1 L% i9 [25] $end
$var wire 1 M% i9 [24] $end
$var wire 1 N% i9 [23] $end
$var wire 1 O% i9 [22] $end
$var wire 1 P% i9 [21] $end
$var wire 1 Q% i9 [20] $end
$var wire 1 R% i9 [19] $end
$var wire 1 S% i9 [18] $end
$var wire 1 T% i9 [17] $end
$var wire 1 U% i9 [16] $end
$var wire 1 V% i9 [15] $end
$var wire 1 W% i9 [14] $end
$var wire 1 X% i9 [13] $end
$var wire 1 Y% i9 [12] $end
$var wire 1 Z% i9 [11] $end
$var wire 1 [% i9 [10] $end
$var wire 1 \% i9 [9] $end
$var wire 1 ]% i9 [8] $end
$var wire 1 ^% i9 [7] $end
$var wire 1 _% i9 [6] $end
$var wire 1 `% i9 [5] $end
$var wire 1 a% i9 [4] $end
$var wire 1 b% i9 [3] $end
$var wire 1 c% i9 [2] $end
$var wire 1 d% i9 [1] $end
$var wire 1 e% i9 [0] $end
$var wire 1 f% i10 [31] $end
$var wire 1 g% i10 [30] $end
$var wire 1 h% i10 [29] $end
$var wire 1 i% i10 [28] $end
$var wire 1 j% i10 [27] $end
$var wire 1 k% i10 [26] $end
$var wire 1 l% i10 [25] $end
$var wire 1 m% i10 [24] $end
$var wire 1 n% i10 [23] $end
$var wire 1 o% i10 [22] $end
$var wire 1 p% i10 [21] $end
$var wire 1 q% i10 [20] $end
$var wire 1 r% i10 [19] $end
$var wire 1 s% i10 [18] $end
$var wire 1 t% i10 [17] $end
$var wire 1 u% i10 [16] $end
$var wire 1 v% i10 [15] $end
$var wire 1 w% i10 [14] $end
$var wire 1 x% i10 [13] $end
$var wire 1 y% i10 [12] $end
$var wire 1 z% i10 [11] $end
$var wire 1 {% i10 [10] $end
$var wire 1 |% i10 [9] $end
$var wire 1 }% i10 [8] $end
$var wire 1 ~% i10 [7] $end
$var wire 1 !& i10 [6] $end
$var wire 1 "& i10 [5] $end
$var wire 1 #& i10 [4] $end
$var wire 1 $& i10 [3] $end
$var wire 1 %& i10 [2] $end
$var wire 1 && i10 [1] $end
$var wire 1 '& i10 [0] $end
$var wire 1 /" i11 [31] $end
$var wire 1 0" i11 [30] $end
$var wire 1 1" i11 [29] $end
$var wire 1 2" i11 [28] $end
$var wire 1 3" i11 [27] $end
$var wire 1 4" i11 [26] $end
$var wire 1 5" i11 [25] $end
$var wire 1 6" i11 [24] $end
$var wire 1 7" i11 [23] $end
$var wire 1 8" i11 [22] $end
$var wire 1 9" i11 [21] $end
$var wire 1 :" i11 [20] $end
$var wire 1 ;" i11 [19] $end
$var wire 1 <" i11 [18] $end
$var wire 1 =" i11 [17] $end
$var wire 1 >" i11 [16] $end
$var wire 1 ?" i11 [15] $end
$var wire 1 @" i11 [14] $end
$var wire 1 A" i11 [13] $end
$var wire 1 B" i11 [12] $end
$var wire 1 C" i11 [11] $end
$var wire 1 D" i11 [10] $end
$var wire 1 E" i11 [9] $end
$var wire 1 F" i11 [8] $end
$var wire 1 G" i11 [7] $end
$var wire 1 H" i11 [6] $end
$var wire 1 I" i11 [5] $end
$var wire 1 J" i11 [4] $end
$var wire 1 K" i11 [3] $end
$var wire 1 L" i11 [2] $end
$var wire 1 M" i11 [1] $end
$var wire 1 N" i11 [0] $end
$var wire 1 { s [3] $end
$var wire 1 | s [2] $end
$var wire 1 } s [1] $end
$var wire 1 ~ s [0] $end
$var reg 32 (& y [31:0] $end
$upscope $end
$upscope $end

$scope module Instrmem_instance $end
$var wire 1 )& addr_i [31] $end
$var wire 1 *& addr_i [30] $end
$var wire 1 +& addr_i [29] $end
$var wire 1 ,& addr_i [28] $end
$var wire 1 -& addr_i [27] $end
$var wire 1 .& addr_i [26] $end
$var wire 1 /& addr_i [25] $end
$var wire 1 0& addr_i [24] $end
$var wire 1 1& addr_i [23] $end
$var wire 1 2& addr_i [22] $end
$var wire 1 3& addr_i [21] $end
$var wire 1 4& addr_i [20] $end
$var wire 1 5& addr_i [19] $end
$var wire 1 6& addr_i [18] $end
$var wire 1 7& addr_i [17] $end
$var wire 1 8& addr_i [16] $end
$var wire 1 9& addr_i [15] $end
$var wire 1 :& addr_i [14] $end
$var wire 1 ;& addr_i [13] $end
$var wire 1 <& addr_i [12] $end
$var wire 1 =& addr_i [11] $end
$var wire 1 >& addr_i [10] $end
$var wire 1 ?& addr_i [9] $end
$var wire 1 @& addr_i [8] $end
$var wire 1 A& addr_i [7] $end
$var wire 1 B& addr_i [6] $end
$var wire 1 C& addr_i [5] $end
$var wire 1 D& addr_i [4] $end
$var wire 1 E& addr_i [3] $end
$var wire 1 F& addr_i [2] $end
$var wire 1 G& addr_i [1] $end
$var wire 1 H& addr_i [0] $end
$var reg 32 I& instruction_o [31:0] $end
$upscope $end

$scope module data_mem_instance $end
$var wire 1 $ clk $end
$var wire 1 % rst $end
$var wire 1 t mem_wr $end
$var wire 1 J& addr [31] $end
$var wire 1 K& addr [30] $end
$var wire 1 L& addr [29] $end
$var wire 1 M& addr [28] $end
$var wire 1 N& addr [27] $end
$var wire 1 O& addr [26] $end
$var wire 1 P& addr [25] $end
$var wire 1 Q& addr [24] $end
$var wire 1 R& addr [23] $end
$var wire 1 S& addr [22] $end
$var wire 1 T& addr [21] $end
$var wire 1 U& addr [20] $end
$var wire 1 V& addr [19] $end
$var wire 1 W& addr [18] $end
$var wire 1 X& addr [17] $end
$var wire 1 Y& addr [16] $end
$var wire 1 Z& addr [15] $end
$var wire 1 [& addr [14] $end
$var wire 1 \& addr [13] $end
$var wire 1 ]& addr [12] $end
$var wire 1 ^& addr [11] $end
$var wire 1 _& addr [10] $end
$var wire 1 `& addr [9] $end
$var wire 1 a& addr [8] $end
$var wire 1 b& addr [7] $end
$var wire 1 c& addr [6] $end
$var wire 1 d& addr [5] $end
$var wire 1 e& addr [4] $end
$var wire 1 f& addr [3] $end
$var wire 1 g& addr [2] $end
$var wire 1 h& addr [1] $end
$var wire 1 i& addr [0] $end
$var wire 1 j& data_wr [31] $end
$var wire 1 k& data_wr [30] $end
$var wire 1 l& data_wr [29] $end
$var wire 1 m& data_wr [28] $end
$var wire 1 n& data_wr [27] $end
$var wire 1 o& data_wr [26] $end
$var wire 1 p& data_wr [25] $end
$var wire 1 q& data_wr [24] $end
$var wire 1 r& data_wr [23] $end
$var wire 1 s& data_wr [22] $end
$var wire 1 t& data_wr [21] $end
$var wire 1 u& data_wr [20] $end
$var wire 1 v& data_wr [19] $end
$var wire 1 w& data_wr [18] $end
$var wire 1 x& data_wr [17] $end
$var wire 1 y& data_wr [16] $end
$var wire 1 z& data_wr [15] $end
$var wire 1 {& data_wr [14] $end
$var wire 1 |& data_wr [13] $end
$var wire 1 }& data_wr [12] $end
$var wire 1 ~& data_wr [11] $end
$var wire 1 !' data_wr [10] $end
$var wire 1 "' data_wr [9] $end
$var wire 1 #' data_wr [8] $end
$var wire 1 $' data_wr [7] $end
$var wire 1 %' data_wr [6] $end
$var wire 1 &' data_wr [5] $end
$var wire 1 '' data_wr [4] $end
$var wire 1 (' data_wr [3] $end
$var wire 1 )' data_wr [2] $end
$var wire 1 *' data_wr [1] $end
$var wire 1 +' data_wr [0] $end
$var wire 1 ,' func3 [2] $end
$var wire 1 -' func3 [1] $end
$var wire 1 .' func3 [0] $end
$var wire 1 /' mem_col [1] $end
$var wire 1 0' mem_col [0] $end
$var reg 32 1' mem_data [31:0] $end
$var reg 4 2' mask [3:0] $end
$var reg 3 3' load_ctrl [2:0] $end
$var reg 32 4' data_wr_gen [31:0] $end
$var reg 32 5' mem_data_read [31:0] $end

$scope module LS_controller_instance $end
$var parameter 3 6' b $end
$var parameter 3 7' h $end
$var parameter 3 8' w $end
$var parameter 3 9' bu $end
$var parameter 3 :' hu $end
$var wire 1 ,' func3 [2] $end
$var wire 1 -' func3 [1] $end
$var wire 1 .' func3 [0] $end
$var wire 1 /' address [1] $end
$var wire 1 0' address [0] $end
$var wire 1 j& rdata2 [31] $end
$var wire 1 k& rdata2 [30] $end
$var wire 1 l& rdata2 [29] $end
$var wire 1 m& rdata2 [28] $end
$var wire 1 n& rdata2 [27] $end
$var wire 1 o& rdata2 [26] $end
$var wire 1 p& rdata2 [25] $end
$var wire 1 q& rdata2 [24] $end
$var wire 1 r& rdata2 [23] $end
$var wire 1 s& rdata2 [22] $end
$var wire 1 t& rdata2 [21] $end
$var wire 1 u& rdata2 [20] $end
$var wire 1 v& rdata2 [19] $end
$var wire 1 w& rdata2 [18] $end
$var wire 1 x& rdata2 [17] $end
$var wire 1 y& rdata2 [16] $end
$var wire 1 z& rdata2 [15] $end
$var wire 1 {& rdata2 [14] $end
$var wire 1 |& rdata2 [13] $end
$var wire 1 }& rdata2 [12] $end
$var wire 1 ~& rdata2 [11] $end
$var wire 1 !' rdata2 [10] $end
$var wire 1 "' rdata2 [9] $end
$var wire 1 #' rdata2 [8] $end
$var wire 1 $' rdata2 [7] $end
$var wire 1 %' rdata2 [6] $end
$var wire 1 &' rdata2 [5] $end
$var wire 1 '' rdata2 [4] $end
$var wire 1 (' rdata2 [3] $end
$var wire 1 )' rdata2 [2] $end
$var wire 1 *' rdata2 [1] $end
$var wire 1 +' rdata2 [0] $end
$var reg 32 ;' wdata_mem [31:0] $end
$var reg 3 <' load_ctrl [2:0] $end
$var reg 4 =' mask [3:0] $end
$upscope $end
$upscope $end

$scope module Branch_block_instance $end
$var wire 1 >' op_a [31] $end
$var wire 1 ?' op_a [30] $end
$var wire 1 @' op_a [29] $end
$var wire 1 A' op_a [28] $end
$var wire 1 B' op_a [27] $end
$var wire 1 C' op_a [26] $end
$var wire 1 D' op_a [25] $end
$var wire 1 E' op_a [24] $end
$var wire 1 F' op_a [23] $end
$var wire 1 G' op_a [22] $end
$var wire 1 H' op_a [21] $end
$var wire 1 I' op_a [20] $end
$var wire 1 J' op_a [19] $end
$var wire 1 K' op_a [18] $end
$var wire 1 L' op_a [17] $end
$var wire 1 M' op_a [16] $end
$var wire 1 N' op_a [15] $end
$var wire 1 O' op_a [14] $end
$var wire 1 P' op_a [13] $end
$var wire 1 Q' op_a [12] $end
$var wire 1 R' op_a [11] $end
$var wire 1 S' op_a [10] $end
$var wire 1 T' op_a [9] $end
$var wire 1 U' op_a [8] $end
$var wire 1 V' op_a [7] $end
$var wire 1 W' op_a [6] $end
$var wire 1 X' op_a [5] $end
$var wire 1 Y' op_a [4] $end
$var wire 1 Z' op_a [3] $end
$var wire 1 [' op_a [2] $end
$var wire 1 \' op_a [1] $end
$var wire 1 ]' op_a [0] $end
$var wire 1 ^' op_b [31] $end
$var wire 1 _' op_b [30] $end
$var wire 1 `' op_b [29] $end
$var wire 1 a' op_b [28] $end
$var wire 1 b' op_b [27] $end
$var wire 1 c' op_b [26] $end
$var wire 1 d' op_b [25] $end
$var wire 1 e' op_b [24] $end
$var wire 1 f' op_b [23] $end
$var wire 1 g' op_b [22] $end
$var wire 1 h' op_b [21] $end
$var wire 1 i' op_b [20] $end
$var wire 1 j' op_b [19] $end
$var wire 1 k' op_b [18] $end
$var wire 1 l' op_b [17] $end
$var wire 1 m' op_b [16] $end
$var wire 1 n' op_b [15] $end
$var wire 1 o' op_b [14] $end
$var wire 1 p' op_b [13] $end
$var wire 1 q' op_b [12] $end
$var wire 1 r' op_b [11] $end
$var wire 1 s' op_b [10] $end
$var wire 1 t' op_b [9] $end
$var wire 1 u' op_b [8] $end
$var wire 1 v' op_b [7] $end
$var wire 1 w' op_b [6] $end
$var wire 1 x' op_b [5] $end
$var wire 1 y' op_b [4] $end
$var wire 1 z' op_b [3] $end
$var wire 1 {' op_b [2] $end
$var wire 1 |' op_b [1] $end
$var wire 1 }' op_b [0] $end
$var wire 1 ~' func3 [2] $end
$var wire 1 !( func3 [1] $end
$var wire 1 "( func3 [0] $end
$var reg 1 #( branch_taken $end
$var reg 32 $( branch_sub [31:0] $end
$var reg 1 %( overflow $end
$var reg 1 &( not_zero $end
$var reg 1 '( neg $end
$var reg 1 (( carry $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end

$scope begin std $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
1"
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bx !!
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bx $!
bx %!
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b1100 4
b100 5
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b1000 7
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b11001 :
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b100 i
b0 j
b11000 k
b1000 l
b11011 m
b11001 n
b1101 o
b101 p
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