RunnerGame/webtalk_pn.xml at master · RahimACM/RunnerGame · GitHub

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<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Tue May 15 23:01:36 2018">
<section name="Project Information" visible="false">
<property name="ProjectID" value="ADBE9BD0733241F89F22291AD4CED9F5" type="project"/>
<property name="ProjectIteration" value="45" type="project"/>
<property name="ProjectFile" value="D:/ESI/2CS/S2/SEMB/TD/Mini projet/RunnerGameProjectV2 development optim/RunnerGameProjectV2.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2014-11-22T15:12:54" type="project"/>
</section>
<section name="Project Statistics" visible="true">
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_MapPowerReduction_spartan6" value="On" type="process"/>
<property name="PROP_ProjectDescription" value="Editting the "working" version of our RunnerGameProject to try and improve obstacle generation rate and randomization." type="process"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
<property name="PROP_UseSmartGuide" value="false" type="design"/>
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2014-11-22T15:12:54" type="design"/>
<property name="PROP_intWbtProjectID" value="ADBE9BD0733241F89F22291AD4CED9F5" type="design"/>
<property name="PROP_intWbtProjectIteration" value="45" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_xilxBitgStart_Clk" value="JTAG Clock" type="process"/>
<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/>
<property name="PROP_xstPowerOptimization_spartan6" value="true" type="process"/>
<property name="PROPEXT_parPowerReduction_spartan6" value="true" type="process"/>
<property name="PROP_AutoTop" value="false" type="design"/>
<property name="PROP_DevFamily" value="Spartan6" type="design"/>
<property name="PROP_DevDevice" value="xc6slx16" type="design"/>
<property name="PROP_DevFamilyPMName" value="spartan6" type="design"/>
<property name="PROP_DevPackage" value="csg324" type="design"/>
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
<property name="PROP_DevSpeed" value="-3" type="design"/>
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
<property name="FILE_UCF" value="1" type="source"/>
<property name="FILE_USERDOC" value="1" type="source"/>
<property name="FILE_VHDL" value="9" type="source"/>
</section>
</application>
</document>