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game_logic.stx
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63 lines (48 loc) · 2.08 KB
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Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to C:/Xilinx Projects F2014/RunnerGameProject/xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
--> Parameter xsthdpdir set to C:/Xilinx Projects F2014/RunnerGameProject/xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
--> Reading design: game_logic.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* HDL Parsing *
=========================================================================
Parsing VHDL file "C:\Xilinx Projects F2014\RunnerGameProject\SR.vhd" into library work
Parsing entity <SR>.
Parsing architecture <Behavioral> of entity <sr>.
Parsing VHDL file "C:\Xilinx Projects F2014\RunnerGameProject\LFSR.vhd" into library work
Parsing entity <LFSR>.
Parsing architecture <Behavioral> of entity <lfsr>.
Parsing VHDL file "C:\Xilinx Projects F2014\RunnerGameProject\runner_toplevel_wiring.vhd" into library work
Parsing entity <game_logic>.
Parsing architecture <Behavioral> of entity <game_logic>.
Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.25 secs
-->
Total memory usage is 182100 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)