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Updatd for multi-dimensions
1 parent 7a185ef commit 2de9088

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2 files changed

+4
-5
lines changed

2 files changed

+4
-5
lines changed

pyverilog/vparser/ast.py

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -159,10 +159,11 @@ def children(self):
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class Port(Node):
160160
attr_names = ('name', 'type',)
161161

162-
def __init__(self, name, width, type, lineno=0):
162+
def __init__(self, name, width, dimensions, type, lineno=0):
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self.lineno = lineno
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self.name = name
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self.width = width
166+
self.dimensions = dimensions
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self.type = type
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168169
def children(self):

pyverilog/vparser/parser.py

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -261,15 +261,13 @@ def p_portlist_empty(self, p):
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262262
def p_ports(self, p):
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'ports : ports COMMA portname'
264-
wid = None
265-
port = Port(name=p[3], width=wid, type=None, lineno=p.lineno(1))
264+
port = Port(name=p[3], width=None, dimensions=None, type=None, lineno=p.lineno(1))
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p[0] = p[1] + (port,)
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p.set_lineno(0, p.lineno(1))
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def p_ports_one(self, p):
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'ports : portname'
271-
wid = None
272-
port = Port(name=p[1], width=wid, type=None, lineno=p.lineno(1))
270+
port = Port(name=p[1], width=None, dimensions=None, type=None, lineno=p.lineno(1))
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p[0] = (port,)
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p.set_lineno(0, p.lineno(1))
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