fpga: fixed a new pylint complain about to use f-strings

rodrigomelo9 · rodrigomelo9 · commit 2d1f06351580 · 2021-11-25T22:20:10.000-03:00
diff --git a/fpga/tool/__init__.py b/fpga/tool/__init__.py
@@ -1,6 +1,6 @@
 #
 # Copyright (C) 2019-2020 INTI
-# Copyright (C) 2019-2020 Rodrigo A. Melo
+# Copyright (C) 2019-2021 Rodrigo A. Melo
 #
 # This program is free software: you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -37,10 +37,8 @@
 def check_value(value, values):
     """Check if VALUE is included in VALUES."""
     if value not in values:
-        raise ValueError(
-            '{} is not a valid value [{}]'
-            .format(value, ", ".join(values))
-        )
+        joined_values = ", ".join(values)
+        raise ValueError(f'{value} is not a valid value [{joined_values}]')
 
 
 def run(command, capture):
@@ -163,27 +161,27 @@ def _create_gen_script(self, tasks):
         # Paths and files
         files = []
         if self.presynth:
-            files.append('    fpga_file {}.edif'.format(self.project))
+            files.append(f'    fpga_file {self.project}.edif')
         else:
             for path in self.paths:
-                files.append('    fpga_include {}'.format(tcl_path(path)))
+                files.append(f'    fpga_include {tcl_path(path)}')
             for file in self.files['verilog']:
-                files.append('    fpga_file {}'.format(tcl_path(file[0])))
+                files.append(f'    fpga_file {tcl_path(file[0])}')
             for file in self.files['vhdl']:
                 if file[1] is None:
-                    files.append('    fpga_file {}'.format(tcl_path(file[0])))
+                    files.append(f'    fpga_file {tcl_path(file[0])}')
                 else:
-                    files.append('    fpga_file {} {}'.format(
-                        tcl_path(file[0]), file[1]
-                    ))
+                    files.append(
+                        f'    fpga_file {tcl_path(file[0])} {file[1]}'
+                    )
         for file in self.files['design']:
-            files.append('    fpga_design {}'.format(tcl_path(file[0])))
+            files.append(f'    fpga_design {tcl_path(file[0])}')
         for file in self.files['constraint']:
-            files.append('    fpga_file {}'.format(tcl_path(file[0])))
+            files.append(f'    fpga_file {tcl_path(file[0])}')
         # Parameters
         params = []
         for param in self.params:
-            params.append('{{ {} {} }}'.format(param[0], param[1]))
+            params.append(f'{{ {param[0]} {param[1]} }}')
         # Script creation
         template = os.path.join(os.path.dirname(__file__), 'template.tcl')
         with open(template, 'r') as file:
@@ -206,7 +204,7 @@ def _create_gen_script(self, tasks):
         tcl = tcl.replace('#POSTSYN_CMDS#', '\n'.join(self.cmds['postsyn']))
         tcl = tcl.replace('#POSTIMP_CMDS#', '\n'.join(self.cmds['postimp']))
         tcl = tcl.replace('#POSTBIT_CMDS#', '\n'.join(self.cmds['postbit']))
-        with open('%s.tcl' % self._TOOL, 'w') as file:
+        with open(f'{self._TOOL}.tcl', 'w') as file:
             file.write(tcl)
 
     def generate(self, to_task, from_task, capture):
@@ -217,15 +215,13 @@ def generate(self, to_task, from_task, capture):
         from_index = TASKS.index(from_task)
         if from_index > to_index:
             raise ValueError(
-                'initial task "{}" cannot be later than the last task "{}"'
-                .format(from_task, to_task)
+                f'initial task "{from_task}" cannot be later than the ' +
+                f'last task "{to_task}"'
             )
         tasks = " ".join(TASKS[from_index:to_index+1])
         self._create_gen_script(tasks)
         if not which(self._GEN_PROGRAM):
-            raise RuntimeError(
-                'program "{}" not found'.format(self._GEN_PROGRAM)
-            )
+            raise RuntimeError(f'program "{self._GEN_PROGRAM}" not found')
         return run(self._GEN_COMMAND, capture)
 
     def set_bitstream(self, path):
@@ -235,9 +231,7 @@ def set_bitstream(self, path):
     def transfer(self, devtype, position, part, width, capture):
         """Transfer a bitstream."""
         if not which(self._TRF_PROGRAM):
-            raise RuntimeError(
-                'program "{}" not found'.format(self._TRF_PROGRAM)
-            )
+            raise RuntimeError(f'program "{self._TRF_PROGRAM}" not found')
         check_value(devtype, self._DEVTYPES)
         check_value(position, range(10))
         isinstance(part, str)
@@ -247,7 +241,7 @@ def transfer(self, devtype, position, part, width, capture):
         if not self.bitstream and devtype not in ['detect', 'unlock']:
             bitstream = []
             for ext in self._BIT_EXT:
-                bitstream.extend(glob('**/*.{}'.format(ext), recursive=True))
+                bitstream.extend(glob(f'**/*.{ext}', recursive=True))
             if len(bitstream) == 0:
                 raise FileNotFoundError('bitStream not found')
             self.bitstream = bitstream[0]
diff --git a/fpga/tool/ise.py b/fpga/tool/ise.py
@@ -1,6 +1,6 @@
 #
 # Copyright (C) 2019-2020 INTI
-# Copyright (C) 2019-2020 Rodrigo A. Melo
+# Copyright (C) 2019-2021 Rodrigo A. Melo
 #
 # This program is free software: you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -132,7 +132,7 @@ def set_part(self, part):
             device, speed, package = re.findall(r'(\w+)-(\w+)-(\w+)', part)[0]
             if len(speed) > len(package):
                 speed, package = package, speed
-            part = "{}-{}-{}".format(device, speed, package)
+            part = f'{device}-{speed}-{package}'
         except IndexError:
             raise ValueError(
                 'Part must be DEVICE-SPEED-PACKAGE or DEVICE-PACKAGE-SPEED'
diff --git a/fpga/tool/libero.py b/fpga/tool/libero.py
@@ -1,6 +1,6 @@
 #
 # Copyright (C) 2019-2020 INTI
-# Copyright (C) 2019-2020 Rodrigo A. Melo
+# Copyright (C) 2019-2021 Rodrigo A. Melo
 #
 # This program is free software: you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -64,7 +64,7 @@ def set_part(self, part):
                 speed, package = package, speed
             if speed == '':
                 speed = 'STD'
-            part = "{}-{}-{}".format(device, speed, package)
+            part = f'{device}-{speed}-{package}'
         except IndexError:
             raise ValueError(
                 'Part must be DEVICE-SPEED-PACKAGE or DEVICE-PACKAGE'
diff --git a/fpga/tool/openflow.py b/fpga/tool/openflow.py
@@ -1,6 +1,6 @@
 #
 # Copyright (C) 2020 INTI
-# Copyright (C) 2020 Rodrigo A. Melo
+# Copyright (C) 2020-2021 Rodrigo A. Melo
 #
 # This program is free software: you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -60,7 +60,7 @@ def _configure(self):
         command = engine.get('command', 'docker') + ' run --rm'
         volumes = '-v ' + ('-v ').join(engine.get('volumes', ['$HOME:$HOME']))
         work = '-w ' + engine.get('work', '$PWD')
-        self.oci_engine = '{} {} {}'.format(command, volumes, work)
+        self.oci_engine = f'{command} {volumes} {work}'
         # Containers
         defaults = {
             'ghdl': 'ghdl/synth:beta',
@@ -90,7 +90,7 @@ def set_part(self, part):
                 self.part['device'] = aux[0]
                 self.part['package'] = aux[1]
             elif len(aux) == 3:
-                self.part['device'] = '{}-{}'.format(aux[0], aux[1])
+                self.part['device'] = f'{aux[0]}-{aux[1]}'
                 self.part['package'] = aux[2]
             else:
                 raise ValueError('Part must be DEVICE-PACKAGE')
@@ -103,33 +103,29 @@ def _create_gen_script(self, tasks):
         # Verilog includes
         paths = []
         for path in self.paths:
-            paths.append('verilog_defaults -add -I{}'.format(path))
+            paths.append(f'verilog_defaults -add -I{path}')
         # Files
         constraints = []
         verilogs = []
         vhdls = []
         for file in self.files['vhdl']:
             lib = ''
             if file[1] is not None:
-                lib = '--work={}'.format(file[1])
-            vhdls.append('{} -a $FLAGS {} {}'.format(
-                self.tools['ghdl'], lib, file[0])
-            )
+                lib = f'--work={file[1]}'
+            vhdls.append(f'{self.tools["ghdl"]} -a $FLAGS {lib} {file[0]}')
         for file in self.files['verilog']:
             if file[0].endswith('.sv'):
-                verilogs.append('read_verilog -sv -defer {}'.format(file[0]))
+                verilogs.append(f'read_verilog -sv -defer {file[0]}')
             else:
-                verilogs.append('read_verilog -defer {}'.format(file[0]))
+                verilogs.append(f'read_verilog -defer {file[0]}')
         for file in self.files['constraint']:
             constraints.append(file[0])
         if len(vhdls) > 0:
-            verilogs = ['ghdl $FLAGS {}'.format(self.top)]
+            verilogs = [f'ghdl $FLAGS {self.top}']
         # Parameters
         params = []
         for param in self.params:
-            params.append('chparam -set {} {} {}'.format(
-                param[0], param[1], self.top
-            ))
+            params.append(f'chparam -set {param[0]} {param[1]} {self.top}')
         # Script creation
         template = os.path.join(os.path.dirname(__file__), 'template.sh')
         with open(template, 'r') as file:
@@ -165,7 +161,7 @@ def _create_gen_script(self, tasks):
             tool_nextpnr_ecp5=self.tools['nextpnr-ecp5'],
             tool_ecppack=self.tools['ecppack']
         )
-        with open('%s.sh' % self._TOOL, 'w') as file:
+        with open(f'{self._TOOL}.sh', 'w') as file:
             file.write(text)
 
     def generate(self, to_task, from_task, capture):
