[PyTorchSim] Fix dram_stride update logic

YWHyuk · YWHyuk · commit 32f66c43ba50 · 2025-07-17T12:06:15.000Z
diff --git a/mlir/test/lib/Analysis/TestLoopPadding.cpp b/mlir/test/lib/Analysis/TestLoopPadding.cpp
@@ -608,7 +608,7 @@ mlir::AffineExpr TestLoopPadding::updateAffineExprWithBounds(mlir::AffineExpr ex
     }
 
     int64_t value = intAttr.getInt();
-    if (value > targetCoefficient || (value == targetCoefficient && i < updated_position_index))
+    if (value > targetCoefficient)
       dram_stride[i] = mlir::IntegerAttr::get(intAttr.getType(), (value / upperBound) * paddedUpperBound);
   }
 

Original file line number	Diff line number	Diff line change
`@@ -608,7 +608,7 @@ mlir::AffineExpr TestLoopPadding::updateAffineExprWithBounds(mlir::AffineExpr ex`
`608`	`608`	`}`
`609`	`609`
`610`	`610`	`int64_t value = intAttr.getInt();`
`611`		`- if (value > targetCoefficient \|\| (value == targetCoefficient && i < updated_position_index))`
	`611`	`+ if (value > targetCoefficient)`
`612`	`612`	`dram_stride[i] = mlir::IntegerAttr::get(intAttr.getType(), (value / upperBound) * paddedUpperBound);`
`613`	`613`	`}`
`614`	`614`