[TOGSim] Fix incorrect icnt frequency

YWHyuk · YWHyuk · commit 77ac432721b2 · 2025-11-30T22:27:44.000Z
diff --git a/README.md b/README.md
@@ -361,9 +361,10 @@ export TORCHSIM_USE_TIMING_POOLING=0 # use lightweight pooling for timing
   "l2d_type" : "datacache",
   "l2d_config" : "S:64:128:512,32,L:B:m:W:L,A:192:4,32:0,32",
 
-  "icnt_type" : "simple",            // Interconnect type (ex. booksim, simple)
-  "icnt_latency" : 7,                // Interconnect latency (cycle)
-  "icnt_freq" : 28000,               // Interconnect frequency (MHz)
+  "icnt_type" : "simple",              // Interconnect type (ex. booksim, simple)
+  "icnt_latency" : 7,                  // Interconnect latency (cycle)
+  "icnt_freq_mhz" : 940,               // Interconnect frequency (MHz)
+  "icnt_injection_ports_per_core" : 16 // Interconnect injection ports per core
   "icnt_config_path" : "../configs/booksim2_configs/fly_c4_m32.icnt", // Booksim2 config file path
 
   "precision" : 4,                   // Element's precision in tensor (Byte)
diff --git a/TOGSim/configs/heterogeneous_c2_simple_noc.json b/TOGSim/configs/heterogeneous_c2_simple_noc.json
@@ -18,7 +18,8 @@
 
   "icnt_type" : "simple",
   "icnt_latency" : 7,
-  "icnt_freq_mhz" : 15000,
+  "icnt_freq_mhz" : 940,
+  "icnt_injection_ports_per_core" : 16,
 
   "num_partition" : 2,
   "partition": {
diff --git a/TOGSim/configs/stonne_big_c1_simple_noc.json b/TOGSim/configs/stonne_big_c1_simple_noc.json
@@ -17,10 +17,6 @@
 
   "icnt_type" : "simple",
   "icnt_latency" : 7,
-  "icnt_freq_mhz" : 15000,
-
-  "num_partition" : 1,
-  "partition": {
-    "core_0":0
-  }
+  "icnt_freq_mhz" : 940,
+  "icnt_injection_ports_per_core" : 16
 }
diff --git a/TOGSim/configs/stonne_single_c1_simple_noc.json b/TOGSim/configs/stonne_single_c1_simple_noc.json
@@ -17,10 +17,6 @@
 
   "icnt_type" : "simple",
   "icnt_latency" : 7,
-  "icnt_freq_mhz" : 7000,
-
-  "num_partition" : 1,
-  "partition": {
-    "core_0":0
-  }
+  "icnt_freq_mhz" : 700,
+  "icnt_injection_ports_per_core" : 8
 }
diff --git a/TOGSim/configs/stonne_validation_c1_simple_noc.json b/TOGSim/configs/stonne_validation_c1_simple_noc.json
@@ -18,10 +18,6 @@
 
   "icnt_type" : "simple",
   "icnt_latency" : 7,
-  "icnt_freq_mhz" : 7000,
-
-  "num_partition" : 1,
-  "partition": {
-    "core_0":0
-  }
+  "icnt_freq_mhz" : 1000,
+  "icnt_injection_ports_per_core" : 8
 }
diff --git a/TOGSim/configs/systolic_ws_128x128_c1_booksim_tpuv2.json b/TOGSim/configs/systolic_ws_128x128_c1_booksim_tpuv2.json
@@ -13,7 +13,7 @@
   "ramulator_config_path" : "../configs/ramulator2_configs/HBM2.yaml",
 
   "icnt_type" : "booksim2",
-  "icnt_freq_mhz" : 8000,
-  "icnt_node_per_core" : 16,
+  "icnt_freq_mhz" : 700,
+  "icnt_injection_ports_per_core" : 16,
   "booksim_config_path" : "../configs/booksim2_configs/fly_c16_m16.icnt"
 }
diff --git a/TOGSim/configs/systolic_ws_128x128_c1_simple_noc_tpuv2.json b/TOGSim/configs/systolic_ws_128x128_c1_simple_noc_tpuv2.json
@@ -13,5 +13,6 @@
 
   "icnt_type" : "simple",
   "icnt_latency" : 7,
-  "icnt_freq_mhz" : 10000
+  "icnt_freq_mhz" : 700,
+  "icnt_injection_ports_per_core" : 16
 }
diff --git a/TOGSim/configs/systolic_ws_128x128_c1_simple_noc_tpuv3.json b/TOGSim/configs/systolic_ws_128x128_c1_simple_noc_tpuv3.json
@@ -14,5 +14,6 @@
 
   "icnt_type" : "simple",
   "icnt_latency" : 7,
-  "icnt_freq_mhz" : 15000
+  "icnt_freq_mhz" : 940,
+  "icnt_injection_ports_per_core" : 16
 }
diff --git a/TOGSim/configs/systolic_ws_128x128_c1_simple_noc_tpuv3_half.json b/TOGSim/configs/systolic_ws_128x128_c1_simple_noc_tpuv3_half.json
@@ -14,5 +14,6 @@
 
   "icnt_type" : "simple",
   "icnt_latency" : 7,
-  "icnt_freq_mhz" : 15000
+  "icnt_freq_mhz" : 940,
+  "icnt_injection_ports_per_core" : 16
 }
diff --git a/TOGSim/configs/systolic_ws_128x128_c1_simple_noc_tpuv4.json b/TOGSim/configs/systolic_ws_128x128_c1_simple_noc_tpuv4.json
@@ -16,5 +16,6 @@
 
   "icnt_type" : "simple",
   "icnt_latency" : 7,
-  "icnt_freq_mhz" : 19200
+  "icnt_freq_mhz" : 1050,
+  "icnt_injection_ports_per_core" : 16
 }
diff --git a/TOGSim/configs/systolic_ws_128x128_c2_booksim_tpuv3.json b/TOGSim/configs/systolic_ws_128x128_c2_booksim_tpuv3.json
@@ -13,7 +13,7 @@
   "ramulator_config_path" : "../configs/ramulator2_configs/HBM2_TPUv3.yaml",
 
   "icnt_type" : "booksim2",
-  "icnt_freq_mhz" : 28000,
-  "icnt_node_per_core" : 1,
+  "icnt_freq_mhz" : 940,
+  "icnt_injection_ports_per_core" : 16,
   "booksim_config_path" : "../configs/booksim2_configs/fly_c2_m32.icnt"
 }
diff --git a/TOGSim/configs/systolic_ws_128x128_c2_booksim_tpuv3_bw_quarter.json b/TOGSim/configs/systolic_ws_128x128_c2_booksim_tpuv3_bw_quarter.json
@@ -10,15 +10,14 @@
   "dram_channels": 8,
   "dram_req_size": 32,
   "dram_latency" : 10,
-  "dram_size" : 32,
   "dram_nbl" : 2,
   "dram_print_interval": 10000,
   "dram_config_path" : "../configs/ramulator2_configs/HBM2_TPUv3.yaml",
  
   "icnt_type" : "booksim2",
   "icnt_latency" : 1,
-  "icnt_freq" : 2000,
-  "icnt_node_per_core" : 16,
+  "icnt_freq" : 940,
+  "icnt_injection_ports_per_core" : 16,
   "icnt_config_path" : "../configs/booksim2_configs/fly_c32_m8.icnt",
  
   "precision" : 4,
diff --git a/TOGSim/configs/systolic_ws_128x128_c2_chiplet_tpuv3.json b/TOGSim/configs/systolic_ws_128x128_c2_chiplet_tpuv3.json
@@ -15,7 +15,7 @@
 
   "icnt_type" : "booksim2",
   "icnt_freq_mhz" : 1000,
-  "icnt_node_per_core" : 16,
+  "icnt_injection_ports_per_core" : 16,
   "booksim_config_path" : "../configs/booksim2_configs/chiplet_32_32_2.icnt",
   "icnt_stats_print_period_cycles" : 10000
 }
diff --git a/TOGSim/configs/systolic_ws_128x128_c2_chiplet_tpuv3_xnuma.json b/TOGSim/configs/systolic_ws_128x128_c2_chiplet_tpuv3_xnuma.json
@@ -15,6 +15,6 @@
 
   "icnt_type" : "booksim2",
   "icnt_freq_mhz" : 1000,
-  "icnt_node_per_core" : 16,
+  "icnt_injection_ports_per_core" : 16,
   "booksim_config_path" : "../configs/booksim2_configs/chiplet_32_32_2.icnt"
 }
diff --git a/TOGSim/configs/systolic_ws_128x128_c2_simple_noc_tpuv2.json b/TOGSim/configs/systolic_ws_128x128_c2_simple_noc_tpuv2.json
@@ -13,5 +13,6 @@
 
   "icnt_type" : "simple",
   "icnt_latency" : 7,
-  "icnt_freq_mhz" : 20000
+  "icnt_freq_mhz" : 700,
+  "icnt_injection_ports_per_core" : 16
 }
diff --git a/TOGSim/configs/systolic_ws_128x128_c2_simple_noc_tpuv3.json b/TOGSim/configs/systolic_ws_128x128_c2_simple_noc_tpuv3.json
@@ -14,5 +14,6 @@
 
   "icnt_type" : "simple",
   "icnt_latency" : 7,
-  "icnt_freq_mhz" : 28000
+  "icnt_freq_mhz" : 940,
+  "icnt_injection_ports_per_core" : 16
 }
diff --git a/TOGSim/configs/systolic_ws_128x128_c2_simple_noc_tpuv3_partition.json b/TOGSim/configs/systolic_ws_128x128_c2_simple_noc_tpuv3_partition.json
@@ -14,7 +14,8 @@
 
   "icnt_type" : "simple",
   "icnt_latency" : 7,
-  "icnt_freq_mhz" : 28000,
+  "icnt_freq_mhz" : 940,
+  "icnt_injection_ports_per_core" : 16,
 
   "num_partition" : 2,
   "partition": {
diff --git a/TOGSim/configs/systolic_ws_128x128_c2_simple_noc_tpuv4.json b/TOGSim/configs/systolic_ws_128x128_c2_simple_noc_tpuv4.json
@@ -16,6 +16,6 @@
 
   "icnt_type" : "simple",
   "icnt_latency" : 7,
-  "icnt_freq_mhz" : 48000,
-  "icnt_node_per_core" : 1
+  "icnt_freq_mhz" : 1050,
+  "icnt_injection_ports_per_core" : 16
 }
diff --git a/TOGSim/configs/systolic_ws_8x8_c1_24G_simple_noc.json b/TOGSim/configs/systolic_ws_8x8_c1_24G_simple_noc.json
@@ -7,12 +7,11 @@
   "dram_freq_mhz" :800,
   "dram_channels": 2,
   "dram_req_size_byte": 64,
-  "dram_size" : 16,
   "dram_num_burst_length" : 4,
   "dram_stats_print_period_cycles": 100000,
   "ramulator_config_path" : "../configs/ramulator2_configs/DDR4.yaml",
 
   "icnt_type" : "simple",
   "icnt_latency" : 1,
-  "icnt_freq_mhz" : 8000
+  "icnt_freq_mhz" : 1000
 }
diff --git a/TOGSim/configs/systolic_ws_8x8_c1_48G_simple_noc.json b/TOGSim/configs/systolic_ws_8x8_c1_48G_simple_noc.json
@@ -7,12 +7,11 @@
   "dram_freq_mhz" :800,
   "dram_channels": 4,
   "dram_req_size_byte": 64,
-  "dram_size" : 16,
   "dram_num_burst_length" : 4,
   "dram_stats_print_period_cycles": 100000,
   "ramulator_config_path" : "../configs/ramulator2_configs/DDR4.yaml",
 
   "icnt_type" : "simple",
   "icnt_latency" : 1,
-  "icnt_freq_mhz" : 8000
+  "icnt_freq_mhz" : 1000
 }
diff --git a/TOGSim/configs/systolic_ws_8x8_c1_booksim.json b/TOGSim/configs/systolic_ws_8x8_c1_booksim.json
@@ -7,12 +7,11 @@
   "dram_freq_mhz" :800,
   "dram_channels": 1,
   "dram_req_size_byte": 64,
-  "dram_size" : 16,
   "dram_num_burst_length" : 4,
   "dram_stats_print_period_cycless": 100000,
   "ramulator_config_path" : "../configs/ramulator2_configs/DDR4.yaml",
 
   "icnt_type" : "booksim2",
   "icnt_latency" : 1,
-  "icnt_freq_mhz" : 8000
+  "icnt_freq_mhz" : 1000
 }
diff --git a/TOGSim/configs/systolic_ws_8x8_c1_simple_noc.json b/TOGSim/configs/systolic_ws_8x8_c1_simple_noc.json
@@ -7,13 +7,11 @@
   "dram_freq_mhz" :800,
   "dram_channels": 1,
   "dram_req_size_byte": 64,
-  
-  "dram_size" : 16,
   "dram_num_burst_length" : 4,
   "dram_stats_print_period_cycles": 100000,
   "ramulator_config_path" : "../configs/ramulator2_configs/DDR4.yaml",
  
   "icnt_type" : "simple",
   "icnt_latency" : 1,
-  "icnt_freq_mhz" : 8000
+  "icnt_freq_mhz" : 1000
 }
diff --git a/TOGSim/configs/systolic_ws_8x8_c2_12G_simple_noc.json b/TOGSim/configs/systolic_ws_8x8_c2_12G_simple_noc.json
@@ -8,12 +8,11 @@
   "dram_freq_mhz" :800,
   "dram_channels": 1,
   "dram_req_size_byte": 64,
-  "dram_size" : 16,
   "dram_num_burst_length" : 4,
   "dram_stats_print_period_cycless": 100000,
   "ramulator_config_path" : "../configs/ramulator2_configs/DDR4.yaml",
 
   "icnt_type" : "simple",
   "icnt_latency" : 1,
-  "icnt_freq_mhz" : 8000
+  "icnt_freq_mhz" : 1000
 }
diff --git a/TOGSim/configs/systolic_ws_8x8_c2_24G_simple_noc.json b/TOGSim/configs/systolic_ws_8x8_c2_24G_simple_noc.json
@@ -13,5 +13,5 @@
 
   "icnt_type" : "simple",
   "icnt_latency" : 1,
-  "icnt_freq_mhz" : 8000
+  "icnt_freq_mhz" : 1000
 }
diff --git a/TOGSim/configs/systolic_ws_8x8_c2_48G_simple_noc.json b/TOGSim/configs/systolic_ws_8x8_c2_48G_simple_noc.json
@@ -13,5 +13,5 @@
 
   "icnt_type" : "simple",
   "icnt_latency" : 1,
-  "icnt_freq_mhz" : 8000
+  "icnt_freq_mhz" : 1000
 }
diff --git a/TOGSim/include/SimulationConfig.h b/TOGSim/include/SimulationConfig.h
@@ -42,9 +42,9 @@ struct SimulationConfig {
 
   /* ICNT config */
   IcntType icnt_type;
-  uint32_t icnt_node_per_core = 1;
+  uint32_t icnt_injection_ports_per_core = 1;
   std::string icnt_config_path;
-  uint32_t icnt_freq;
+  uint32_t icnt_freq_mhz;
   uint32_t icnt_latency;
   uint32_t icnt_stats_print_period_cycles=0;
 
diff --git a/TOGSim/src/Common.cc b/TOGSim/src/Common.cc
@@ -103,15 +103,15 @@ SimulationConfig initialize_config(json config) {
   else
     throw std::runtime_error(fmt::format("Not implemented icnt type {} ",
                                          (std::string)config["icnt_type"]));
-  parsed_config.icnt_freq = config["icnt_freq_mhz"];
+  parsed_config.icnt_freq_mhz = config["icnt_freq_mhz"];
   if (config.contains("icnt_latency"))
     parsed_config.icnt_latency = config["icnt_latency"];
   if (config.contains("booksim_config_path"))
     parsed_config.icnt_config_path = config["booksim_config_path"];
-  if (config.contains("icnt_stats_print_interval_cycle"))
-    parsed_config.icnt_stats_print_period_cycles = config["icnt_stats_print_interval_cycle"];
-  if (config.contains("icnt_node_per_core"))
-    parsed_config.icnt_node_per_core = config["icnt_node_per_core"];
+  if (config.contains("icnt_stats_print_period_cycles"))
+    parsed_config.icnt_stats_print_period_cycles = config["icnt_stats_print_period_cycles"];
+  if (config.contains("icnt_injection_ports_per_core"))
+    parsed_config.icnt_injection_ports_per_core = config["icnt_injection_ports_per_core"];
 
   if (config.contains("scheduler"))
     parsed_config.scheduler_type = config["scheduler"];
diff --git a/TOGSim/src/Interconnect.cc b/TOGSim/src/Interconnect.cc
@@ -4,7 +4,7 @@ SimpleInterconnect::SimpleInterconnect(SimulationConfig config)
   :  _latency(config.icnt_latency) {
   _cycles = 0;
   _config = config;
-  _n_nodes = config.num_cores * _config.icnt_node_per_core + config.dram_channels;
+  _n_nodes = config.num_cores * _config.icnt_injection_ports_per_core + config.dram_channels;
   _in_buffers.resize(_n_nodes);
   _out_buffers.resize(_n_nodes);
   _busy_node.resize(_n_nodes);
@@ -76,7 +76,7 @@ void SimpleInterconnect::pop(uint32_t nid) {
 
 Booksim2Interconnect::Booksim2Interconnect(SimulationConfig config) {
   _config = config;
-  _n_nodes = config.num_cores * _config.icnt_node_per_core + config.dram_channels;
+  _n_nodes = config.num_cores * _config.icnt_injection_ports_per_core + config.dram_channels;
   spdlog::info("Initialize Booksim2");
   char* onnxim_path_env = std::getenv("TORCHSIM_DIR");
   std::string onnxim_path = onnxim_path_env != NULL?
diff --git a/TOGSim/src/Simulator.cc b/TOGSim/src/Simulator.cc
@@ -4,7 +4,7 @@ Simulator::Simulator(SimulationConfig config)
     : _config(config), _core_cycles(0) {
   // Create dram object
   _core_period = 1000000 / (config.core_freq_mhz);
-  _icnt_period = 1000000 / (config.icnt_freq);
+  _icnt_period = 1000000 / (config.icnt_freq_mhz);
   _dram_period = 1000000 / (config.dram_freq_mhz);
   _core_time = 0;
   _dram_time = 0;
@@ -14,7 +14,7 @@ Simulator::Simulator(SimulationConfig config)
   _n_cores = config.num_cores;
   _n_memories = config.dram_channels;
   _memory_req_size = config.dram_req_size;
-  _noc_node_per_core = config.icnt_node_per_core;
+  _noc_node_per_core = config.icnt_injection_ports_per_core;
   char* onnxim_path_env = std::getenv("TORCHSIM_DIR");
   std::string onnxim_path = onnxim_path_env != NULL?
     std::string(onnxim_path_env) + "/TOGSim" : std::string("./");
@@ -51,7 +51,7 @@ Simulator::Simulator(SimulationConfig config)
   }
 
   // Create interconnect object
-  spdlog::info("[Config/Interconnect] Interconnect freq: {} MHz", config.icnt_freq);
+  spdlog::info("[Config/Interconnect] Interconnect freq: {} MHz", config.icnt_freq_mhz);
   if (config.icnt_type == IcntType::SIMPLE) {
     spdlog::info("[Config/Interconnect] SimpleInerconnect selected");
     _icnt = std::make_unique<SimpleInterconnect>(config);

Original file line number	Diff line number	Diff line change
`@@ -13,7 +13,7 @@`
`13`	`13`	`"ramulator_config_path" : "../configs/ramulator2_configs/HBM2.yaml",`
`14`	`14`
`15`	`15`	`"icnt_type" : "booksim2",`
`16`		`- "icnt_freq_mhz" : 8000,`
`17`		`- "icnt_node_per_core" : 16,`
	`16`	`+ "icnt_freq_mhz" : 700,`
	`17`	`+ "icnt_injection_ports_per_core" : 16,`
`18`	`18`	`"booksim_config_path" : "../configs/booksim2_configs/fly_c16_m16.icnt"`
`19`	`19`	`}`
Original file line number	Diff line number	Diff line change
`@@ -13,5 +13,6 @@`
`13`	`13`
`14`	`14`	`"icnt_type" : "simple",`
`15`	`15`	`"icnt_latency" : 7,`
`16`		`- "icnt_freq_mhz" : 10000`
	`16`	`+ "icnt_freq_mhz" : 700,`
	`17`	`+ "icnt_injection_ports_per_core" : 16`
`17`	`18`	`}`
Original file line number	Diff line number	Diff line change
`@@ -14,5 +14,6 @@`
`14`	`14`
`15`	`15`	`"icnt_type" : "simple",`
`16`	`16`	`"icnt_latency" : 7,`
`17`		`- "icnt_freq_mhz" : 15000`
	`17`	`+ "icnt_freq_mhz" : 940,`
	`18`	`+ "icnt_injection_ports_per_core" : 16`
`18`	`19`	`}`
Original file line number	Diff line number	Diff line change
`@@ -16,5 +16,6 @@`
`16`	`16`
`17`	`17`	`"icnt_type" : "simple",`
`18`	`18`	`"icnt_latency" : 7,`
`19`		`- "icnt_freq_mhz" : 19200`
	`19`	`+ "icnt_freq_mhz" : 1050,`
	`20`	`+ "icnt_injection_ports_per_core" : 16`
`20`	`21`	`}`