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[Refactor] Remove deprecated env var
1 parent 51d7028 commit 230dfcb

4 files changed

Lines changed: 3 additions & 26 deletions

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PyTorchSimFrontend/extension_codecache.py

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -27,19 +27,6 @@ def dump_metadata(args, arg_attributes, path):
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file.write(f'{arg_name}=({arg_attribute[0]}, {arg.dtype}, {arg.shape})\n')
2828
return
2929

30-
def llvm_compile_command(input, output):
31-
opt_output = f"{input[:-3]}_opt.ll"
32-
return [re.sub(r"[ \n]+", " ",
33-
f"""
34-
{extension_config.CONFIG_TORCHSIM_LLVM_PATH}/opt --load-pass-plugin={extension_config.CONFIG_TORCHSIM_CUSTOM_PASS_PATH}/libLowerGemminiPass.so -S -march=riscv64 --passes=LowerGemminiPass {input} -o {opt_output}
35-
""",
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).strip(),
37-
re.sub(r"[ \n]+", " ",
38-
f"""
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{extension_config.CONFIG_TORCHSIM_LLVM_PATH}/llc -march=riscv64 -mattr=+m,+f,+d,+a,+c,+v -O2 {opt_output} -o {output}
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""",
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).strip()]
42-
4330
def mlir_compile_command(filename, vectorlane_size, vlen=256):
4431
return [re.sub(r"[ \n]+", " ",
4532
f"""

PyTorchSimFrontend/extension_config.py

Lines changed: 1 addition & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -42,9 +42,6 @@ def __getattr__(name):
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# LLVM PATH
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if name == "CONFIG_TORCHSIM_LLVM_PATH":
4444
return os.environ.get('TORCHSIM_LLVM_PATH', default="/usr/bin")
45-
if name == "CONFIG_TORCHSIM_CUSTOM_PASS_PATH":
46-
return os.environ.get('TORCHSIM_CUSTOM_PASS_PATH',
47-
default=f"{__getattr__('CONFIG_TORCHSIM_DIR')}/GemminiLowerPass/build")
4845
if name == "CONFIG_TORCHSIM_DUMP_MLIR_IR":
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return int(os.environ.get("TORCHSIM_DUMP_MLIR_IR", default=False))
5047
if name == "CONFIG_TORCHSIM_DUMP_LLVM_IR":
@@ -64,13 +61,6 @@ def __getattr__(name):
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# GEM5 config
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if name == "CONFIG_GEM5_PATH":
6663
return os.environ.get('GEM5_PATH', default="/workspace/gem5/build/RISCV/gem5.opt")
67-
if name == "CONFIG_GEM5_SCRIPT_PATH":
68-
return os.environ.get('GEM5_SCRIPT_PATH',
69-
default=f"{__getattr__('CONFIG_TORCHSIM_DIR')}/gem5_script/script_systolic.py")
70-
71-
# For block sparse
72-
if name == "CONFIG_BLOCK_SPARSE":
73-
return int(os.environ.get('BLOCK_SPARSE', default=0))
7464

7565
# Mapping Policy
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if name == "CONFIG_MAPPING_POLICY":
@@ -105,6 +95,7 @@ def __getattr__(name):
10595
# Compiler Optimization
10696
if name == "CONFIG_COMPILER_OPTIMIZATION":
10797
return os.environ.get('TORCHSIM_COMPILER_OPTIMIZATION', default="all") # options: all, none, custom
98+
10899
# Advanced fusion options
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if name == "CONFIG_FUSION":
110101
return True if (__getattr__("CONFIG_COMPILER_OPTIMIZATION") == "all" or "fusion" in __getattr__("CONFIG_COMPILER_OPTIMIZATION")) else False

README.md

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -333,8 +333,6 @@ export TORCHSIM_VECTOR_LANE=128 # vector lane size
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export TORCHSIM_VECTOR_LANE_STRIDE=2 # vector lane stride for DMA
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export TORCHSIM_DIR=/workspace/PyTorchSim # home directory
335335

336-
export BLOCK_SPARSE=0 # If you want to use block sparse workload, turn it on
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338336
# Plan which tensor allocated in TPUv4's CMEM
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export SRAM_BUFFER_PLAN_PATH=/workspace/PyTorchSim/tpuv4/gemm_plan.py
340338

Simulator/simulator.py

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -161,7 +161,8 @@ def show_progress():
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print("")
162162

163163
dir_path = os.path.join(os.path.dirname(target_binary), "m5out")
164-
gem5_cmd = [extension_config.CONFIG_GEM5_PATH, "-r", "--stdout-file=sto.log", "-d", dir_path, extension_config.CONFIG_GEM5_SCRIPT_PATH, "-c", target_binary, "--vlane", str(vectorlane_size)]
164+
gem5_script_path = os.path.join(extension_config.CONFIG_TORCHSIM_DIR, "gem5_script/script_systolic.py")
165+
gem5_cmd = [extension_config.CONFIG_GEM5_PATH, "-r", "--stdout-file=sto.log", "-d", dir_path, gem5_script_path, "-c", target_binary, "--vlane", str(vectorlane_size)]
165166
try:
166167
# Create progress thread
167168
is_dryrun = int(os.environ.get('TOGSIM_DRYRUN', default=False)) or silent_mode

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