|
| 1 | +/dts-v1/; |
| 2 | + |
| 3 | +/ { |
| 4 | + #address-cells = <0x02>; |
| 5 | + #size-cells = <0x02>; |
| 6 | + compatible = "freechips,rocketchip-unknown-dev"; |
| 7 | + model = "xiangshan,xiangshan-kunminghu"; |
| 8 | + |
| 9 | + soc { |
| 10 | + #address-cells = <0x02>; |
| 11 | + #size-cells = <0x02>; |
| 12 | + compatible = "freechips,rocketchip-unknown-soc", "simple-bus"; |
| 13 | + ranges; |
| 14 | + |
| 15 | + clint@38000000 { |
| 16 | + compatible = "riscv,clint0"; |
| 17 | + interrupts-extended = <0x01 0x03 0x01 0x07>; |
| 18 | + reg = <0x00 0x38000000 0x00 0x10000>; |
| 19 | + reg-names = "control"; |
| 20 | + clock-frequency-mhz = <0x1f4>; |
| 21 | + }; |
| 22 | + |
| 23 | + serial@40600000 { |
| 24 | + compatible = "xilinx,uartlite", "xlnx,xps-uartlite-1.00.a"; |
| 25 | + current-speed = <0x1c200>; |
| 26 | + reg = <0x00 0x40600000 0x00 0x1000>; |
| 27 | + reg-names = "control"; |
| 28 | + }; |
| 29 | + }; |
| 30 | + |
| 31 | + chosen { |
| 32 | + bootargs = "console=hvc0 earlycon=sbi"; |
| 33 | + linux,initrd-start = <0x0 INITRAMFS_BEGIN>; |
| 34 | + linux,initrd-end = <0x0 INITRAMFS_END>; |
| 35 | + }; |
| 36 | + |
| 37 | + memory@100000000 { |
| 38 | + device_type = "memory"; |
| 39 | + reg = <0x00 0x80000000 0x00 0x08000000>; |
| 40 | + phandle = <0x02>; |
| 41 | + }; |
| 42 | + |
| 43 | + aliases { |
| 44 | + serial0 = "/soc/serial@40600000"; |
| 45 | + }; |
| 46 | + |
| 47 | + cpus { |
| 48 | + #address-cells = <0x01>; |
| 49 | + #size-cells = <0x00>; |
| 50 | + timebase-frequency = <0xf4240>; |
| 51 | + |
| 52 | + cpu@0 { |
| 53 | + clock-frequency = <0x00>; |
| 54 | + compatible = "UCAS,COOSCA1.0", "riscv"; |
| 55 | + d-cache-block-size = <0x40>; |
| 56 | + d-cache-sets = <0x40>; |
| 57 | + d-cache-size = <0x4000>; |
| 58 | + d-tlb-sets = <0x01>; |
| 59 | + d-tlb-size = <0x20>; |
| 60 | + device_type = "cpu"; |
| 61 | + i-cache-block-size = <0x40>; |
| 62 | + i-cache-sets = <0x40>; |
| 63 | + i-cache-size = <0x4000>; |
| 64 | + i-tlb-sets = <0x01>; |
| 65 | + i-tlb-size = <0x20>; |
| 66 | + mmu-type = "riscv,sv39"; |
| 67 | + next-level-cache = <0x02>; |
| 68 | + reg = <0x00>; |
| 69 | + riscv,isa = "rv64imafdc"; |
| 70 | + riscv,isa-base = "rv64i"; |
| 71 | + riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", "zihpm"; |
| 72 | + status = "okay"; |
| 73 | + timebase-frequency = <0xf4240>; |
| 74 | + tlb-split; |
| 75 | + |
| 76 | + interrupt-controller { |
| 77 | + #address-cells = <0x02>; |
| 78 | + #interrupt-cells = <0x01>; |
| 79 | + compatible = "riscv,cpu-intc"; |
| 80 | + interrupt-controller; |
| 81 | + phandle = <0x01>; |
| 82 | + }; |
| 83 | + }; |
| 84 | + }; |
| 85 | +}; |
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