diff --git a/MODULE.bazel.lock b/MODULE.bazel.lock
index fa65afe2..bc3705a3 100644
--- a/MODULE.bazel.lock
+++ b/MODULE.bazel.lock
@@ -2005,8 +2005,8 @@
         "bzlTransitiveDigest": "NWG/zr7TmqNjKiFdm1yVDA5cIKBVybQcHs2v6Jj3knc=",
         "usagesDigest": "ZgXht80CWumrDcfuuFR/TIuoRsux94U5UO6wxAREUa4=",
         "recordedFileInputs": {
-          "@@//third_party/crates_io/Cargo.lock": "8e7ecf84003bd5665089d1b6e8f98bcc066828bd8ce0d176c3ebb0ff9775f585",
-          "@@//third_party/crates_io/Cargo.toml": "4861db42333cdd603876a1c5628268590f6936c9fed036e9ace092195632f3e2",
+          "@@//third_party/crates_io/Cargo.lock": "b6a26d91198cfa3ab8854b25b87281f6007903115552ac16d05136f0ede5fb82",
+          "@@//third_party/crates_io/Cargo.toml": "5bfb597e724723504a23a90e07e1fc0dc874f214017ab65abf38a0e4c3a838aa",
           "@@pigweed+//third_party/crates_io/crates_no_std/Cargo.lock": "d38da5fa5f942b59a8017730285afe69aaf6f741b6171f361d66202de3473bc2",
           "@@pigweed+//third_party/crates_io/crates_no_std/Cargo.toml": "00e4a621a4a49d1b269bb2e688d8b5bbabb8700eb7b583ccaa20c36a60aebf98",
           "@@pigweed+//third_party/crates_io/crates_std/Cargo.lock": "13ffbc71abd52f9c79d69ce7101aca75faddaefb314ab8b112a623ab0ea81540",
@@ -2028,9 +2028,9 @@
             "repoRuleId": "@@rules_rust+//crate_universe:extensions.bzl%_generate_repo",
             "attributes": {
               "contents": {
-                "BUILD.bazel": "###############################################################################\n# @generated\n# DO NOT MODIFY: This file is auto-generated by a crate_universe tool. To \n# regenerate this file, run the following:\n#\n#     bazel mod show_repo 'openprot'\n###############################################################################\n\npackage(default_visibility = [\"//visibility:public\"])\n\nexports_files(\n    [\n        \"cargo-bazel.json\",\n        \"crates.bzl\",\n        \"defs.bzl\",\n    ] + glob(\n        allow_empty = True,\n        include = [\"*.bazel\"],\n    ),\n)\n\nfilegroup(\n    name = \"srcs\",\n    srcs = glob(\n        allow_empty = True,\n        include = [\n            \"*.bazel\",\n            \"*.bzl\",\n        ],\n    ),\n)\n\n# Workspace Member Dependencies\nalias(\n    name = \"aes-0.8.4\",\n    actual = \"@rust_crates__aes-0.8.4//:aes\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"aes\",\n    actual = \"@rust_crates__aes-0.8.4//:aes\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"aes-gcm-0.10.3\",\n    actual = \"@rust_crates__aes-gcm-0.10.3//:aes_gcm\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"aes-gcm\",\n    actual = \"@rust_crates__aes-gcm-0.10.3//:aes_gcm\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"anyhow-1.0.102\",\n    actual = \"@rust_crates__anyhow-1.0.102//:anyhow\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"anyhow\",\n    actual = \"@rust_crates__anyhow-1.0.102//:anyhow\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"bitfield-struct-0.11.0\",\n    actual = \"@rust_crates__bitfield-struct-0.11.0//:bitfield_struct\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"bitfield-struct\",\n    actual = \"@rust_crates__bitfield-struct-0.11.0//:bitfield_struct\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"bitflags-2.11.0\",\n    actual = \"@rust_crates__bitflags-2.11.0//:bitflags\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"bitflags\",\n    actual = \"@rust_crates__bitflags-2.11.0//:bitflags\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"byteorder-1.5.0\",\n    actual = \"@rust_crates__byteorder-1.5.0//:byteorder\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"byteorder\",\n    actual = \"@rust_crates__byteorder-1.5.0//:byteorder\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"cipher-0.4.4\",\n    actual = \"@rust_crates__cipher-0.4.4//:cipher\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"cipher\",\n    actual = \"@rust_crates__cipher-0.4.4//:cipher\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"clap-4.5.60\",\n    actual = \"@rust_crates__clap-4.5.60//:clap\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"clap\",\n    actual = \"@rust_crates__clap-4.5.60//:clap\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"compiler_builtins-0.1.160\",\n    actual = \"@rust_crates__compiler_builtins-0.1.160//:compiler_builtins\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"compiler_builtins\",\n    actual = \"@rust_crates__compiler_builtins-0.1.160//:compiler_builtins\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"cortex-m-0.7.7\",\n    actual = \"@rust_crates__cortex-m-0.7.7//:cortex_m\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"cortex-m\",\n    actual = \"@rust_crates__cortex-m-0.7.7//:cortex_m\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"ctr-0.9.2\",\n    actual = \"@rust_crates__ctr-0.9.2//:ctr\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"ctr\",\n    actual = \"@rust_crates__ctr-0.9.2//:ctr\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal-1.0.0\",\n    actual = \"@rust_crates__embedded-hal-1.0.0//:embedded_hal\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal\",\n    actual = \"@rust_crates__embedded-hal-1.0.0//:embedded_hal\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal-async-1.0.0\",\n    actual = \"@rust_crates__embedded-hal-async-1.0.0//:embedded_hal_async\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal-async\",\n    actual = \"@rust_crates__embedded-hal-async-1.0.0//:embedded_hal_async\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal-nb-1.0.0\",\n    actual = \"@rust_crates__embedded-hal-nb-1.0.0//:embedded_hal_nb\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal-nb\",\n    actual = \"@rust_crates__embedded-hal-nb-1.0.0//:embedded_hal_nb\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-io-0.6.1\",\n    actual = \"@rust_crates__embedded-io-0.6.1//:embedded_io\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-io\",\n    actual = \"@rust_crates__embedded-io-0.6.1//:embedded_io\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"hashlink-0.10.0\",\n    actual = \"@rust_crates__hashlink-0.10.0//:hashlink\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"hashlink\",\n    actual = \"@rust_crates__hashlink-0.10.0//:hashlink\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"heapless-0.9.2\",\n    actual = \"@rust_crates__heapless-0.9.2//:heapless\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"heapless\",\n    actual = \"@rust_crates__heapless-0.9.2//:heapless\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"hmac-0.12.1\",\n    actual = \"@rust_crates__hmac-0.12.1//:hmac\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"hmac\",\n    actual = \"@rust_crates__hmac-0.12.1//:hmac\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"k256-0.13.4\",\n    actual = \"@rust_crates__k256-0.13.4//:k256\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"k256\",\n    actual = \"@rust_crates__k256-0.13.4//:k256\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"minijinja-2.16.0\",\n    actual = \"@rust_crates__minijinja-2.16.0//:minijinja\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"minijinja\",\n    actual = \"@rust_crates__minijinja-2.16.0//:minijinja\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"nb-1.1.0\",\n    actual = \"@rust_crates__nb-1.1.0//:nb\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"nb\",\n    actual = \"@rust_crates__nb-1.1.0//:nb\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"nom-7.1.3\",\n    actual = \"@rust_crates__nom-7.1.3//:nom\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"nom\",\n    actual = \"@rust_crates__nom-7.1.3//:nom\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"object-0.37.3\",\n    actual = \"@rust_crates__object-0.37.3//:object\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"object\",\n    actual = \"@rust_crates__object-0.37.3//:object\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"p256-0.13.2\",\n    actual = \"@rust_crates__p256-0.13.2//:p256\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"p256\",\n    actual = \"@rust_crates__p256-0.13.2//:p256\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"p384-0.13.1\",\n    actual = \"@rust_crates__p384-0.13.1//:p384\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"p384\",\n    actual = \"@rust_crates__p384-0.13.1//:p384\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"panic-halt-1.0.0\",\n    actual = \"@rust_crates__panic-halt-1.0.0//:panic_halt\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"panic-halt\",\n    actual = \"@rust_crates__panic-halt-1.0.0//:panic_halt\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"paste-1.0.15\",\n    actual = \"@rust_crates__paste-1.0.15//:paste\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"paste\",\n    actual = \"@rust_crates__paste-1.0.15//:paste\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"proc-macro2-1.0.106\",\n    actual = \"@rust_crates__proc-macro2-1.0.106//:proc_macro2\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"proc-macro2\",\n    actual = \"@rust_crates__proc-macro2-1.0.106//:proc_macro2\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"quote-1.0.44\",\n    actual = \"@rust_crates__quote-1.0.44//:quote\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"quote\",\n    actual = \"@rust_crates__quote-1.0.44//:quote\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"rand_core-0.9.5\",\n    actual = \"@rust_crates__rand_core-0.9.5//:rand_core\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"rand_core\",\n    actual = \"@rust_crates__rand_core-0.9.5//:rand_core\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"riscv-0.12.1\",\n    actual = \"@rust_crates__riscv-0.12.1//:riscv\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"riscv\",\n    actual = \"@rust_crates__riscv-0.12.1//:riscv\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"riscv-rt-0.12.2\",\n    actual = \"@rust_crates__riscv-rt-0.12.2//:riscv_rt\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"riscv-rt\",\n    actual = \"@rust_crates__riscv-rt-0.12.2//:riscv_rt\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"riscv-semihosting-0.1.3\",\n    actual = \"@rust_crates__riscv-semihosting-0.1.3//:riscv_semihosting\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"riscv-semihosting\",\n    actual = \"@rust_crates__riscv-semihosting-0.1.3//:riscv_semihosting\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"rustc-demangle-0.1.27\",\n    actual = \"@rust_crates__rustc-demangle-0.1.27//:rustc_demangle\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"rustc-demangle\",\n    actual = \"@rust_crates__rustc-demangle-0.1.27//:rustc_demangle\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"serde-1.0.228\",\n    actual = \"@rust_crates__serde-1.0.228//:serde\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"serde\",\n    actual = \"@rust_crates__serde-1.0.228//:serde\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"serde_json5-0.2.1\",\n    actual = \"@rust_crates__serde_json5-0.2.1//:serde_json5\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"serde_json5\",\n    actual = \"@rust_crates__serde_json5-0.2.1//:serde_json5\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"sha2-0.10.9\",\n    actual = \"@rust_crates__sha2-0.10.9//:sha2\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"sha2\",\n    actual = \"@rust_crates__sha2-0.10.9//:sha2\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"sha3-0.10.8\",\n    actual = \"@rust_crates__sha3-0.10.8//:sha3\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"sha3\",\n    actual = \"@rust_crates__sha3-0.10.8//:sha3\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"subtle-2.6.1\",\n    actual = \"@rust_crates__subtle-2.6.1//:subtle\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"subtle\",\n    actual = \"@rust_crates__subtle-2.6.1//:subtle\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"syn-2.0.116\",\n    actual = \"@rust_crates__syn-2.0.116//:syn\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"syn\",\n    actual = \"@rust_crates__syn-2.0.116//:syn\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"toml-0.8.23\",\n    actual = \"@rust_crates__toml-0.8.23//:toml\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"toml\",\n    actual = \"@rust_crates__toml-0.8.23//:toml\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"zerocopy-0.8.39\",\n    actual = \"@rust_crates__zerocopy-0.8.39//:zerocopy\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"zerocopy\",\n    actual = \"@rust_crates__zerocopy-0.8.39//:zerocopy\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"zeroize-1.8.2\",\n    actual = \"@rust_crates__zeroize-1.8.2//:zeroize\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"zeroize\",\n    actual = \"@rust_crates__zeroize-1.8.2//:zeroize\",\n    tags = [\"manual\"],\n)\n",
+                "BUILD.bazel": "###############################################################################\n# @generated\n# DO NOT MODIFY: This file is auto-generated by a crate_universe tool. To \n# regenerate this file, run the following:\n#\n#     bazel mod show_repo 'openprot'\n###############################################################################\n\npackage(default_visibility = [\"//visibility:public\"])\n\nexports_files(\n    [\n        \"cargo-bazel.json\",\n        \"crates.bzl\",\n        \"defs.bzl\",\n    ] + glob(\n        allow_empty = True,\n        include = [\"*.bazel\"],\n    ),\n)\n\nfilegroup(\n    name = \"srcs\",\n    srcs = glob(\n        allow_empty = True,\n        include = [\n            \"*.bazel\",\n            \"*.bzl\",\n        ],\n    ),\n)\n\n# Workspace Member Dependencies\nalias(\n    name = \"aes-0.8.4\",\n    actual = \"@rust_crates__aes-0.8.4//:aes\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"aes\",\n    actual = \"@rust_crates__aes-0.8.4//:aes\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"aes-gcm-0.10.3\",\n    actual = \"@rust_crates__aes-gcm-0.10.3//:aes_gcm\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"aes-gcm\",\n    actual = \"@rust_crates__aes-gcm-0.10.3//:aes_gcm\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"aligned-0.4.3\",\n    actual = \"@rust_crates__aligned-0.4.3//:aligned\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"aligned\",\n    actual = \"@rust_crates__aligned-0.4.3//:aligned\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"anyhow-1.0.102\",\n    actual = \"@rust_crates__anyhow-1.0.102//:anyhow\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"anyhow\",\n    actual = \"@rust_crates__anyhow-1.0.102//:anyhow\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"bitfield-struct-0.11.0\",\n    actual = \"@rust_crates__bitfield-struct-0.11.0//:bitfield_struct\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"bitfield-struct\",\n    actual = \"@rust_crates__bitfield-struct-0.11.0//:bitfield_struct\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"bitflags-2.11.0\",\n    actual = \"@rust_crates__bitflags-2.11.0//:bitflags\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"bitflags\",\n    actual = \"@rust_crates__bitflags-2.11.0//:bitflags\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"byteorder-1.5.0\",\n    actual = \"@rust_crates__byteorder-1.5.0//:byteorder\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"byteorder\",\n    actual = \"@rust_crates__byteorder-1.5.0//:byteorder\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"cipher-0.4.4\",\n    actual = \"@rust_crates__cipher-0.4.4//:cipher\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"cipher\",\n    actual = \"@rust_crates__cipher-0.4.4//:cipher\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"clap-4.5.60\",\n    actual = \"@rust_crates__clap-4.5.60//:clap\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"clap\",\n    actual = \"@rust_crates__clap-4.5.60//:clap\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"compiler_builtins-0.1.160\",\n    actual = \"@rust_crates__compiler_builtins-0.1.160//:compiler_builtins\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"compiler_builtins\",\n    actual = \"@rust_crates__compiler_builtins-0.1.160//:compiler_builtins\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"cortex-m-0.7.7\",\n    actual = \"@rust_crates__cortex-m-0.7.7//:cortex_m\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"cortex-m\",\n    actual = \"@rust_crates__cortex-m-0.7.7//:cortex_m\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"ctr-0.9.2\",\n    actual = \"@rust_crates__ctr-0.9.2//:ctr\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"ctr\",\n    actual = \"@rust_crates__ctr-0.9.2//:ctr\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal-1.0.0\",\n    actual = \"@rust_crates__embedded-hal-1.0.0//:embedded_hal\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal\",\n    actual = \"@rust_crates__embedded-hal-1.0.0//:embedded_hal\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal-async-1.0.0\",\n    actual = \"@rust_crates__embedded-hal-async-1.0.0//:embedded_hal_async\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal-async\",\n    actual = \"@rust_crates__embedded-hal-async-1.0.0//:embedded_hal_async\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal-nb-1.0.0\",\n    actual = \"@rust_crates__embedded-hal-nb-1.0.0//:embedded_hal_nb\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal-nb\",\n    actual = \"@rust_crates__embedded-hal-nb-1.0.0//:embedded_hal_nb\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-io-0.6.1\",\n    actual = \"@rust_crates__embedded-io-0.6.1//:embedded_io\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-io\",\n    actual = \"@rust_crates__embedded-io-0.6.1//:embedded_io\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"hashlink-0.10.0\",\n    actual = \"@rust_crates__hashlink-0.10.0//:hashlink\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"hashlink\",\n    actual = \"@rust_crates__hashlink-0.10.0//:hashlink\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"heapless-0.9.2\",\n    actual = \"@rust_crates__heapless-0.9.2//:heapless\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"heapless\",\n    actual = \"@rust_crates__heapless-0.9.2//:heapless\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"hmac-0.12.1\",\n    actual = \"@rust_crates__hmac-0.12.1//:hmac\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"hmac\",\n    actual = \"@rust_crates__hmac-0.12.1//:hmac\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"k256-0.13.4\",\n    actual = \"@rust_crates__k256-0.13.4//:k256\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"k256\",\n    actual = \"@rust_crates__k256-0.13.4//:k256\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"minijinja-2.16.0\",\n    actual = \"@rust_crates__minijinja-2.16.0//:minijinja\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"minijinja\",\n    actual = \"@rust_crates__minijinja-2.16.0//:minijinja\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"nb-1.1.0\",\n    actual = \"@rust_crates__nb-1.1.0//:nb\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"nb\",\n    actual = \"@rust_crates__nb-1.1.0//:nb\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"nom-7.1.3\",\n    actual = \"@rust_crates__nom-7.1.3//:nom\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"nom\",\n    actual = \"@rust_crates__nom-7.1.3//:nom\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"object-0.37.3\",\n    actual = \"@rust_crates__object-0.37.3//:object\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"object\",\n    actual = \"@rust_crates__object-0.37.3//:object\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"p256-0.13.2\",\n    actual = \"@rust_crates__p256-0.13.2//:p256\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"p256\",\n    actual = \"@rust_crates__p256-0.13.2//:p256\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"p384-0.13.1\",\n    actual = \"@rust_crates__p384-0.13.1//:p384\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"p384\",\n    actual = \"@rust_crates__p384-0.13.1//:p384\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"panic-halt-1.0.0\",\n    actual = \"@rust_crates__panic-halt-1.0.0//:panic_halt\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"panic-halt\",\n    actual = \"@rust_crates__panic-halt-1.0.0//:panic_halt\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"paste-1.0.15\",\n    actual = \"@rust_crates__paste-1.0.15//:paste\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"paste\",\n    actual = \"@rust_crates__paste-1.0.15//:paste\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"proc-macro2-1.0.106\",\n    actual = \"@rust_crates__proc-macro2-1.0.106//:proc_macro2\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"proc-macro2\",\n    actual = \"@rust_crates__proc-macro2-1.0.106//:proc_macro2\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"quote-1.0.44\",\n    actual = \"@rust_crates__quote-1.0.44//:quote\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"quote\",\n    actual = \"@rust_crates__quote-1.0.44//:quote\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"rand_core-0.9.5\",\n    actual = \"@rust_crates__rand_core-0.9.5//:rand_core\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"rand_core\",\n    actual = \"@rust_crates__rand_core-0.9.5//:rand_core\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"riscv-0.12.1\",\n    actual = \"@rust_crates__riscv-0.12.1//:riscv\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"riscv\",\n    actual = \"@rust_crates__riscv-0.12.1//:riscv\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"riscv-rt-0.12.2\",\n    actual = \"@rust_crates__riscv-rt-0.12.2//:riscv_rt\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"riscv-rt\",\n    actual = \"@rust_crates__riscv-rt-0.12.2//:riscv_rt\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"riscv-semihosting-0.1.3\",\n    actual = \"@rust_crates__riscv-semihosting-0.1.3//:riscv_semihosting\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"riscv-semihosting\",\n    actual = \"@rust_crates__riscv-semihosting-0.1.3//:riscv_semihosting\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"rustc-demangle-0.1.27\",\n    actual = \"@rust_crates__rustc-demangle-0.1.27//:rustc_demangle\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"rustc-demangle\",\n    actual = \"@rust_crates__rustc-demangle-0.1.27//:rustc_demangle\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"serde-1.0.228\",\n    actual = \"@rust_crates__serde-1.0.228//:serde\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"serde\",\n    actual = \"@rust_crates__serde-1.0.228//:serde\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"serde_json5-0.2.1\",\n    actual = \"@rust_crates__serde_json5-0.2.1//:serde_json5\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"serde_json5\",\n    actual = \"@rust_crates__serde_json5-0.2.1//:serde_json5\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"sha2-0.10.9\",\n    actual = \"@rust_crates__sha2-0.10.9//:sha2\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"sha2\",\n    actual = \"@rust_crates__sha2-0.10.9//:sha2\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"sha3-0.10.8\",\n    actual = \"@rust_crates__sha3-0.10.8//:sha3\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"sha3\",\n    actual = \"@rust_crates__sha3-0.10.8//:sha3\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"subtle-2.6.1\",\n    actual = \"@rust_crates__subtle-2.6.1//:subtle\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"subtle\",\n    actual = \"@rust_crates__subtle-2.6.1//:subtle\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"syn-2.0.116\",\n    actual = \"@rust_crates__syn-2.0.116//:syn\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"syn\",\n    actual = \"@rust_crates__syn-2.0.116//:syn\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"toml-0.8.23\",\n    actual = \"@rust_crates__toml-0.8.23//:toml\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"toml\",\n    actual = \"@rust_crates__toml-0.8.23//:toml\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"ufmt-0.2.0\",\n    actual = \"@rust_crates__ufmt-0.2.0//:ufmt\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"ufmt\",\n    actual = \"@rust_crates__ufmt-0.2.0//:ufmt\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"zerocopy-0.8.39\",\n    actual = \"@rust_crates__zerocopy-0.8.39//:zerocopy\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"zerocopy\",\n    actual = \"@rust_crates__zerocopy-0.8.39//:zerocopy\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"zeroize-1.8.2\",\n    actual = \"@rust_crates__zeroize-1.8.2//:zeroize\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"zeroize\",\n    actual = \"@rust_crates__zeroize-1.8.2//:zeroize\",\n    tags = [\"manual\"],\n)\n",
                 "alias_rules.bzl": "\"\"\"Alias that transitions its target to `compilation_mode=opt`.  Use `transition_alias=\"opt\"` to enable.\"\"\"\n\nload(\"@rules_cc//cc:defs.bzl\", \"CcInfo\")\nload(\"@rules_rust//rust:rust_common.bzl\", \"COMMON_PROVIDERS\")\n\ndef _transition_alias_impl(ctx):\n    # `ctx.attr.actual` is a list of 1 item due to the transition\n    providers = [ctx.attr.actual[0][provider] for provider in COMMON_PROVIDERS]\n    if CcInfo in ctx.attr.actual[0]:\n        providers.append(ctx.attr.actual[0][CcInfo])\n    return providers\n\ndef _change_compilation_mode(compilation_mode):\n    def _change_compilation_mode_impl(_settings, _attr):\n        return {\n            \"//command_line_option:compilation_mode\": compilation_mode,\n        }\n\n    return transition(\n        implementation = _change_compilation_mode_impl,\n        inputs = [],\n        outputs = [\n            \"//command_line_option:compilation_mode\",\n        ],\n    )\n\ndef _transition_alias_rule(compilation_mode):\n    return rule(\n        implementation = _transition_alias_impl,\n        provides = COMMON_PROVIDERS,\n        attrs = {\n            \"actual\": attr.label(\n                mandatory = True,\n                doc = \"`rust_library()` target to transition to `compilation_mode=opt`.\",\n                providers = COMMON_PROVIDERS,\n                cfg = _change_compilation_mode(compilation_mode),\n            ),\n            \"_allowlist_function_transition\": attr.label(\n                default = \"@bazel_tools//tools/allowlists/function_transition_allowlist\",\n            ),\n        },\n        doc = \"Transitions a Rust library crate to the `compilation_mode=opt`.\",\n    )\n\ntransition_alias_dbg = _transition_alias_rule(\"dbg\")\ntransition_alias_fastbuild = _transition_alias_rule(\"fastbuild\")\ntransition_alias_opt = _transition_alias_rule(\"opt\")\n",
-                "defs.bzl": "###############################################################################\n# @generated\n# DO NOT MODIFY: This file is auto-generated by a crate_universe tool. To \n# regenerate this file, run the following:\n#\n#     bazel mod show_repo 'openprot'\n###############################################################################\n\"\"\"\n# `crates_repository` API\n\n- [aliases](#aliases)\n- [crate_deps](#crate_deps)\n- [all_crate_deps](#all_crate_deps)\n- [crate_repositories](#crate_repositories)\n\n\"\"\"\n\nload(\"@bazel_tools//tools/build_defs/repo:git.bzl\", \"new_git_repository\")\nload(\"@bazel_tools//tools/build_defs/repo:http.bzl\", \"http_archive\")\nload(\"@bazel_tools//tools/build_defs/repo:utils.bzl\", \"maybe\")\nload(\"@bazel_skylib//lib:selects.bzl\", \"selects\")\nload(\"@rules_rust//crate_universe/private:local_crate_mirror.bzl\", \"local_crate_mirror\")\n\n###############################################################################\n# MACROS API\n###############################################################################\n\n# An identifier that represent common dependencies (unconditional).\n_COMMON_CONDITION = \"\"\n\ndef _flatten_dependency_maps(all_dependency_maps):\n    \"\"\"Flatten a list of dependency maps into one dictionary.\n\n    Dependency maps have the following structure:\n\n    ```python\n    DEPENDENCIES_MAP = {\n        # The first key in the map is a Bazel package\n        # name of the workspace this file is defined in.\n        \"workspace_member_package\": {\n\n            # Not all dependencies are supported for all platforms.\n            # the condition key is the condition required to be true\n            # on the host platform.\n            \"condition\": {\n\n                # An alias to a crate target.     # The label of the crate target the\n                # Aliases are only crate names.   # package name refers to.\n                \"package_name\":                   \"@full//:label\",\n            }\n        }\n    }\n    ```\n\n    Args:\n        all_dependency_maps (list): A list of dicts as described above\n\n    Returns:\n        dict: A dictionary as described above\n    \"\"\"\n    dependencies = {}\n\n    for workspace_deps_map in all_dependency_maps:\n        for pkg_name, conditional_deps_map in workspace_deps_map.items():\n            if pkg_name not in dependencies:\n                non_frozen_map = dict()\n                for key, values in conditional_deps_map.items():\n                    non_frozen_map.update({key: dict(values.items())})\n                dependencies.setdefault(pkg_name, non_frozen_map)\n                continue\n\n            for condition, deps_map in conditional_deps_map.items():\n                # If the condition has not been recorded, do so and continue\n                if condition not in dependencies[pkg_name]:\n                    dependencies[pkg_name].setdefault(condition, dict(deps_map.items()))\n                    continue\n\n                # Alert on any miss-matched dependencies\n                inconsistent_entries = []\n                for crate_name, crate_label in deps_map.items():\n                    existing = dependencies[pkg_name][condition].get(crate_name)\n                    if existing and existing != crate_label:\n                        inconsistent_entries.append((crate_name, existing, crate_label))\n                    dependencies[pkg_name][condition].update({crate_name: crate_label})\n\n    return dependencies\n\ndef crate_deps(deps, package_name = None):\n    \"\"\"Finds the fully qualified label of the requested crates for the package where this macro is called.\n\n    Args:\n        deps (list): The desired list of crate targets.\n        package_name (str, optional): The package name of the set of dependencies to look up.\n            Defaults to `native.package_name()`.\n\n    Returns:\n        list: A list of labels to generated rust targets (str)\n    \"\"\"\n\n    if not deps:\n        return []\n\n    if package_name == None:\n        package_name = native.package_name()\n\n    # Join both sets of dependencies\n    dependencies = _flatten_dependency_maps([\n        _NORMAL_DEPENDENCIES,\n        _NORMAL_DEV_DEPENDENCIES,\n        _PROC_MACRO_DEPENDENCIES,\n        _PROC_MACRO_DEV_DEPENDENCIES,\n        _BUILD_DEPENDENCIES,\n        _BUILD_PROC_MACRO_DEPENDENCIES,\n    ]).pop(package_name, {})\n\n    # Combine all conditional packages so we can easily index over a flat list\n    # TODO: Perhaps this should actually return select statements and maintain\n    # the conditionals of the dependencies\n    flat_deps = {}\n    for deps_set in dependencies.values():\n        for crate_name, crate_label in deps_set.items():\n            flat_deps.update({crate_name: crate_label})\n\n    missing_crates = []\n    crate_targets = []\n    for crate_target in deps:\n        if crate_target not in flat_deps:\n            missing_crates.append(crate_target)\n        else:\n            crate_targets.append(flat_deps[crate_target])\n\n    if missing_crates:\n        fail(\"Could not find crates `{}` among dependencies of `{}`. Available dependencies were `{}`\".format(\n            missing_crates,\n            package_name,\n            dependencies,\n        ))\n\n    return crate_targets\n\ndef all_crate_deps(\n        normal = False, \n        normal_dev = False, \n        proc_macro = False, \n        proc_macro_dev = False,\n        build = False,\n        build_proc_macro = False,\n        package_name = None):\n    \"\"\"Finds the fully qualified label of all requested direct crate dependencies \\\n    for the package where this macro is called.\n\n    If no parameters are set, all normal dependencies are returned. Setting any one flag will\n    otherwise impact the contents of the returned list.\n\n    Args:\n        normal (bool, optional): If True, normal dependencies are included in the\n            output list.\n        normal_dev (bool, optional): If True, normal dev dependencies will be\n            included in the output list..\n        proc_macro (bool, optional): If True, proc_macro dependencies are included\n            in the output list.\n        proc_macro_dev (bool, optional): If True, dev proc_macro dependencies are\n            included in the output list.\n        build (bool, optional): If True, build dependencies are included\n            in the output list.\n        build_proc_macro (bool, optional): If True, build proc_macro dependencies are\n            included in the output list.\n        package_name (str, optional): The package name of the set of dependencies to look up.\n            Defaults to `native.package_name()` when unset.\n\n    Returns:\n        list: A list of labels to generated rust targets (str)\n    \"\"\"\n\n    if package_name == None:\n        package_name = native.package_name()\n\n    # Determine the relevant maps to use\n    all_dependency_maps = []\n    if normal:\n        all_dependency_maps.append(_NORMAL_DEPENDENCIES)\n    if normal_dev:\n        all_dependency_maps.append(_NORMAL_DEV_DEPENDENCIES)\n    if proc_macro:\n        all_dependency_maps.append(_PROC_MACRO_DEPENDENCIES)\n    if proc_macro_dev:\n        all_dependency_maps.append(_PROC_MACRO_DEV_DEPENDENCIES)\n    if build:\n        all_dependency_maps.append(_BUILD_DEPENDENCIES)\n    if build_proc_macro:\n        all_dependency_maps.append(_BUILD_PROC_MACRO_DEPENDENCIES)\n\n    # Default to always using normal dependencies\n    if not all_dependency_maps:\n        all_dependency_maps.append(_NORMAL_DEPENDENCIES)\n\n    dependencies = _flatten_dependency_maps(all_dependency_maps).pop(package_name, None)\n\n    if not dependencies:\n        if dependencies == None:\n            fail(\"Tried to get all_crate_deps for package \" + package_name + \" but that package had no Cargo.toml file\")\n        else:\n            return []\n\n    crate_deps = list(dependencies.pop(_COMMON_CONDITION, {}).values())\n    for condition, deps in dependencies.items():\n        crate_deps += selects.with_or({\n            tuple(_CONDITIONS[condition]): deps.values(),\n            \"//conditions:default\": [],\n        })\n\n    return crate_deps\n\ndef aliases(\n        normal = False,\n        normal_dev = False,\n        proc_macro = False,\n        proc_macro_dev = False,\n        build = False,\n        build_proc_macro = False,\n        package_name = None):\n    \"\"\"Produces a map of Crate alias names to their original label\n\n    If no dependency kinds are specified, `normal` and `proc_macro` are used by default.\n    Setting any one flag will otherwise determine the contents of the returned dict.\n\n    Args:\n        normal (bool, optional): If True, normal dependencies are included in the\n            output list.\n        normal_dev (bool, optional): If True, normal dev dependencies will be\n            included in the output list..\n        proc_macro (bool, optional): If True, proc_macro dependencies are included\n            in the output list.\n        proc_macro_dev (bool, optional): If True, dev proc_macro dependencies are\n            included in the output list.\n        build (bool, optional): If True, build dependencies are included\n            in the output list.\n        build_proc_macro (bool, optional): If True, build proc_macro dependencies are\n            included in the output list.\n        package_name (str, optional): The package name of the set of dependencies to look up.\n            Defaults to `native.package_name()` when unset.\n\n    Returns:\n        dict: The aliases of all associated packages\n    \"\"\"\n    if package_name == None:\n        package_name = native.package_name()\n\n    # Determine the relevant maps to use\n    all_aliases_maps = []\n    if normal:\n        all_aliases_maps.append(_NORMAL_ALIASES)\n    if normal_dev:\n        all_aliases_maps.append(_NORMAL_DEV_ALIASES)\n    if proc_macro:\n        all_aliases_maps.append(_PROC_MACRO_ALIASES)\n    if proc_macro_dev:\n        all_aliases_maps.append(_PROC_MACRO_DEV_ALIASES)\n    if build:\n        all_aliases_maps.append(_BUILD_ALIASES)\n    if build_proc_macro:\n        all_aliases_maps.append(_BUILD_PROC_MACRO_ALIASES)\n\n    # Default to always using normal aliases\n    if not all_aliases_maps:\n        all_aliases_maps.append(_NORMAL_ALIASES)\n        all_aliases_maps.append(_PROC_MACRO_ALIASES)\n\n    aliases = _flatten_dependency_maps(all_aliases_maps).pop(package_name, None)\n\n    if not aliases:\n        return dict()\n\n    common_items = aliases.pop(_COMMON_CONDITION, {}).items()\n\n    # If there are only common items in the dictionary, immediately return them\n    if not len(aliases.keys()) == 1:\n        return dict(common_items)\n\n    # Build a single select statement where each conditional has accounted for the\n    # common set of aliases.\n    crate_aliases = {\"//conditions:default\": dict(common_items)}\n    for condition, deps in aliases.items():\n        condition_triples = _CONDITIONS[condition]\n        for triple in condition_triples:\n            if triple in crate_aliases:\n                crate_aliases[triple].update(deps)\n            else:\n                crate_aliases.update({triple: dict(deps.items() + common_items)})\n\n    return select(crate_aliases)\n\n###############################################################################\n# WORKSPACE MEMBER DEPS AND ALIASES\n###############################################################################\n\n_NORMAL_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n        _COMMON_CONDITION: {\n            \"aes\": Label(\"@rust_crates//:aes-0.8.4\"),\n            \"aes-gcm\": Label(\"@rust_crates//:aes-gcm-0.10.3\"),\n            \"anyhow\": Label(\"@rust_crates//:anyhow-1.0.102\"),\n            \"bitflags\": Label(\"@rust_crates//:bitflags-2.11.0\"),\n            \"byteorder\": Label(\"@rust_crates//:byteorder-1.5.0\"),\n            \"cipher\": Label(\"@rust_crates//:cipher-0.4.4\"),\n            \"clap\": Label(\"@rust_crates//:clap-4.5.60\"),\n            \"compiler_builtins\": Label(\"@rust_crates//:compiler_builtins-0.1.160\"),\n            \"cortex-m\": Label(\"@rust_crates//:cortex-m-0.7.7\"),\n            \"ctr\": Label(\"@rust_crates//:ctr-0.9.2\"),\n            \"embedded-hal\": Label(\"@rust_crates//:embedded-hal-1.0.0\"),\n            \"embedded-hal-async\": Label(\"@rust_crates//:embedded-hal-async-1.0.0\"),\n            \"embedded-hal-nb\": Label(\"@rust_crates//:embedded-hal-nb-1.0.0\"),\n            \"embedded-io\": Label(\"@rust_crates//:embedded-io-0.6.1\"),\n            \"hashlink\": Label(\"@rust_crates//:hashlink-0.10.0\"),\n            \"heapless\": Label(\"@rust_crates//:heapless-0.9.2\"),\n            \"hmac\": Label(\"@rust_crates//:hmac-0.12.1\"),\n            \"k256\": Label(\"@rust_crates//:k256-0.13.4\"),\n            \"minijinja\": Label(\"@rust_crates//:minijinja-2.16.0\"),\n            \"nb\": Label(\"@rust_crates//:nb-1.1.0\"),\n            \"nom\": Label(\"@rust_crates//:nom-7.1.3\"),\n            \"object\": Label(\"@rust_crates//:object-0.37.3\"),\n            \"p256\": Label(\"@rust_crates//:p256-0.13.2\"),\n            \"p384\": Label(\"@rust_crates//:p384-0.13.1\"),\n            \"panic-halt\": Label(\"@rust_crates//:panic-halt-1.0.0\"),\n            \"proc-macro2\": Label(\"@rust_crates//:proc-macro2-1.0.106\"),\n            \"quote\": Label(\"@rust_crates//:quote-1.0.44\"),\n            \"rand_core\": Label(\"@rust_crates//:rand_core-0.9.5\"),\n            \"riscv\": Label(\"@rust_crates//:riscv-0.12.1\"),\n            \"riscv-rt\": Label(\"@rust_crates//:riscv-rt-0.12.2\"),\n            \"riscv-semihosting\": Label(\"@rust_crates//:riscv-semihosting-0.1.3\"),\n            \"rustc-demangle\": Label(\"@rust_crates//:rustc-demangle-0.1.27\"),\n            \"serde\": Label(\"@rust_crates//:serde-1.0.228\"),\n            \"serde_json5\": Label(\"@rust_crates//:serde_json5-0.2.1\"),\n            \"sha2\": Label(\"@rust_crates//:sha2-0.10.9\"),\n            \"sha3\": Label(\"@rust_crates//:sha3-0.10.8\"),\n            \"subtle\": Label(\"@rust_crates//:subtle-2.6.1\"),\n            \"syn\": Label(\"@rust_crates//:syn-2.0.116\"),\n            \"toml\": Label(\"@rust_crates//:toml-0.8.23\"),\n            \"zerocopy\": Label(\"@rust_crates//:zerocopy-0.8.39\"),\n            \"zeroize\": Label(\"@rust_crates//:zeroize-1.8.2\"),\n        },\n    },\n}\n\n\n_NORMAL_ALIASES = {\n    \"third_party/crates_io\": {\n        _COMMON_CONDITION: {\n        },\n    },\n}\n\n\n_NORMAL_DEV_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_NORMAL_DEV_ALIASES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_PROC_MACRO_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n        _COMMON_CONDITION: {\n            \"bitfield-struct\": Label(\"@rust_crates//:bitfield-struct-0.11.0\"),\n            \"paste\": Label(\"@rust_crates//:paste-1.0.15\"),\n        },\n    },\n}\n\n\n_PROC_MACRO_ALIASES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_PROC_MACRO_DEV_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_PROC_MACRO_DEV_ALIASES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_BUILD_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_BUILD_ALIASES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_BUILD_PROC_MACRO_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_BUILD_PROC_MACRO_ALIASES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_CONDITIONS = {\n    \"aarch64-apple-darwin\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\"],\n    \"aarch64-linux-android\": [],\n    \"aarch64-unknown-linux-gnu\": [\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\"],\n    \"cfg(all(target_arch = \\\"aarch64\\\", target_os = \\\"linux\\\"))\": [\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\"],\n    \"cfg(all(target_arch = \\\"aarch64\\\", target_vendor = \\\"apple\\\"))\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\"],\n    \"cfg(all(target_arch = \\\"loongarch64\\\", target_os = \\\"linux\\\"))\": [],\n    \"cfg(any())\": [],\n    \"cfg(any(target_arch = \\\"aarch64\\\", target_arch = \\\"x86_64\\\", target_arch = \\\"x86\\\"))\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\",\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\",\"@rules_rust//rust/platform:x86_64-apple-darwin\",\"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\"],\n    \"cfg(any(target_arch = \\\"arm\\\", target_pointer_width = \\\"32\\\", target_pointer_width = \\\"64\\\"))\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\",\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\",\"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\",\"@rules_rust//rust/platform:x86_64-apple-darwin\",\"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\"],\n    \"cfg(target_arch = \\\"aarch64\\\")\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\",\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\"],\n    \"cfg(windows)\": [],\n    \"riscv32imc-unknown-none-elf\": [\"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\"],\n    \"x86_64-apple-darwin\": [\"@rules_rust//rust/platform:x86_64-apple-darwin\"],\n    \"x86_64-unknown-linux-gnu\": [\"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\"],\n}\n\n###############################################################################\n\ndef crate_repositories():\n    \"\"\"A macro for defining repositories for all generated crates.\n\n    Returns:\n      A list of repos visible to the module through the module extension.\n    \"\"\"\n    maybe(\n        http_archive,\n        name = \"rust_crates__adler2-2.0.1\",\n        sha256 = \"320119579fcad9c21884f5c4861d16174d0e06250625266f50fe6898340abefa\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/adler2/2.0.1/download\"],\n        strip_prefix = \"adler2-2.0.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.adler2-2.0.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__aead-0.5.2\",\n        sha256 = \"d122413f284cf2d62fb1b7db97e02edb8cda96d769b16e443a4f6195e35662b0\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/aead/0.5.2/download\"],\n        strip_prefix = \"aead-0.5.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.aead-0.5.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__aes-0.8.4\",\n        sha256 = \"b169f7a6d4742236a0a00c541b845991d0ac43e546831af1249753ab4c3aa3a0\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/aes/0.8.4/download\"],\n        strip_prefix = \"aes-0.8.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.aes-0.8.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__aes-gcm-0.10.3\",\n        sha256 = \"831010a0f742e1209b3bcea8fab6a8e149051ba6099432c8cb2cc117dec3ead1\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/aes-gcm/0.10.3/download\"],\n        strip_prefix = \"aes-gcm-0.10.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.aes-gcm-0.10.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anstream-0.6.21\",\n        sha256 = \"43d5b281e737544384e969a5ccad3f1cdd24b48086a0fc1b2a5262a26b8f4f4a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anstream/0.6.21/download\"],\n        strip_prefix = \"anstream-0.6.21\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anstream-0.6.21.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anstyle-1.0.13\",\n        sha256 = \"5192cca8006f1fd4f7237516f40fa183bb07f8fbdfedaa0036de5ea9b0b45e78\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anstyle/1.0.13/download\"],\n        strip_prefix = \"anstyle-1.0.13\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anstyle-1.0.13.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anstyle-parse-0.2.7\",\n        sha256 = \"4e7644824f0aa2c7b9384579234ef10eb7efb6a0deb83f9630a49594dd9c15c2\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anstyle-parse/0.2.7/download\"],\n        strip_prefix = \"anstyle-parse-0.2.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anstyle-parse-0.2.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anstyle-query-1.1.5\",\n        sha256 = \"40c48f72fd53cd289104fc64099abca73db4166ad86ea0b4341abe65af83dadc\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anstyle-query/1.1.5/download\"],\n        strip_prefix = \"anstyle-query-1.1.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anstyle-query-1.1.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anstyle-wincon-3.0.11\",\n        sha256 = \"291e6a250ff86cd4a820112fb8898808a366d8f9f58ce16d1f538353ad55747d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anstyle-wincon/3.0.11/download\"],\n        strip_prefix = \"anstyle-wincon-3.0.11\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anstyle-wincon-3.0.11.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anyhow-1.0.102\",\n        sha256 = \"7f202df86484c868dbad7eaa557ef785d5c66295e41b460ef922eca0723b842c\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anyhow/1.0.102/download\"],\n        strip_prefix = \"anyhow-1.0.102\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anyhow-1.0.102.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__bare-metal-0.2.5\",\n        sha256 = \"5deb64efa5bd81e31fcd1938615a6d98c82eafcbcd787162b6f63b91d6bac5b3\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/bare-metal/0.2.5/download\"],\n        strip_prefix = \"bare-metal-0.2.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.bare-metal-0.2.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__base16ct-0.2.0\",\n        sha256 = \"4c7f02d4ea65f2c1853089ffd8d2787bdbc63de2f0d29dedbcf8ccdfa0ccd4cf\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/base16ct/0.2.0/download\"],\n        strip_prefix = \"base16ct-0.2.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.base16ct-0.2.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__bitfield-0.13.2\",\n        sha256 = \"46afbd2983a5d5a7bd740ccb198caf5b82f45c40c09c0eed36052d91cb92e719\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/bitfield/0.13.2/download\"],\n        strip_prefix = \"bitfield-0.13.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.bitfield-0.13.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__bitfield-struct-0.11.0\",\n        sha256 = \"d3ca019570363e800b05ad4fd890734f28ac7b72f563ad8a35079efb793616f8\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/bitfield-struct/0.11.0/download\"],\n        strip_prefix = \"bitfield-struct-0.11.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.bitfield-struct-0.11.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__bitflags-2.11.0\",\n        sha256 = \"843867be96c8daad0d758b57df9392b6d8d271134fce549de6ce169ff98a92af\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/bitflags/2.11.0/download\"],\n        strip_prefix = \"bitflags-2.11.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.bitflags-2.11.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__block-buffer-0.10.4\",\n        sha256 = \"3078c7629b62d3f0439517fa394996acacc5cbc91c5a20d8c658e77abd503a71\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/block-buffer/0.10.4/download\"],\n        strip_prefix = \"block-buffer-0.10.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.block-buffer-0.10.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__byteorder-1.5.0\",\n        sha256 = \"1fd0f2584146f6f2ef48085050886acf353beff7305ebd1ae69500e27c67f64b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/byteorder/1.5.0/download\"],\n        strip_prefix = \"byteorder-1.5.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.byteorder-1.5.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__cfg-if-1.0.4\",\n        sha256 = \"9330f8b2ff13f34540b44e946ef35111825727b38d33286ef986142615121801\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/cfg-if/1.0.4/download\"],\n        strip_prefix = \"cfg-if-1.0.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.cfg-if-1.0.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__cipher-0.4.4\",\n        sha256 = \"773f3b9af64447d2ce9850330c473515014aa235e6a783b02db81ff39e4a3dad\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/cipher/0.4.4/download\"],\n        strip_prefix = \"cipher-0.4.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.cipher-0.4.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__clap-4.5.60\",\n        sha256 = \"2797f34da339ce31042b27d23607e051786132987f595b02ba4f6a6dffb7030a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/clap/4.5.60/download\"],\n        strip_prefix = \"clap-4.5.60\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.clap-4.5.60.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__clap_builder-4.5.60\",\n        sha256 = \"24a241312cea5059b13574bb9b3861cabf758b879c15190b37b6d6fd63ab6876\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/clap_builder/4.5.60/download\"],\n        strip_prefix = \"clap_builder-4.5.60\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.clap_builder-4.5.60.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__clap_derive-4.5.55\",\n        sha256 = \"a92793da1a46a5f2a02a6f4c46c6496b28c43638adea8306fcb0caa1634f24e5\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/clap_derive/4.5.55/download\"],\n        strip_prefix = \"clap_derive-4.5.55\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.clap_derive-4.5.55.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__clap_lex-1.0.0\",\n        sha256 = \"3a822ea5bc7590f9d40f1ba12c0dc3c2760f3482c6984db1573ad11031420831\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/clap_lex/1.0.0/download\"],\n        strip_prefix = \"clap_lex-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.clap_lex-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__colorchoice-1.0.4\",\n        sha256 = \"b05b61dc5112cbb17e4b6cd61790d9845d13888356391624cbe7e41efeac1e75\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/colorchoice/1.0.4/download\"],\n        strip_prefix = \"colorchoice-1.0.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.colorchoice-1.0.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__compiler_builtins-0.1.160\",\n        sha256 = \"6376049cfa92c0aa8b9ac95fae22184b981c658208d4ed8a1dc553cd83612895\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/compiler_builtins/0.1.160/download\"],\n        strip_prefix = \"compiler_builtins-0.1.160\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.compiler_builtins-0.1.160.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__const-oid-0.9.6\",\n        sha256 = \"c2459377285ad874054d797f3ccebf984978aa39129f6eafde5cdc8315b612f8\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/const-oid/0.9.6/download\"],\n        strip_prefix = \"const-oid-0.9.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.const-oid-0.9.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__cortex-m-0.7.7\",\n        sha256 = \"8ec610d8f49840a5b376c69663b6369e71f4b34484b9b2eb29fb918d92516cb9\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/cortex-m/0.7.7/download\"],\n        strip_prefix = \"cortex-m-0.7.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.cortex-m-0.7.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__cpufeatures-0.2.17\",\n        sha256 = \"59ed5838eebb26a2bb2e58f6d5b5316989ae9d08bab10e0e6d103e656d1b0280\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/cpufeatures/0.2.17/download\"],\n        strip_prefix = \"cpufeatures-0.2.17\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.cpufeatures-0.2.17.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__crc32fast-1.5.0\",\n        sha256 = \"9481c1c90cbf2ac953f07c8d4a58aa3945c425b7185c9154d67a65e4230da511\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/crc32fast/1.5.0/download\"],\n        strip_prefix = \"crc32fast-1.5.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.crc32fast-1.5.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__critical-section-1.2.0\",\n        sha256 = \"790eea4361631c5e7d22598ecd5723ff611904e3344ce8720784c93e3d83d40b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/critical-section/1.2.0/download\"],\n        strip_prefix = \"critical-section-1.2.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.critical-section-1.2.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__crypto-bigint-0.5.5\",\n        sha256 = \"0dc92fb57ca44df6db8059111ab3af99a63d5d0f8375d9972e319a379c6bab76\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/crypto-bigint/0.5.5/download\"],\n        strip_prefix = \"crypto-bigint-0.5.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.crypto-bigint-0.5.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__crypto-common-0.1.7\",\n        sha256 = \"78c8292055d1c1df0cce5d180393dc8cce0abec0a7102adb6c7b1eef6016d60a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/crypto-common/0.1.7/download\"],\n        strip_prefix = \"crypto-common-0.1.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.crypto-common-0.1.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ctr-0.9.2\",\n        sha256 = \"0369ee1ad671834580515889b80f2ea915f23b8be8d0daa4bbaf2ac5c7590835\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ctr/0.9.2/download\"],\n        strip_prefix = \"ctr-0.9.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ctr-0.9.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__der-0.7.10\",\n        sha256 = \"e7c1832837b905bbfb5101e07cc24c8deddf52f93225eee6ead5f4d63d53ddcb\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/der/0.7.10/download\"],\n        strip_prefix = \"der-0.7.10\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.der-0.7.10.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__digest-0.10.7\",\n        sha256 = \"9ed9a281f7bc9b7576e61468ba615a66a5c8cfdff42420a70aa82701a3b1e292\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/digest/0.10.7/download\"],\n        strip_prefix = \"digest-0.10.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.digest-0.10.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ecdsa-0.16.9\",\n        sha256 = \"ee27f32b5c5292967d2d4a9d7f1e0b0aed2c15daded5a60300e4abb9d8020bca\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ecdsa/0.16.9/download\"],\n        strip_prefix = \"ecdsa-0.16.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ecdsa-0.16.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__elliptic-curve-0.13.8\",\n        sha256 = \"b5e6043086bf7973472e0c7dff2142ea0b680d30e18d9cc40f267efbf222bd47\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/elliptic-curve/0.13.8/download\"],\n        strip_prefix = \"elliptic-curve-0.13.8\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.elliptic-curve-0.13.8.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-hal-0.2.7\",\n        sha256 = \"35949884794ad573cf46071e41c9b60efb0cb311e3ca01f7af807af1debc66ff\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-hal/0.2.7/download\"],\n        strip_prefix = \"embedded-hal-0.2.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-hal-0.2.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-hal-1.0.0\",\n        sha256 = \"361a90feb7004eca4019fb28352a9465666b24f840f5c3cddf0ff13920590b89\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-hal/1.0.0/download\"],\n        strip_prefix = \"embedded-hal-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-hal-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-hal-async-1.0.0\",\n        sha256 = \"0c4c685bbef7fe13c3c6dd4da26841ed3980ef33e841cddfa15ce8a8fb3f1884\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-hal-async/1.0.0/download\"],\n        strip_prefix = \"embedded-hal-async-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-hal-async-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-hal-nb-1.0.0\",\n        sha256 = \"fba4268c14288c828995299e59b12babdbe170f6c6d73731af1b4648142e8605\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-hal-nb/1.0.0/download\"],\n        strip_prefix = \"embedded-hal-nb-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-hal-nb-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-io-0.6.1\",\n        sha256 = \"edd0f118536f44f5ccd48bcb8b111bdc3de888b58c74639dfb034a357d0f206d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-io/0.6.1/download\"],\n        strip_prefix = \"embedded-io-0.6.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-io-0.6.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__equivalent-1.0.2\",\n        sha256 = \"877a4ace8713b0bcf2a4e7eec82529c029f1d0619886d18145fea96c3ffe5c0f\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/equivalent/1.0.2/download\"],\n        strip_prefix = \"equivalent-1.0.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.equivalent-1.0.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ff-0.13.1\",\n        sha256 = \"c0b50bfb653653f9ca9095b427bed08ab8d75a137839d9ad64eb11810d5b6393\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ff/0.13.1/download\"],\n        strip_prefix = \"ff-0.13.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ff-0.13.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__flate2-1.1.9\",\n        sha256 = \"843fba2746e448b37e26a819579957415c8cef339bf08564fe8b7ddbd959573c\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/flate2/1.1.9/download\"],\n        strip_prefix = \"flate2-1.1.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.flate2-1.1.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__foldhash-0.1.5\",\n        sha256 = \"d9c4f5dac5e15c24eb999c26181a6ca40b39fe946cbe4c263c7209467bc83af2\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/foldhash/0.1.5/download\"],\n        strip_prefix = \"foldhash-0.1.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.foldhash-0.1.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__generic-array-0.14.7\",\n        sha256 = \"85649ca51fd72272d7821adaf274ad91c288277713d9c18820d8499a7ff69e9a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/generic-array/0.14.7/download\"],\n        strip_prefix = \"generic-array-0.14.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.generic-array-0.14.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ghash-0.5.1\",\n        sha256 = \"f0d8a4362ccb29cb0b265253fb0a2728f592895ee6854fd9bc13f2ffda266ff1\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ghash/0.5.1/download\"],\n        strip_prefix = \"ghash-0.5.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ghash-0.5.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__group-0.13.0\",\n        sha256 = \"f0f9ef7462f7c099f518d754361858f86d8a07af53ba9af0fe635bbccb151a63\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/group/0.13.0/download\"],\n        strip_prefix = \"group-0.13.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.group-0.13.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__hash32-0.3.1\",\n        sha256 = \"47d60b12902ba28e2730cd37e95b8c9223af2808df9e902d4df49588d1470606\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/hash32/0.3.1/download\"],\n        strip_prefix = \"hash32-0.3.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.hash32-0.3.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__hashbrown-0.15.5\",\n        sha256 = \"9229cfe53dfd69f0609a49f65461bd93001ea1ef889cd5529dd176593f5338a1\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/hashbrown/0.15.5/download\"],\n        strip_prefix = \"hashbrown-0.15.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.hashbrown-0.15.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__hashbrown-0.16.1\",\n        sha256 = \"841d1cc9bed7f9236f321df977030373f4a4163ae1a7dbfe1a51a2c1a51d9100\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/hashbrown/0.16.1/download\"],\n        strip_prefix = \"hashbrown-0.16.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.hashbrown-0.16.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__hashlink-0.10.0\",\n        sha256 = \"7382cf6263419f2d8df38c55d7da83da5c18aef87fc7a7fc1fb1e344edfe14c1\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/hashlink/0.10.0/download\"],\n        strip_prefix = \"hashlink-0.10.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.hashlink-0.10.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__heapless-0.9.2\",\n        sha256 = \"2af2455f757db2b292a9b1768c4b70186d443bcb3b316252d6b540aec1cd89ed\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/heapless/0.9.2/download\"],\n        strip_prefix = \"heapless-0.9.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.heapless-0.9.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__heck-0.5.0\",\n        sha256 = \"2304e00983f87ffb38b55b444b5e3b60a884b5d30c0fca7d82fe33449bbe55ea\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/heck/0.5.0/download\"],\n        strip_prefix = \"heck-0.5.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.heck-0.5.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__hmac-0.12.1\",\n        sha256 = \"6c49c37c09c17a53d937dfbb742eb3a961d65a994e6bcdcf37e7399d0cc8ab5e\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/hmac/0.12.1/download\"],\n        strip_prefix = \"hmac-0.12.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.hmac-0.12.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__indexmap-2.13.0\",\n        sha256 = \"7714e70437a7dc3ac8eb7e6f8df75fd8eb422675fc7678aff7364301092b1017\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/indexmap/2.13.0/download\"],\n        strip_prefix = \"indexmap-2.13.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.indexmap-2.13.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__inout-0.1.4\",\n        sha256 = \"879f10e63c20629ecabbb64a8010319738c66a5cd0c29b02d63d272b03751d01\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/inout/0.1.4/download\"],\n        strip_prefix = \"inout-0.1.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.inout-0.1.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__is_terminal_polyfill-1.70.2\",\n        sha256 = \"a6cb138bb79a146c1bd460005623e142ef0181e3d0219cb493e02f7d08a35695\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/is_terminal_polyfill/1.70.2/download\"],\n        strip_prefix = \"is_terminal_polyfill-1.70.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.is_terminal_polyfill-1.70.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__k256-0.13.4\",\n        sha256 = \"f6e3919bbaa2945715f0bb6d3934a173d1e9a59ac23767fbaaef277265a7411b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/k256/0.13.4/download\"],\n        strip_prefix = \"k256-0.13.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.k256-0.13.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__keccak-0.1.6\",\n        sha256 = \"cb26cec98cce3a3d96cbb7bced3c4b16e3d13f27ec56dbd62cbc8f39cfb9d653\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/keccak/0.1.6/download\"],\n        strip_prefix = \"keccak-0.1.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.keccak-0.1.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__libc-0.2.182\",\n        sha256 = \"6800badb6cb2082ffd7b6a67e6125bb39f18782f793520caee8cb8846be06112\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/libc/0.2.182/download\"],\n        strip_prefix = \"libc-0.2.182\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.libc-0.2.182.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__memchr-2.8.0\",\n        sha256 = \"f8ca58f447f06ed17d5fc4043ce1b10dd205e060fb3ce5b979b8ed8e59ff3f79\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/memchr/2.8.0/download\"],\n        strip_prefix = \"memchr-2.8.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.memchr-2.8.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__memo-map-0.3.3\",\n        sha256 = \"38d1115007560874e373613744c6fba374c17688327a71c1476d1a5954cc857b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/memo-map/0.3.3/download\"],\n        strip_prefix = \"memo-map-0.3.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.memo-map-0.3.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__minijinja-2.16.0\",\n        sha256 = \"5c54f3bcc034dd74496b5ca929fd0b710186672d5ff0b0f255a9ceb259042ece\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/minijinja/2.16.0/download\"],\n        strip_prefix = \"minijinja-2.16.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.minijinja-2.16.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__minimal-lexical-0.2.1\",\n        sha256 = \"68354c5c6bd36d73ff3feceb05efa59b6acb7626617f4962be322a825e61f79a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/minimal-lexical/0.2.1/download\"],\n        strip_prefix = \"minimal-lexical-0.2.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.minimal-lexical-0.2.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__miniz_oxide-0.8.9\",\n        sha256 = \"1fa76a2c86f704bdb222d66965fb3d63269ce38518b83cb0575fca855ebb6316\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/miniz_oxide/0.8.9/download\"],\n        strip_prefix = \"miniz_oxide-0.8.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.miniz_oxide-0.8.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__nb-0.1.3\",\n        sha256 = \"801d31da0513b6ec5214e9bf433a77966320625a37860f910be265be6e18d06f\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/nb/0.1.3/download\"],\n        strip_prefix = \"nb-0.1.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.nb-0.1.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__nb-1.1.0\",\n        sha256 = \"8d5439c4ad607c3c23abf66de8c8bf57ba8adcd1f129e699851a6e43935d339d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/nb/1.1.0/download\"],\n        strip_prefix = \"nb-1.1.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.nb-1.1.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__nom-7.1.3\",\n        sha256 = \"d273983c5a657a70a3e8f2a01329822f3b8c8172b73826411a55751e404a0a4a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/nom/7.1.3/download\"],\n        strip_prefix = \"nom-7.1.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.nom-7.1.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__object-0.37.3\",\n        sha256 = \"ff76201f031d8863c38aa7f905eca4f53abbfa15f609db4277d44cd8938f33fe\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/object/0.37.3/download\"],\n        strip_prefix = \"object-0.37.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.object-0.37.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__once_cell_polyfill-1.70.2\",\n        sha256 = \"384b8ab6d37215f3c5301a95a4accb5d64aa607f1fcb26a11b5303878451b4fe\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/once_cell_polyfill/1.70.2/download\"],\n        strip_prefix = \"once_cell_polyfill-1.70.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.once_cell_polyfill-1.70.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__opaque-debug-0.3.1\",\n        sha256 = \"c08d65885ee38876c4f86fa503fb49d7b507c2b62552df7c70b2fce627e06381\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/opaque-debug/0.3.1/download\"],\n        strip_prefix = \"opaque-debug-0.3.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.opaque-debug-0.3.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__p256-0.13.2\",\n        sha256 = \"c9863ad85fa8f4460f9c48cb909d38a0d689dba1f6f6988a5e3e0d31071bcd4b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/p256/0.13.2/download\"],\n        strip_prefix = \"p256-0.13.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.p256-0.13.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__p384-0.13.1\",\n        sha256 = \"fe42f1670a52a47d448f14b6a5c61dd78fce51856e68edaa38f7ae3a46b8d6b6\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/p384/0.13.1/download\"],\n        strip_prefix = \"p384-0.13.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.p384-0.13.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__panic-halt-1.0.0\",\n        sha256 = \"a513e167849a384b7f9b746e517604398518590a9142f4846a32e3c2a4de7b11\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/panic-halt/1.0.0/download\"],\n        strip_prefix = \"panic-halt-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.panic-halt-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__paste-1.0.15\",\n        sha256 = \"57c0d7b74b563b49d38dae00a0c37d4d6de9b432382b2892f0574ddcae73fd0a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/paste/1.0.15/download\"],\n        strip_prefix = \"paste-1.0.15\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.paste-1.0.15.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__pest-2.8.6\",\n        sha256 = \"e0848c601009d37dfa3430c4666e147e49cdcf1b92ecd3e63657d8a5f19da662\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/pest/2.8.6/download\"],\n        strip_prefix = \"pest-2.8.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.pest-2.8.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__pest_derive-2.8.6\",\n        sha256 = \"11f486f1ea21e6c10ed15d5a7c77165d0ee443402f0780849d1768e7d9d6fe77\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/pest_derive/2.8.6/download\"],\n        strip_prefix = \"pest_derive-2.8.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.pest_derive-2.8.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__pest_generator-2.8.6\",\n        sha256 = \"8040c4647b13b210a963c1ed407c1ff4fdfa01c31d6d2a098218702e6664f94f\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/pest_generator/2.8.6/download\"],\n        strip_prefix = \"pest_generator-2.8.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.pest_generator-2.8.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__pest_meta-2.8.6\",\n        sha256 = \"89815c69d36021a140146f26659a81d6c2afa33d216d736dd4be5381a7362220\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/pest_meta/2.8.6/download\"],\n        strip_prefix = \"pest_meta-2.8.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.pest_meta-2.8.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__polyval-0.6.2\",\n        sha256 = \"9d1fe60d06143b2430aa532c94cfe9e29783047f06c0d7fd359a9a51b729fa25\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/polyval/0.6.2/download\"],\n        strip_prefix = \"polyval-0.6.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.polyval-0.6.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__primeorder-0.13.6\",\n        sha256 = \"353e1ca18966c16d9deb1c69278edbc5f194139612772bd9537af60ac231e1e6\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/primeorder/0.13.6/download\"],\n        strip_prefix = \"primeorder-0.13.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.primeorder-0.13.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__proc-macro2-1.0.106\",\n        sha256 = \"8fd00f0bb2e90d81d1044c2b32617f68fcb9fa3bb7640c23e9c748e53fb30934\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/proc-macro2/1.0.106/download\"],\n        strip_prefix = \"proc-macro2-1.0.106\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.proc-macro2-1.0.106.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__quote-1.0.44\",\n        sha256 = \"21b2ebcf727b7760c461f091f9f0f539b77b8e87f2fd88131e7f1b433b3cece4\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/quote/1.0.44/download\"],\n        strip_prefix = \"quote-1.0.44\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.quote-1.0.44.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__rand_core-0.6.4\",\n        sha256 = \"ec0be4795e2f6a28069bec0b5ff3e2ac9bafc99e6a9a7dc3547996c5c816922c\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/rand_core/0.6.4/download\"],\n        strip_prefix = \"rand_core-0.6.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.rand_core-0.6.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__rand_core-0.9.5\",\n        sha256 = \"76afc826de14238e6e8c374ddcc1fa19e374fd8dd986b0d2af0d02377261d83c\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/rand_core/0.9.5/download\"],\n        strip_prefix = \"rand_core-0.9.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.rand_core-0.9.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__rfc6979-0.4.0\",\n        sha256 = \"f8dd2a808d456c4a54e300a23e9f5a67e122c3024119acbfd73e3bf664491cb2\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/rfc6979/0.4.0/download\"],\n        strip_prefix = \"rfc6979-0.4.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.rfc6979-0.4.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-0.11.1\",\n        sha256 = \"2f5c1b8bf41ea746266cdee443d1d1e9125c86ce1447e1a2615abd34330d33a9\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv/0.11.1/download\"],\n        strip_prefix = \"riscv-0.11.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-0.11.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-0.12.1\",\n        sha256 = \"5ea8ff73d3720bdd0a97925f0bf79ad2744b6da8ff36be3840c48ac81191d7a7\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv/0.12.1/download\"],\n        strip_prefix = \"riscv-0.12.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-0.12.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-0.13.0\",\n        sha256 = \"afa3cdbeccae4359f6839a00e8b77e5736caa200ba216caf38d24e4c16e2b586\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv/0.13.0/download\"],\n        strip_prefix = \"riscv-0.13.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-0.13.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-macros-0.1.0\",\n        sha256 = \"f265be5d634272320a7de94cea15c22a3bfdd4eb42eb43edc528415f066a1f25\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-macros/0.1.0/download\"],\n        strip_prefix = \"riscv-macros-0.1.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-macros-0.1.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-macros-0.2.0\",\n        sha256 = \"e8c4aa1ea1af6dcc83a61be12e8189f9b293c3ba5a487778a4cd89fb060fdbbc\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-macros/0.2.0/download\"],\n        strip_prefix = \"riscv-macros-0.2.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-macros-0.2.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-pac-0.2.0\",\n        sha256 = \"8188909339ccc0c68cfb5a04648313f09621e8b87dc03095454f1a11f6c5d436\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-pac/0.2.0/download\"],\n        strip_prefix = \"riscv-pac-0.2.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-pac-0.2.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-rt-0.12.2\",\n        sha256 = \"c0d35e32cf1383183e8885d8a9aa4402a087fd094dc34c2cb6df6687d0229dfe\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-rt/0.12.2/download\"],\n        strip_prefix = \"riscv-rt-0.12.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-rt-0.12.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-rt-macros-0.2.2\",\n        sha256 = \"30f19a85fe107b65031e0ba8ec60c34c2494069fe910d6c297f5e7cb5a6f76d0\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-rt-macros/0.2.2/download\"],\n        strip_prefix = \"riscv-rt-macros-0.2.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-rt-macros-0.2.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-semihosting-0.1.3\",\n        sha256 = \"1086dd4bcc13de1cb14b93849411e3466de7e5907d2d8eb269032536e93facc6\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-semihosting/0.1.3/download\"],\n        strip_prefix = \"riscv-semihosting-0.1.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-semihosting-0.1.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__rustc-demangle-0.1.27\",\n        sha256 = \"b50b8869d9fc858ce7266cce0194bd74df58b9d0e3f6df3a9fc8eb470d95c09d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/rustc-demangle/0.1.27/download\"],\n        strip_prefix = \"rustc-demangle-0.1.27\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.rustc-demangle-0.1.27.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__rustc_version-0.2.3\",\n        sha256 = \"138e3e0acb6c9fb258b19b67cb8abd63c00679d2851805ea151465464fe9030a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/rustc_version/0.2.3/download\"],\n        strip_prefix = \"rustc_version-0.2.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.rustc_version-0.2.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ruzstd-0.8.2\",\n        sha256 = \"e5ff0cc5e135c8870a775d3320910cd9b564ec036b4dc0b8741629020be63f01\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ruzstd/0.8.2/download\"],\n        strip_prefix = \"ruzstd-0.8.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ruzstd-0.8.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__sec1-0.7.3\",\n        sha256 = \"d3e97a565f76233a6003f9f5c54be1d9c5bdfa3eccfb189469f11ec4901c47dc\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/sec1/0.7.3/download\"],\n        strip_prefix = \"sec1-0.7.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.sec1-0.7.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__self_cell-1.2.2\",\n        sha256 = \"b12e76d157a900eb52e81bc6e9f3069344290341720e9178cde2407113ac8d89\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/self_cell/1.2.2/download\"],\n     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\"d540f220d3187173da220f885ab66608367b6574e925011a9353e4badda91d79\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/serde_derive/1.0.228/download\"],\n        strip_prefix = \"serde_derive-1.0.228\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.serde_derive-1.0.228.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__serde_json5-0.2.1\",\n        sha256 = \"5d34d03f54462862f2a42918391c9526337f53171eaa4d8894562be7f252edd3\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/serde_json5/0.2.1/download\"],\n        strip_prefix = \"serde_json5-0.2.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.serde_json5-0.2.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__serde_spanned-0.6.9\",\n        sha256 = \"bf41e0cfaf7226dca15e8197172c295a782857fcb97fad1808a166870dee75a3\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/serde_spanned/0.6.9/download\"],\n        strip_prefix = \"serde_spanned-0.6.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.serde_spanned-0.6.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__sha2-0.10.9\",\n        sha256 = \"a7507d819769d01a365ab707794a4084392c824f54a7a6a7862f8c3d0892b283\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/sha2/0.10.9/download\"],\n        strip_prefix = \"sha2-0.10.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.sha2-0.10.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__sha3-0.10.8\",\n        sha256 = \"75872d278a8f37ef87fa0ddbda7802605cb18344497949862c0d4dcb291eba60\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/sha3/0.10.8/download\"],\n        strip_prefix = \"sha3-0.10.8\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.sha3-0.10.8.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__signature-2.2.0\",\n        sha256 = \"77549399552de45a898a580c1b41d445bf730df867cc44e6c0233bbc4b8329de\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/signature/2.2.0/download\"],\n        strip_prefix = \"signature-2.2.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.signature-2.2.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__simd-adler32-0.3.8\",\n        sha256 = \"e320a6c5ad31d271ad523dcf3ad13e2767ad8b1cb8f047f75a8aeaf8da139da2\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/simd-adler32/0.3.8/download\"],\n        strip_prefix = \"simd-adler32-0.3.8\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.simd-adler32-0.3.8.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__stable_deref_trait-1.2.1\",\n        sha256 = \"6ce2be8dc25455e1f91df71bfa12ad37d7af1092ae736f3a6cd0e37bc7810596\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/stable_deref_trait/1.2.1/download\"],\n        strip_prefix = \"stable_deref_trait-1.2.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.stable_deref_trait-1.2.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__strsim-0.11.1\",\n        sha256 = \"7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/strsim/0.11.1/download\"],\n        strip_prefix = \"strsim-0.11.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.strsim-0.11.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__subtle-2.6.1\",\n        sha256 = \"13c2bddecc57b384dee18652358fb23172facb8a2c51ccc10d74c157bdea3292\",\n       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Label(\"@rust_crates//rust_crates:BUILD.toml-0.8.23.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__toml_datetime-0.6.11\",\n        sha256 = \"22cddaf88f4fbc13c51aebbf5f8eceb5c7c5a9da2ac40a13519eb5b0a0e8f11c\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/toml_datetime/0.6.11/download\"],\n        strip_prefix = \"toml_datetime-0.6.11\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.toml_datetime-0.6.11.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__toml_edit-0.22.27\",\n        sha256 = \"41fe8c660ae4257887cf66394862d21dbca4a6ddd26f04a3560410406a2f819a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/toml_edit/0.22.27/download\"],\n        strip_prefix = \"toml_edit-0.22.27\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.toml_edit-0.22.27.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = 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Label(\"@rust_crates//rust_crates:BUILD.unicode-ident-1.0.24.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__universal-hash-0.5.1\",\n        sha256 = \"fc1de2c688dc15305988b563c3854064043356019f97a4b46276fe734c4f07ea\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/universal-hash/0.5.1/download\"],\n        strip_prefix = \"universal-hash-0.5.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.universal-hash-0.5.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__utf8parse-0.2.2\",\n        sha256 = \"06abde3611657adf66d383f00b093d7faecc7fa57071cce2578660c9f1010821\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/utf8parse/0.2.2/download\"],\n        strip_prefix = \"utf8parse-0.2.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.utf8parse-0.2.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = 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urls = [\"https://static.crates.io/crates/void/1.0.2/download\"],\n        strip_prefix = \"void-1.0.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.void-1.0.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__volatile-register-0.2.2\",\n        sha256 = \"de437e2a6208b014ab52972a27e59b33fa2920d3e00fe05026167a1c509d19cc\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/volatile-register/0.2.2/download\"],\n        strip_prefix = \"volatile-register-0.2.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.volatile-register-0.2.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__windows-link-0.2.1\",\n        sha256 = \"f0805222e57f7521d6a62e36fa9163bc891acd422f971defe97d64e70d0a4fe5\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/windows-link/0.2.1/download\"],\n        strip_prefix = \"windows-link-0.2.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.windows-link-0.2.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__windows-sys-0.61.2\",\n        sha256 = \"ae137229bcbd6cdf0f7b80a31df61766145077ddf49416a728b02cb3921ff3fc\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/windows-sys/0.61.2/download\"],\n        strip_prefix = \"windows-sys-0.61.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.windows-sys-0.61.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__winnow-0.7.14\",\n        sha256 = \"5a5364e9d77fcdeeaa6062ced926ee3381faa2ee02d3eb83a5c27a8825540829\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/winnow/0.7.14/download\"],\n        strip_prefix = \"winnow-0.7.14\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.winnow-0.7.14.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__zerocopy-0.8.39\",\n        sha256 = \"db6d35d663eadb6c932438e763b262fe1a70987f9ae936e60158176d710cae4a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/zerocopy/0.8.39/download\"],\n        strip_prefix = \"zerocopy-0.8.39\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.zerocopy-0.8.39.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__zerocopy-derive-0.8.39\",\n        sha256 = \"4122cd3169e94605190e77839c9a40d40ed048d305bfdc146e7df40ab0f3e517\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/zerocopy-derive/0.8.39/download\"],\n        strip_prefix = \"zerocopy-derive-0.8.39\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.zerocopy-derive-0.8.39.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__zeroize-1.8.2\",\n        sha256 = \"b97154e67e32c85465826e8bcc1c59429aaaf107c1e4a9e53c8d8ccd5eff88d0\",\n      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struct(repo=\"rust_crates__bitflags-2.11.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__byteorder-1.5.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__cipher-0.4.4\", is_dev_dep = False),\n       struct(repo=\"rust_crates__clap-4.5.60\", is_dev_dep = False),\n       struct(repo=\"rust_crates__compiler_builtins-0.1.160\", is_dev_dep = False),\n       struct(repo=\"rust_crates__cortex-m-0.7.7\", is_dev_dep = False),\n       struct(repo=\"rust_crates__ctr-0.9.2\", is_dev_dep = False),\n       struct(repo=\"rust_crates__embedded-hal-1.0.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__embedded-hal-async-1.0.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__embedded-hal-nb-1.0.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__embedded-io-0.6.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__hashlink-0.10.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__heapless-0.9.2\", is_dev_dep = False),\n       struct(repo=\"rust_crates__hmac-0.12.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__k256-0.13.4\", is_dev_dep = False),\n       struct(repo=\"rust_crates__minijinja-2.16.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__nb-1.1.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__nom-7.1.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__object-0.37.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__p256-0.13.2\", is_dev_dep = False),\n       struct(repo=\"rust_crates__p384-0.13.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__panic-halt-1.0.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__paste-1.0.15\", is_dev_dep = False),\n       struct(repo=\"rust_crates__proc-macro2-1.0.106\", is_dev_dep = False),\n       struct(repo=\"rust_crates__quote-1.0.44\", is_dev_dep = False),\n       struct(repo=\"rust_crates__rand_core-0.9.5\", is_dev_dep = False),\n       struct(repo=\"rust_crates__riscv-0.12.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__riscv-rt-0.12.2\", is_dev_dep = False),\n       struct(repo=\"rust_crates__riscv-semihosting-0.1.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__rustc-demangle-0.1.27\", is_dev_dep = False),\n       struct(repo=\"rust_crates__serde-1.0.228\", is_dev_dep = False),\n       struct(repo=\"rust_crates__serde_json5-0.2.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__sha2-0.10.9\", is_dev_dep = False),\n       struct(repo=\"rust_crates__sha3-0.10.8\", is_dev_dep = False),\n       struct(repo=\"rust_crates__subtle-2.6.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__syn-2.0.116\", is_dev_dep = False),\n       struct(repo=\"rust_crates__toml-0.8.23\", is_dev_dep = False),\n       struct(repo=\"rust_crates__zerocopy-0.8.39\", is_dev_dep = False),\n       struct(repo=\"rust_crates__zeroize-1.8.2\", is_dev_dep = False),\n    ]\n"
+                "defs.bzl": "###############################################################################\n# @generated\n# DO NOT MODIFY: This file is auto-generated by a crate_universe tool. To \n# regenerate this file, run the following:\n#\n#     bazel mod show_repo 'openprot'\n###############################################################################\n\"\"\"\n# `crates_repository` API\n\n- [aliases](#aliases)\n- [crate_deps](#crate_deps)\n- [all_crate_deps](#all_crate_deps)\n- [crate_repositories](#crate_repositories)\n\n\"\"\"\n\nload(\"@bazel_tools//tools/build_defs/repo:git.bzl\", \"new_git_repository\")\nload(\"@bazel_tools//tools/build_defs/repo:http.bzl\", \"http_archive\")\nload(\"@bazel_tools//tools/build_defs/repo:utils.bzl\", \"maybe\")\nload(\"@bazel_skylib//lib:selects.bzl\", \"selects\")\nload(\"@rules_rust//crate_universe/private:local_crate_mirror.bzl\", \"local_crate_mirror\")\n\n###############################################################################\n# MACROS API\n###############################################################################\n\n# An identifier that represent common dependencies (unconditional).\n_COMMON_CONDITION = \"\"\n\ndef _flatten_dependency_maps(all_dependency_maps):\n    \"\"\"Flatten a list of dependency maps into one dictionary.\n\n    Dependency maps have the following structure:\n\n    ```python\n    DEPENDENCIES_MAP = {\n        # The first key in the map is a Bazel package\n        # name of the workspace this file is defined in.\n        \"workspace_member_package\": {\n\n            # Not all dependencies are supported for all platforms.\n            # the condition key is the condition required to be true\n            # on the host platform.\n            \"condition\": {\n\n                # An alias to a crate target.     # The label of the crate target the\n                # Aliases are only crate names.   # package name refers to.\n                \"package_name\":                   \"@full//:label\",\n            }\n        }\n    }\n    ```\n\n    Args:\n        all_dependency_maps (list): A list of dicts as described above\n\n    Returns:\n        dict: A dictionary as described above\n    \"\"\"\n    dependencies = {}\n\n    for workspace_deps_map in all_dependency_maps:\n        for pkg_name, conditional_deps_map in workspace_deps_map.items():\n            if pkg_name not in dependencies:\n                non_frozen_map = dict()\n                for key, values in conditional_deps_map.items():\n                    non_frozen_map.update({key: dict(values.items())})\n                dependencies.setdefault(pkg_name, non_frozen_map)\n                continue\n\n            for condition, deps_map in conditional_deps_map.items():\n                # If the condition has not been recorded, do so and continue\n                if condition not in dependencies[pkg_name]:\n                    dependencies[pkg_name].setdefault(condition, dict(deps_map.items()))\n                    continue\n\n                # Alert on any miss-matched dependencies\n                inconsistent_entries = []\n                for crate_name, crate_label in deps_map.items():\n                    existing = dependencies[pkg_name][condition].get(crate_name)\n                    if existing and existing != crate_label:\n                        inconsistent_entries.append((crate_name, existing, crate_label))\n                    dependencies[pkg_name][condition].update({crate_name: crate_label})\n\n    return dependencies\n\ndef crate_deps(deps, package_name = None):\n    \"\"\"Finds the fully qualified label of the requested crates for the package where this macro is called.\n\n    Args:\n        deps (list): The desired list of crate targets.\n        package_name (str, optional): The package name of the set of dependencies to look up.\n            Defaults to `native.package_name()`.\n\n    Returns:\n        list: A list of labels to generated rust targets (str)\n    \"\"\"\n\n    if not deps:\n        return []\n\n    if package_name == None:\n        package_name = native.package_name()\n\n    # Join both sets of dependencies\n    dependencies = _flatten_dependency_maps([\n        _NORMAL_DEPENDENCIES,\n        _NORMAL_DEV_DEPENDENCIES,\n        _PROC_MACRO_DEPENDENCIES,\n        _PROC_MACRO_DEV_DEPENDENCIES,\n        _BUILD_DEPENDENCIES,\n        _BUILD_PROC_MACRO_DEPENDENCIES,\n    ]).pop(package_name, {})\n\n    # Combine all conditional packages so we can easily index over a flat list\n    # TODO: Perhaps this should actually return select statements and maintain\n    # the conditionals of the dependencies\n    flat_deps = {}\n    for deps_set in dependencies.values():\n        for crate_name, crate_label in deps_set.items():\n            flat_deps.update({crate_name: crate_label})\n\n    missing_crates = []\n    crate_targets = []\n    for crate_target in deps:\n        if crate_target not in flat_deps:\n            missing_crates.append(crate_target)\n        else:\n            crate_targets.append(flat_deps[crate_target])\n\n    if missing_crates:\n        fail(\"Could not find crates `{}` among dependencies of `{}`. Available dependencies were `{}`\".format(\n            missing_crates,\n            package_name,\n            dependencies,\n        ))\n\n    return crate_targets\n\ndef all_crate_deps(\n        normal = False, \n        normal_dev = False, \n        proc_macro = False, \n        proc_macro_dev = False,\n        build = False,\n        build_proc_macro = False,\n        package_name = None):\n    \"\"\"Finds the fully qualified label of all requested direct crate dependencies \\\n    for the package where this macro is called.\n\n    If no parameters are set, all normal dependencies are returned. Setting any one flag will\n    otherwise impact the contents of the returned list.\n\n    Args:\n        normal (bool, optional): If True, normal dependencies are included in the\n            output list.\n        normal_dev (bool, optional): If True, normal dev dependencies will be\n            included in the output list..\n        proc_macro (bool, optional): If True, proc_macro dependencies are included\n            in the output list.\n        proc_macro_dev (bool, optional): If True, dev proc_macro dependencies are\n            included in the output list.\n        build (bool, optional): If True, build dependencies are included\n            in the output list.\n        build_proc_macro (bool, optional): If True, build proc_macro dependencies are\n            included in the output list.\n        package_name (str, optional): The package name of the set of dependencies to look up.\n            Defaults to `native.package_name()` when unset.\n\n    Returns:\n        list: A list of labels to generated rust targets (str)\n    \"\"\"\n\n    if package_name == None:\n        package_name = native.package_name()\n\n    # Determine the relevant maps to use\n    all_dependency_maps = []\n    if normal:\n        all_dependency_maps.append(_NORMAL_DEPENDENCIES)\n    if normal_dev:\n        all_dependency_maps.append(_NORMAL_DEV_DEPENDENCIES)\n    if proc_macro:\n        all_dependency_maps.append(_PROC_MACRO_DEPENDENCIES)\n    if proc_macro_dev:\n        all_dependency_maps.append(_PROC_MACRO_DEV_DEPENDENCIES)\n    if build:\n        all_dependency_maps.append(_BUILD_DEPENDENCIES)\n    if build_proc_macro:\n        all_dependency_maps.append(_BUILD_PROC_MACRO_DEPENDENCIES)\n\n    # Default to always using normal dependencies\n    if not all_dependency_maps:\n        all_dependency_maps.append(_NORMAL_DEPENDENCIES)\n\n    dependencies = _flatten_dependency_maps(all_dependency_maps).pop(package_name, None)\n\n    if not dependencies:\n        if dependencies == None:\n            fail(\"Tried to get all_crate_deps for package \" + package_name + \" but that package had no Cargo.toml file\")\n        else:\n            return []\n\n    crate_deps = list(dependencies.pop(_COMMON_CONDITION, {}).values())\n    for condition, deps in dependencies.items():\n        crate_deps += selects.with_or({\n            tuple(_CONDITIONS[condition]): deps.values(),\n            \"//conditions:default\": [],\n        })\n\n    return crate_deps\n\ndef aliases(\n        normal = False,\n        normal_dev = False,\n        proc_macro = False,\n        proc_macro_dev = False,\n        build = False,\n        build_proc_macro = False,\n        package_name = None):\n    \"\"\"Produces a map of Crate alias names to their original label\n\n    If no dependency kinds are specified, `normal` and `proc_macro` are used by default.\n    Setting any one flag will otherwise determine the contents of the returned dict.\n\n    Args:\n        normal (bool, optional): If True, normal dependencies are included in the\n            output list.\n        normal_dev (bool, optional): If True, normal dev dependencies will be\n            included in the output list..\n        proc_macro (bool, optional): If True, proc_macro dependencies are included\n            in the output list.\n        proc_macro_dev (bool, optional): If True, dev proc_macro dependencies are\n            included in the output list.\n        build (bool, optional): If True, build dependencies are included\n            in the output list.\n        build_proc_macro (bool, optional): If True, build proc_macro dependencies are\n            included in the output list.\n        package_name (str, optional): The package name of the set of dependencies to look up.\n            Defaults to `native.package_name()` when unset.\n\n    Returns:\n        dict: The aliases of all associated packages\n    \"\"\"\n    if package_name == None:\n        package_name = native.package_name()\n\n    # Determine the relevant maps to use\n    all_aliases_maps = []\n    if normal:\n        all_aliases_maps.append(_NORMAL_ALIASES)\n    if normal_dev:\n        all_aliases_maps.append(_NORMAL_DEV_ALIASES)\n    if proc_macro:\n        all_aliases_maps.append(_PROC_MACRO_ALIASES)\n    if proc_macro_dev:\n        all_aliases_maps.append(_PROC_MACRO_DEV_ALIASES)\n    if build:\n        all_aliases_maps.append(_BUILD_ALIASES)\n    if build_proc_macro:\n        all_aliases_maps.append(_BUILD_PROC_MACRO_ALIASES)\n\n    # Default to always using normal aliases\n    if not all_aliases_maps:\n        all_aliases_maps.append(_NORMAL_ALIASES)\n        all_aliases_maps.append(_PROC_MACRO_ALIASES)\n\n    aliases = _flatten_dependency_maps(all_aliases_maps).pop(package_name, None)\n\n    if not aliases:\n        return dict()\n\n    common_items = aliases.pop(_COMMON_CONDITION, {}).items()\n\n    # If there are only common items in the dictionary, immediately return them\n    if not len(aliases.keys()) == 1:\n        return dict(common_items)\n\n    # Build a single select statement where each conditional has accounted for the\n    # common set of aliases.\n    crate_aliases = {\"//conditions:default\": dict(common_items)}\n    for condition, deps in aliases.items():\n        condition_triples = _CONDITIONS[condition]\n        for triple in condition_triples:\n            if triple in crate_aliases:\n                crate_aliases[triple].update(deps)\n            else:\n                crate_aliases.update({triple: dict(deps.items() + common_items)})\n\n    return select(crate_aliases)\n\n###############################################################################\n# WORKSPACE MEMBER DEPS AND ALIASES\n###############################################################################\n\n_NORMAL_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n        _COMMON_CONDITION: {\n            \"aes\": Label(\"@rust_crates//:aes-0.8.4\"),\n            \"aes-gcm\": Label(\"@rust_crates//:aes-gcm-0.10.3\"),\n            \"aligned\": Label(\"@rust_crates//:aligned-0.4.3\"),\n            \"anyhow\": Label(\"@rust_crates//:anyhow-1.0.102\"),\n            \"bitflags\": Label(\"@rust_crates//:bitflags-2.11.0\"),\n            \"byteorder\": Label(\"@rust_crates//:byteorder-1.5.0\"),\n            \"cipher\": Label(\"@rust_crates//:cipher-0.4.4\"),\n            \"clap\": Label(\"@rust_crates//:clap-4.5.60\"),\n            \"compiler_builtins\": Label(\"@rust_crates//:compiler_builtins-0.1.160\"),\n            \"cortex-m\": Label(\"@rust_crates//:cortex-m-0.7.7\"),\n            \"ctr\": Label(\"@rust_crates//:ctr-0.9.2\"),\n            \"embedded-hal\": Label(\"@rust_crates//:embedded-hal-1.0.0\"),\n            \"embedded-hal-async\": Label(\"@rust_crates//:embedded-hal-async-1.0.0\"),\n            \"embedded-hal-nb\": Label(\"@rust_crates//:embedded-hal-nb-1.0.0\"),\n            \"embedded-io\": Label(\"@rust_crates//:embedded-io-0.6.1\"),\n            \"hashlink\": Label(\"@rust_crates//:hashlink-0.10.0\"),\n            \"heapless\": Label(\"@rust_crates//:heapless-0.9.2\"),\n            \"hmac\": Label(\"@rust_crates//:hmac-0.12.1\"),\n            \"k256\": Label(\"@rust_crates//:k256-0.13.4\"),\n            \"minijinja\": Label(\"@rust_crates//:minijinja-2.16.0\"),\n            \"nb\": Label(\"@rust_crates//:nb-1.1.0\"),\n            \"nom\": Label(\"@rust_crates//:nom-7.1.3\"),\n            \"object\": Label(\"@rust_crates//:object-0.37.3\"),\n            \"p256\": Label(\"@rust_crates//:p256-0.13.2\"),\n            \"p384\": Label(\"@rust_crates//:p384-0.13.1\"),\n            \"panic-halt\": Label(\"@rust_crates//:panic-halt-1.0.0\"),\n            \"proc-macro2\": Label(\"@rust_crates//:proc-macro2-1.0.106\"),\n            \"quote\": Label(\"@rust_crates//:quote-1.0.44\"),\n            \"rand_core\": Label(\"@rust_crates//:rand_core-0.9.5\"),\n            \"riscv\": Label(\"@rust_crates//:riscv-0.12.1\"),\n            \"riscv-rt\": Label(\"@rust_crates//:riscv-rt-0.12.2\"),\n            \"riscv-semihosting\": Label(\"@rust_crates//:riscv-semihosting-0.1.3\"),\n            \"rustc-demangle\": Label(\"@rust_crates//:rustc-demangle-0.1.27\"),\n            \"serde\": Label(\"@rust_crates//:serde-1.0.228\"),\n            \"serde_json5\": Label(\"@rust_crates//:serde_json5-0.2.1\"),\n            \"sha2\": Label(\"@rust_crates//:sha2-0.10.9\"),\n            \"sha3\": Label(\"@rust_crates//:sha3-0.10.8\"),\n            \"subtle\": Label(\"@rust_crates//:subtle-2.6.1\"),\n            \"syn\": Label(\"@rust_crates//:syn-2.0.116\"),\n            \"toml\": Label(\"@rust_crates//:toml-0.8.23\"),\n            \"ufmt\": Label(\"@rust_crates//:ufmt-0.2.0\"),\n            \"zerocopy\": Label(\"@rust_crates//:zerocopy-0.8.39\"),\n            \"zeroize\": Label(\"@rust_crates//:zeroize-1.8.2\"),\n        },\n    },\n}\n\n\n_NORMAL_ALIASES = {\n    \"third_party/crates_io\": {\n        _COMMON_CONDITION: {\n        },\n    },\n}\n\n\n_NORMAL_DEV_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_NORMAL_DEV_ALIASES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_PROC_MACRO_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n        _COMMON_CONDITION: {\n            \"bitfield-struct\": Label(\"@rust_crates//:bitfield-struct-0.11.0\"),\n            \"paste\": Label(\"@rust_crates//:paste-1.0.15\"),\n        },\n    },\n}\n\n\n_PROC_MACRO_ALIASES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_PROC_MACRO_DEV_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_PROC_MACRO_DEV_ALIASES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_BUILD_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_BUILD_ALIASES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_BUILD_PROC_MACRO_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_BUILD_PROC_MACRO_ALIASES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_CONDITIONS = {\n    \"aarch64-apple-darwin\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\"],\n    \"aarch64-linux-android\": [],\n    \"aarch64-unknown-linux-gnu\": [\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\"],\n    \"cfg(all(target_arch = \\\"aarch64\\\", target_os = \\\"linux\\\"))\": [\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\"],\n    \"cfg(all(target_arch = \\\"aarch64\\\", target_vendor = \\\"apple\\\"))\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\"],\n    \"cfg(all(target_arch = \\\"loongarch64\\\", target_os = \\\"linux\\\"))\": [],\n    \"cfg(any())\": [],\n    \"cfg(any(target_arch = \\\"aarch64\\\", target_arch = \\\"x86_64\\\", target_arch = \\\"x86\\\"))\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\",\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\",\"@rules_rust//rust/platform:x86_64-apple-darwin\",\"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\"],\n    \"cfg(any(target_arch = \\\"arm\\\", target_pointer_width = \\\"32\\\", target_pointer_width = \\\"64\\\"))\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\",\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\",\"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\",\"@rules_rust//rust/platform:x86_64-apple-darwin\",\"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\"],\n    \"cfg(target_arch = \\\"aarch64\\\")\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\",\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\"],\n    \"cfg(windows)\": [],\n    \"riscv32imc-unknown-none-elf\": [\"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\"],\n    \"x86_64-apple-darwin\": [\"@rules_rust//rust/platform:x86_64-apple-darwin\"],\n    \"x86_64-unknown-linux-gnu\": [\"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\"],\n}\n\n###############################################################################\n\ndef crate_repositories():\n    \"\"\"A macro for defining repositories for all generated crates.\n\n    Returns:\n      A list of repos visible to the module through the module extension.\n    \"\"\"\n    maybe(\n        http_archive,\n        name = \"rust_crates__adler2-2.0.1\",\n        sha256 = \"320119579fcad9c21884f5c4861d16174d0e06250625266f50fe6898340abefa\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/adler2/2.0.1/download\"],\n        strip_prefix = \"adler2-2.0.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.adler2-2.0.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__aead-0.5.2\",\n        sha256 = \"d122413f284cf2d62fb1b7db97e02edb8cda96d769b16e443a4f6195e35662b0\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/aead/0.5.2/download\"],\n        strip_prefix = \"aead-0.5.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.aead-0.5.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__aes-0.8.4\",\n        sha256 = \"b169f7a6d4742236a0a00c541b845991d0ac43e546831af1249753ab4c3aa3a0\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/aes/0.8.4/download\"],\n        strip_prefix = \"aes-0.8.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.aes-0.8.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__aes-gcm-0.10.3\",\n        sha256 = \"831010a0f742e1209b3bcea8fab6a8e149051ba6099432c8cb2cc117dec3ead1\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/aes-gcm/0.10.3/download\"],\n        strip_prefix = \"aes-gcm-0.10.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.aes-gcm-0.10.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__aligned-0.4.3\",\n        sha256 = \"ee4508988c62edf04abd8d92897fca0c2995d907ce1dfeaf369dac3716a40685\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/aligned/0.4.3/download\"],\n        strip_prefix = \"aligned-0.4.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.aligned-0.4.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anstream-0.6.21\",\n        sha256 = \"43d5b281e737544384e969a5ccad3f1cdd24b48086a0fc1b2a5262a26b8f4f4a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anstream/0.6.21/download\"],\n        strip_prefix = \"anstream-0.6.21\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anstream-0.6.21.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anstyle-1.0.13\",\n        sha256 = \"5192cca8006f1fd4f7237516f40fa183bb07f8fbdfedaa0036de5ea9b0b45e78\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anstyle/1.0.13/download\"],\n        strip_prefix = \"anstyle-1.0.13\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anstyle-1.0.13.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anstyle-parse-0.2.7\",\n        sha256 = \"4e7644824f0aa2c7b9384579234ef10eb7efb6a0deb83f9630a49594dd9c15c2\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anstyle-parse/0.2.7/download\"],\n        strip_prefix = \"anstyle-parse-0.2.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anstyle-parse-0.2.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anstyle-query-1.1.5\",\n        sha256 = \"40c48f72fd53cd289104fc64099abca73db4166ad86ea0b4341abe65af83dadc\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anstyle-query/1.1.5/download\"],\n        strip_prefix = \"anstyle-query-1.1.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anstyle-query-1.1.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anstyle-wincon-3.0.11\",\n        sha256 = \"291e6a250ff86cd4a820112fb8898808a366d8f9f58ce16d1f538353ad55747d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anstyle-wincon/3.0.11/download\"],\n        strip_prefix = \"anstyle-wincon-3.0.11\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anstyle-wincon-3.0.11.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anyhow-1.0.102\",\n        sha256 = \"7f202df86484c868dbad7eaa557ef785d5c66295e41b460ef922eca0723b842c\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anyhow/1.0.102/download\"],\n        strip_prefix = \"anyhow-1.0.102\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anyhow-1.0.102.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__as-slice-0.2.1\",\n        sha256 = \"516b6b4f0e40d50dcda9365d53964ec74560ad4284da2e7fc97122cd83174516\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/as-slice/0.2.1/download\"],\n        strip_prefix = \"as-slice-0.2.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.as-slice-0.2.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__bare-metal-0.2.5\",\n        sha256 = \"5deb64efa5bd81e31fcd1938615a6d98c82eafcbcd787162b6f63b91d6bac5b3\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/bare-metal/0.2.5/download\"],\n        strip_prefix = \"bare-metal-0.2.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.bare-metal-0.2.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__base16ct-0.2.0\",\n        sha256 = \"4c7f02d4ea65f2c1853089ffd8d2787bdbc63de2f0d29dedbcf8ccdfa0ccd4cf\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/base16ct/0.2.0/download\"],\n        strip_prefix = \"base16ct-0.2.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.base16ct-0.2.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__bitfield-0.13.2\",\n        sha256 = \"46afbd2983a5d5a7bd740ccb198caf5b82f45c40c09c0eed36052d91cb92e719\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/bitfield/0.13.2/download\"],\n        strip_prefix = \"bitfield-0.13.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.bitfield-0.13.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__bitfield-struct-0.11.0\",\n        sha256 = \"d3ca019570363e800b05ad4fd890734f28ac7b72f563ad8a35079efb793616f8\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/bitfield-struct/0.11.0/download\"],\n        strip_prefix = \"bitfield-struct-0.11.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.bitfield-struct-0.11.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__bitflags-2.11.0\",\n        sha256 = \"843867be96c8daad0d758b57df9392b6d8d271134fce549de6ce169ff98a92af\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/bitflags/2.11.0/download\"],\n        strip_prefix = \"bitflags-2.11.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.bitflags-2.11.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__block-buffer-0.10.4\",\n        sha256 = \"3078c7629b62d3f0439517fa394996acacc5cbc91c5a20d8c658e77abd503a71\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/block-buffer/0.10.4/download\"],\n        strip_prefix = \"block-buffer-0.10.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.block-buffer-0.10.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__byteorder-1.5.0\",\n        sha256 = \"1fd0f2584146f6f2ef48085050886acf353beff7305ebd1ae69500e27c67f64b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/byteorder/1.5.0/download\"],\n        strip_prefix = \"byteorder-1.5.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.byteorder-1.5.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__cfg-if-1.0.4\",\n        sha256 = \"9330f8b2ff13f34540b44e946ef35111825727b38d33286ef986142615121801\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/cfg-if/1.0.4/download\"],\n        strip_prefix = \"cfg-if-1.0.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.cfg-if-1.0.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__cipher-0.4.4\",\n        sha256 = \"773f3b9af64447d2ce9850330c473515014aa235e6a783b02db81ff39e4a3dad\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/cipher/0.4.4/download\"],\n        strip_prefix = \"cipher-0.4.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.cipher-0.4.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__clap-4.5.60\",\n        sha256 = \"2797f34da339ce31042b27d23607e051786132987f595b02ba4f6a6dffb7030a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/clap/4.5.60/download\"],\n        strip_prefix = \"clap-4.5.60\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.clap-4.5.60.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__clap_builder-4.5.60\",\n        sha256 = \"24a241312cea5059b13574bb9b3861cabf758b879c15190b37b6d6fd63ab6876\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/clap_builder/4.5.60/download\"],\n        strip_prefix = \"clap_builder-4.5.60\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.clap_builder-4.5.60.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__clap_derive-4.5.55\",\n        sha256 = \"a92793da1a46a5f2a02a6f4c46c6496b28c43638adea8306fcb0caa1634f24e5\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/clap_derive/4.5.55/download\"],\n        strip_prefix = \"clap_derive-4.5.55\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.clap_derive-4.5.55.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__clap_lex-1.0.0\",\n        sha256 = \"3a822ea5bc7590f9d40f1ba12c0dc3c2760f3482c6984db1573ad11031420831\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/clap_lex/1.0.0/download\"],\n        strip_prefix = \"clap_lex-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.clap_lex-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__colorchoice-1.0.4\",\n        sha256 = \"b05b61dc5112cbb17e4b6cd61790d9845d13888356391624cbe7e41efeac1e75\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/colorchoice/1.0.4/download\"],\n        strip_prefix = \"colorchoice-1.0.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.colorchoice-1.0.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__compiler_builtins-0.1.160\",\n        sha256 = \"6376049cfa92c0aa8b9ac95fae22184b981c658208d4ed8a1dc553cd83612895\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/compiler_builtins/0.1.160/download\"],\n        strip_prefix = \"compiler_builtins-0.1.160\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.compiler_builtins-0.1.160.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__const-oid-0.9.6\",\n        sha256 = \"c2459377285ad874054d797f3ccebf984978aa39129f6eafde5cdc8315b612f8\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/const-oid/0.9.6/download\"],\n        strip_prefix = \"const-oid-0.9.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.const-oid-0.9.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__cortex-m-0.7.7\",\n        sha256 = \"8ec610d8f49840a5b376c69663b6369e71f4b34484b9b2eb29fb918d92516cb9\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/cortex-m/0.7.7/download\"],\n        strip_prefix = \"cortex-m-0.7.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.cortex-m-0.7.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__cpufeatures-0.2.17\",\n        sha256 = \"59ed5838eebb26a2bb2e58f6d5b5316989ae9d08bab10e0e6d103e656d1b0280\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/cpufeatures/0.2.17/download\"],\n        strip_prefix = \"cpufeatures-0.2.17\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.cpufeatures-0.2.17.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__crc32fast-1.5.0\",\n        sha256 = \"9481c1c90cbf2ac953f07c8d4a58aa3945c425b7185c9154d67a65e4230da511\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/crc32fast/1.5.0/download\"],\n        strip_prefix = \"crc32fast-1.5.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.crc32fast-1.5.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__critical-section-1.2.0\",\n        sha256 = \"790eea4361631c5e7d22598ecd5723ff611904e3344ce8720784c93e3d83d40b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/critical-section/1.2.0/download\"],\n        strip_prefix = \"critical-section-1.2.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.critical-section-1.2.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__crypto-bigint-0.5.5\",\n        sha256 = \"0dc92fb57ca44df6db8059111ab3af99a63d5d0f8375d9972e319a379c6bab76\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/crypto-bigint/0.5.5/download\"],\n        strip_prefix = \"crypto-bigint-0.5.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.crypto-bigint-0.5.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__crypto-common-0.1.7\",\n        sha256 = \"78c8292055d1c1df0cce5d180393dc8cce0abec0a7102adb6c7b1eef6016d60a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/crypto-common/0.1.7/download\"],\n        strip_prefix = \"crypto-common-0.1.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.crypto-common-0.1.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ctr-0.9.2\",\n        sha256 = \"0369ee1ad671834580515889b80f2ea915f23b8be8d0daa4bbaf2ac5c7590835\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ctr/0.9.2/download\"],\n        strip_prefix = \"ctr-0.9.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ctr-0.9.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__der-0.7.10\",\n        sha256 = \"e7c1832837b905bbfb5101e07cc24c8deddf52f93225eee6ead5f4d63d53ddcb\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/der/0.7.10/download\"],\n        strip_prefix = \"der-0.7.10\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.der-0.7.10.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__digest-0.10.7\",\n        sha256 = \"9ed9a281f7bc9b7576e61468ba615a66a5c8cfdff42420a70aa82701a3b1e292\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/digest/0.10.7/download\"],\n        strip_prefix = \"digest-0.10.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.digest-0.10.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ecdsa-0.16.9\",\n        sha256 = \"ee27f32b5c5292967d2d4a9d7f1e0b0aed2c15daded5a60300e4abb9d8020bca\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ecdsa/0.16.9/download\"],\n        strip_prefix = \"ecdsa-0.16.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ecdsa-0.16.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__elliptic-curve-0.13.8\",\n        sha256 = \"b5e6043086bf7973472e0c7dff2142ea0b680d30e18d9cc40f267efbf222bd47\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/elliptic-curve/0.13.8/download\"],\n        strip_prefix = \"elliptic-curve-0.13.8\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.elliptic-curve-0.13.8.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-hal-0.2.7\",\n        sha256 = \"35949884794ad573cf46071e41c9b60efb0cb311e3ca01f7af807af1debc66ff\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-hal/0.2.7/download\"],\n        strip_prefix = \"embedded-hal-0.2.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-hal-0.2.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-hal-1.0.0\",\n        sha256 = \"361a90feb7004eca4019fb28352a9465666b24f840f5c3cddf0ff13920590b89\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-hal/1.0.0/download\"],\n        strip_prefix = \"embedded-hal-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-hal-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-hal-async-1.0.0\",\n        sha256 = \"0c4c685bbef7fe13c3c6dd4da26841ed3980ef33e841cddfa15ce8a8fb3f1884\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-hal-async/1.0.0/download\"],\n        strip_prefix = \"embedded-hal-async-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-hal-async-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-hal-nb-1.0.0\",\n        sha256 = \"fba4268c14288c828995299e59b12babdbe170f6c6d73731af1b4648142e8605\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-hal-nb/1.0.0/download\"],\n        strip_prefix = \"embedded-hal-nb-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-hal-nb-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-io-0.6.1\",\n        sha256 = \"edd0f118536f44f5ccd48bcb8b111bdc3de888b58c74639dfb034a357d0f206d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-io/0.6.1/download\"],\n        strip_prefix = \"embedded-io-0.6.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-io-0.6.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__equivalent-1.0.2\",\n        sha256 = \"877a4ace8713b0bcf2a4e7eec82529c029f1d0619886d18145fea96c3ffe5c0f\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/equivalent/1.0.2/download\"],\n        strip_prefix = \"equivalent-1.0.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.equivalent-1.0.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ff-0.13.1\",\n        sha256 = \"c0b50bfb653653f9ca9095b427bed08ab8d75a137839d9ad64eb11810d5b6393\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ff/0.13.1/download\"],\n        strip_prefix = \"ff-0.13.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ff-0.13.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__flate2-1.1.9\",\n        sha256 = \"843fba2746e448b37e26a819579957415c8cef339bf08564fe8b7ddbd959573c\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/flate2/1.1.9/download\"],\n        strip_prefix = \"flate2-1.1.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.flate2-1.1.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__foldhash-0.1.5\",\n        sha256 = \"d9c4f5dac5e15c24eb999c26181a6ca40b39fe946cbe4c263c7209467bc83af2\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/foldhash/0.1.5/download\"],\n        strip_prefix = \"foldhash-0.1.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.foldhash-0.1.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__generic-array-0.14.7\",\n        sha256 = \"85649ca51fd72272d7821adaf274ad91c288277713d9c18820d8499a7ff69e9a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/generic-array/0.14.7/download\"],\n        strip_prefix = \"generic-array-0.14.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.generic-array-0.14.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ghash-0.5.1\",\n        sha256 = \"f0d8a4362ccb29cb0b265253fb0a2728f592895ee6854fd9bc13f2ffda266ff1\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ghash/0.5.1/download\"],\n        strip_prefix = \"ghash-0.5.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ghash-0.5.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__group-0.13.0\",\n        sha256 = \"f0f9ef7462f7c099f518d754361858f86d8a07af53ba9af0fe635bbccb151a63\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/group/0.13.0/download\"],\n        strip_prefix = \"group-0.13.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.group-0.13.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__hash32-0.3.1\",\n        sha256 = \"47d60b12902ba28e2730cd37e95b8c9223af2808df9e902d4df49588d1470606\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/hash32/0.3.1/download\"],\n        strip_prefix = \"hash32-0.3.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.hash32-0.3.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__hashbrown-0.15.5\",\n        sha256 = \"9229cfe53dfd69f0609a49f65461bd93001ea1ef889cd5529dd176593f5338a1\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/hashbrown/0.15.5/download\"],\n        strip_prefix = \"hashbrown-0.15.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.hashbrown-0.15.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__hashbrown-0.16.1\",\n        sha256 = \"841d1cc9bed7f9236f321df977030373f4a4163ae1a7dbfe1a51a2c1a51d9100\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/hashbrown/0.16.1/download\"],\n        strip_prefix = \"hashbrown-0.16.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.hashbrown-0.16.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__hashlink-0.10.0\",\n        sha256 = \"7382cf6263419f2d8df38c55d7da83da5c18aef87fc7a7fc1fb1e344edfe14c1\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/hashlink/0.10.0/download\"],\n        strip_prefix = \"hashlink-0.10.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.hashlink-0.10.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__heapless-0.9.2\",\n        sha256 = \"2af2455f757db2b292a9b1768c4b70186d443bcb3b316252d6b540aec1cd89ed\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/heapless/0.9.2/download\"],\n        strip_prefix = \"heapless-0.9.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.heapless-0.9.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__heck-0.5.0\",\n        sha256 = \"2304e00983f87ffb38b55b444b5e3b60a884b5d30c0fca7d82fe33449bbe55ea\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/heck/0.5.0/download\"],\n        strip_prefix = \"heck-0.5.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.heck-0.5.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__hmac-0.12.1\",\n        sha256 = \"6c49c37c09c17a53d937dfbb742eb3a961d65a994e6bcdcf37e7399d0cc8ab5e\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/hmac/0.12.1/download\"],\n        strip_prefix = \"hmac-0.12.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.hmac-0.12.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__indexmap-2.13.0\",\n        sha256 = \"7714e70437a7dc3ac8eb7e6f8df75fd8eb422675fc7678aff7364301092b1017\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/indexmap/2.13.0/download\"],\n        strip_prefix = \"indexmap-2.13.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.indexmap-2.13.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__inout-0.1.4\",\n        sha256 = \"879f10e63c20629ecabbb64a8010319738c66a5cd0c29b02d63d272b03751d01\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/inout/0.1.4/download\"],\n        strip_prefix = \"inout-0.1.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.inout-0.1.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__is_terminal_polyfill-1.70.2\",\n        sha256 = \"a6cb138bb79a146c1bd460005623e142ef0181e3d0219cb493e02f7d08a35695\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/is_terminal_polyfill/1.70.2/download\"],\n        strip_prefix = \"is_terminal_polyfill-1.70.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.is_terminal_polyfill-1.70.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__k256-0.13.4\",\n        sha256 = \"f6e3919bbaa2945715f0bb6d3934a173d1e9a59ac23767fbaaef277265a7411b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/k256/0.13.4/download\"],\n        strip_prefix = \"k256-0.13.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.k256-0.13.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__keccak-0.1.6\",\n        sha256 = \"cb26cec98cce3a3d96cbb7bced3c4b16e3d13f27ec56dbd62cbc8f39cfb9d653\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/keccak/0.1.6/download\"],\n        strip_prefix = \"keccak-0.1.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.keccak-0.1.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__libc-0.2.182\",\n        sha256 = \"6800badb6cb2082ffd7b6a67e6125bb39f18782f793520caee8cb8846be06112\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/libc/0.2.182/download\"],\n        strip_prefix = \"libc-0.2.182\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.libc-0.2.182.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__memchr-2.8.0\",\n        sha256 = \"f8ca58f447f06ed17d5fc4043ce1b10dd205e060fb3ce5b979b8ed8e59ff3f79\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/memchr/2.8.0/download\"],\n        strip_prefix = \"memchr-2.8.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.memchr-2.8.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__memo-map-0.3.3\",\n        sha256 = \"38d1115007560874e373613744c6fba374c17688327a71c1476d1a5954cc857b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/memo-map/0.3.3/download\"],\n        strip_prefix = \"memo-map-0.3.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.memo-map-0.3.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__minijinja-2.16.0\",\n        sha256 = \"5c54f3bcc034dd74496b5ca929fd0b710186672d5ff0b0f255a9ceb259042ece\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/minijinja/2.16.0/download\"],\n        strip_prefix = \"minijinja-2.16.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.minijinja-2.16.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__minimal-lexical-0.2.1\",\n        sha256 = \"68354c5c6bd36d73ff3feceb05efa59b6acb7626617f4962be322a825e61f79a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/minimal-lexical/0.2.1/download\"],\n        strip_prefix = \"minimal-lexical-0.2.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.minimal-lexical-0.2.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__miniz_oxide-0.8.9\",\n        sha256 = \"1fa76a2c86f704bdb222d66965fb3d63269ce38518b83cb0575fca855ebb6316\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/miniz_oxide/0.8.9/download\"],\n        strip_prefix = \"miniz_oxide-0.8.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.miniz_oxide-0.8.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__nb-0.1.3\",\n        sha256 = \"801d31da0513b6ec5214e9bf433a77966320625a37860f910be265be6e18d06f\",\n       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Label(\"@rust_crates//rust_crates:BUILD.nom-7.1.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__object-0.37.3\",\n        sha256 = \"ff76201f031d8863c38aa7f905eca4f53abbfa15f609db4277d44cd8938f33fe\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/object/0.37.3/download\"],\n        strip_prefix = \"object-0.37.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.object-0.37.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__once_cell_polyfill-1.70.2\",\n        sha256 = \"384b8ab6d37215f3c5301a95a4accb5d64aa607f1fcb26a11b5303878451b4fe\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/once_cell_polyfill/1.70.2/download\"],\n        strip_prefix = \"once_cell_polyfill-1.70.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.once_cell_polyfill-1.70.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__opaque-debug-0.3.1\",\n        sha256 = \"c08d65885ee38876c4f86fa503fb49d7b507c2b62552df7c70b2fce627e06381\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/opaque-debug/0.3.1/download\"],\n        strip_prefix = \"opaque-debug-0.3.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.opaque-debug-0.3.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__p256-0.13.2\",\n        sha256 = \"c9863ad85fa8f4460f9c48cb909d38a0d689dba1f6f6988a5e3e0d31071bcd4b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/p256/0.13.2/download\"],\n        strip_prefix = \"p256-0.13.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.p256-0.13.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__p384-0.13.1\",\n        sha256 = \"fe42f1670a52a47d448f14b6a5c61dd78fce51856e68edaa38f7ae3a46b8d6b6\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/p384/0.13.1/download\"],\n        strip_prefix = \"p384-0.13.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.p384-0.13.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__panic-halt-1.0.0\",\n        sha256 = \"a513e167849a384b7f9b746e517604398518590a9142f4846a32e3c2a4de7b11\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/panic-halt/1.0.0/download\"],\n        strip_prefix = \"panic-halt-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.panic-halt-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__paste-1.0.15\",\n        sha256 = \"57c0d7b74b563b49d38dae00a0c37d4d6de9b432382b2892f0574ddcae73fd0a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/paste/1.0.15/download\"],\n        strip_prefix = \"paste-1.0.15\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.paste-1.0.15.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__pest-2.8.6\",\n        sha256 = \"e0848c601009d37dfa3430c4666e147e49cdcf1b92ecd3e63657d8a5f19da662\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/pest/2.8.6/download\"],\n        strip_prefix = \"pest-2.8.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.pest-2.8.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__pest_derive-2.8.6\",\n        sha256 = \"11f486f1ea21e6c10ed15d5a7c77165d0ee443402f0780849d1768e7d9d6fe77\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/pest_derive/2.8.6/download\"],\n        strip_prefix = \"pest_derive-2.8.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.pest_derive-2.8.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__pest_generator-2.8.6\",\n        sha256 = \"8040c4647b13b210a963c1ed407c1ff4fdfa01c31d6d2a098218702e6664f94f\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/pest_generator/2.8.6/download\"],\n        strip_prefix = \"pest_generator-2.8.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.pest_generator-2.8.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__pest_meta-2.8.6\",\n        sha256 = \"89815c69d36021a140146f26659a81d6c2afa33d216d736dd4be5381a7362220\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/pest_meta/2.8.6/download\"],\n        strip_prefix = \"pest_meta-2.8.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.pest_meta-2.8.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__polyval-0.6.2\",\n        sha256 = \"9d1fe60d06143b2430aa532c94cfe9e29783047f06c0d7fd359a9a51b729fa25\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/polyval/0.6.2/download\"],\n        strip_prefix = \"polyval-0.6.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.polyval-0.6.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__primeorder-0.13.6\",\n        sha256 = \"353e1ca18966c16d9deb1c69278edbc5f194139612772bd9537af60ac231e1e6\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/primeorder/0.13.6/download\"],\n        strip_prefix = \"primeorder-0.13.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.primeorder-0.13.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__proc-macro2-1.0.106\",\n        sha256 = \"8fd00f0bb2e90d81d1044c2b32617f68fcb9fa3bb7640c23e9c748e53fb30934\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/proc-macro2/1.0.106/download\"],\n        strip_prefix = \"proc-macro2-1.0.106\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.proc-macro2-1.0.106.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__quote-1.0.44\",\n        sha256 = \"21b2ebcf727b7760c461f091f9f0f539b77b8e87f2fd88131e7f1b433b3cece4\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/quote/1.0.44/download\"],\n        strip_prefix = \"quote-1.0.44\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.quote-1.0.44.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__rand_core-0.6.4\",\n        sha256 = \"ec0be4795e2f6a28069bec0b5ff3e2ac9bafc99e6a9a7dc3547996c5c816922c\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/rand_core/0.6.4/download\"],\n        strip_prefix = \"rand_core-0.6.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.rand_core-0.6.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__rand_core-0.9.5\",\n        sha256 = \"76afc826de14238e6e8c374ddcc1fa19e374fd8dd986b0d2af0d02377261d83c\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/rand_core/0.9.5/download\"],\n        strip_prefix = \"rand_core-0.9.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.rand_core-0.9.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__rfc6979-0.4.0\",\n        sha256 = \"f8dd2a808d456c4a54e300a23e9f5a67e122c3024119acbfd73e3bf664491cb2\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/rfc6979/0.4.0/download\"],\n        strip_prefix = \"rfc6979-0.4.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.rfc6979-0.4.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-0.11.1\",\n        sha256 = \"2f5c1b8bf41ea746266cdee443d1d1e9125c86ce1447e1a2615abd34330d33a9\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv/0.11.1/download\"],\n        strip_prefix = \"riscv-0.11.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-0.11.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-0.12.1\",\n        sha256 = \"5ea8ff73d3720bdd0a97925f0bf79ad2744b6da8ff36be3840c48ac81191d7a7\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv/0.12.1/download\"],\n        strip_prefix = \"riscv-0.12.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-0.12.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-0.13.0\",\n        sha256 = \"afa3cdbeccae4359f6839a00e8b77e5736caa200ba216caf38d24e4c16e2b586\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv/0.13.0/download\"],\n        strip_prefix = \"riscv-0.13.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-0.13.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-macros-0.1.0\",\n        sha256 = \"f265be5d634272320a7de94cea15c22a3bfdd4eb42eb43edc528415f066a1f25\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-macros/0.1.0/download\"],\n        strip_prefix = \"riscv-macros-0.1.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-macros-0.1.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-macros-0.2.0\",\n        sha256 = \"e8c4aa1ea1af6dcc83a61be12e8189f9b293c3ba5a487778a4cd89fb060fdbbc\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-macros/0.2.0/download\"],\n        strip_prefix = \"riscv-macros-0.2.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-macros-0.2.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-pac-0.2.0\",\n        sha256 = \"8188909339ccc0c68cfb5a04648313f09621e8b87dc03095454f1a11f6c5d436\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-pac/0.2.0/download\"],\n        strip_prefix = \"riscv-pac-0.2.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-pac-0.2.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-rt-0.12.2\",\n        sha256 = \"c0d35e32cf1383183e8885d8a9aa4402a087fd094dc34c2cb6df6687d0229dfe\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-rt/0.12.2/download\"],\n        strip_prefix = \"riscv-rt-0.12.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-rt-0.12.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-rt-macros-0.2.2\",\n        sha256 = \"30f19a85fe107b65031e0ba8ec60c34c2494069fe910d6c297f5e7cb5a6f76d0\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-rt-macros/0.2.2/download\"],\n        strip_prefix = \"riscv-rt-macros-0.2.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-rt-macros-0.2.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-semihosting-0.1.3\",\n        sha256 = \"1086dd4bcc13de1cb14b93849411e3466de7e5907d2d8eb269032536e93facc6\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-semihosting/0.1.3/download\"],\n        strip_prefix = \"riscv-semihosting-0.1.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-semihosting-0.1.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__rustc-demangle-0.1.27\",\n        sha256 = \"b50b8869d9fc858ce7266cce0194bd74df58b9d0e3f6df3a9fc8eb470d95c09d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/rustc-demangle/0.1.27/download\"],\n        strip_prefix = \"rustc-demangle-0.1.27\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.rustc-demangle-0.1.27.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__rustc_version-0.2.3\",\n        sha256 = \"138e3e0acb6c9fb258b19b67cb8abd63c00679d2851805ea151465464fe9030a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/rustc_version/0.2.3/download\"],\n        strip_prefix = \"rustc_version-0.2.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.rustc_version-0.2.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ruzstd-0.8.2\",\n        sha256 = \"e5ff0cc5e135c8870a775d3320910cd9b564ec036b4dc0b8741629020be63f01\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ruzstd/0.8.2/download\"],\n        strip_prefix = \"ruzstd-0.8.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ruzstd-0.8.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__sec1-0.7.3\",\n        sha256 = \"d3e97a565f76233a6003f9f5c54be1d9c5bdfa3eccfb189469f11ec4901c47dc\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/sec1/0.7.3/download\"],\n        strip_prefix = \"sec1-0.7.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.sec1-0.7.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__self_cell-1.2.2\",\n        sha256 = \"b12e76d157a900eb52e81bc6e9f3069344290341720e9178cde2407113ac8d89\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/self_cell/1.2.2/download\"],\n        strip_prefix = \"self_cell-1.2.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.self_cell-1.2.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__semver-0.9.0\",\n        sha256 = \"1d7eb9ef2c18661902cc47e535f9bc51b78acd254da71d375c2f6720d9a40403\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/semver/0.9.0/download\"],\n        strip_prefix = \"semver-0.9.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.semver-0.9.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__semver-parser-0.7.0\",\n        sha256 = \"388a1df253eca08550bef6c72392cfe7c30914bf41df5269b68cbd6ff8f570a3\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/semver-parser/0.7.0/download\"],\n        strip_prefix = \"semver-parser-0.7.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.semver-parser-0.7.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__serde-1.0.228\",\n        sha256 = \"9a8e94ea7f378bd32cbbd37198a4a91436180c5bb472411e48b5ec2e2124ae9e\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/serde/1.0.228/download\"],\n        strip_prefix = \"serde-1.0.228\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.serde-1.0.228.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__serde_core-1.0.228\",\n        sha256 = \"41d385c7d4ca58e59fc732af25c3983b67ac852c1a25000afe1175de458b67ad\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/serde_core/1.0.228/download\"],\n        strip_prefix = \"serde_core-1.0.228\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.serde_core-1.0.228.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__serde_derive-1.0.228\",\n        sha256 = \"d540f220d3187173da220f885ab66608367b6574e925011a9353e4badda91d79\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/serde_derive/1.0.228/download\"],\n        strip_prefix = \"serde_derive-1.0.228\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.serde_derive-1.0.228.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__serde_json5-0.2.1\",\n        sha256 = \"5d34d03f54462862f2a42918391c9526337f53171eaa4d8894562be7f252edd3\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/serde_json5/0.2.1/download\"],\n        strip_prefix = \"serde_json5-0.2.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.serde_json5-0.2.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__serde_spanned-0.6.9\",\n        sha256 = \"bf41e0cfaf7226dca15e8197172c295a782857fcb97fad1808a166870dee75a3\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/serde_spanned/0.6.9/download\"],\n        strip_prefix = \"serde_spanned-0.6.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.serde_spanned-0.6.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__sha2-0.10.9\",\n        sha256 = \"a7507d819769d01a365ab707794a4084392c824f54a7a6a7862f8c3d0892b283\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/sha2/0.10.9/download\"],\n        strip_prefix = \"sha2-0.10.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.sha2-0.10.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__sha3-0.10.8\",\n        sha256 = \"75872d278a8f37ef87fa0ddbda7802605cb18344497949862c0d4dcb291eba60\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/sha3/0.10.8/download\"],\n        strip_prefix = \"sha3-0.10.8\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.sha3-0.10.8.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__signature-2.2.0\",\n        sha256 = \"77549399552de45a898a580c1b41d445bf730df867cc44e6c0233bbc4b8329de\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/signature/2.2.0/download\"],\n        strip_prefix = \"signature-2.2.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.signature-2.2.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__simd-adler32-0.3.8\",\n        sha256 = \"e320a6c5ad31d271ad523dcf3ad13e2767ad8b1cb8f047f75a8aeaf8da139da2\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/simd-adler32/0.3.8/download\"],\n        strip_prefix = \"simd-adler32-0.3.8\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.simd-adler32-0.3.8.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__stable_deref_trait-1.2.1\",\n        sha256 = \"6ce2be8dc25455e1f91df71bfa12ad37d7af1092ae736f3a6cd0e37bc7810596\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/stable_deref_trait/1.2.1/download\"],\n        strip_prefix = \"stable_deref_trait-1.2.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.stable_deref_trait-1.2.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__strsim-0.11.1\",\n        sha256 = \"7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/strsim/0.11.1/download\"],\n        strip_prefix = \"strsim-0.11.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.strsim-0.11.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__subtle-2.6.1\",\n        sha256 = \"13c2bddecc57b384dee18652358fb23172facb8a2c51ccc10d74c157bdea3292\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/subtle/2.6.1/download\"],\n        strip_prefix = \"subtle-2.6.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.subtle-2.6.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__syn-1.0.109\",\n        sha256 = \"72b64191b275b66ffe2469e8af2c1cfe3bafa67b529ead792a6d0160888b4237\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/syn/1.0.109/download\"],\n        strip_prefix = \"syn-1.0.109\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.syn-1.0.109.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__syn-2.0.116\",\n        sha256 = \"3df424c70518695237746f84cede799c9c58fcb37450d7b23716568cc8bc69cb\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/syn/2.0.116/download\"],\n        strip_prefix = \"syn-2.0.116\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.syn-2.0.116.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__toml-0.8.23\",\n        sha256 = \"dc1beb996b9d83529a9e75c17a1686767d148d70663143c7854d8b4a09ced362\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/toml/0.8.23/download\"],\n        strip_prefix = \"toml-0.8.23\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.toml-0.8.23.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__toml_datetime-0.6.11\",\n        sha256 = \"22cddaf88f4fbc13c51aebbf5f8eceb5c7c5a9da2ac40a13519eb5b0a0e8f11c\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/toml_datetime/0.6.11/download\"],\n        strip_prefix = \"toml_datetime-0.6.11\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.toml_datetime-0.6.11.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__toml_edit-0.22.27\",\n        sha256 = \"41fe8c660ae4257887cf66394862d21dbca4a6ddd26f04a3560410406a2f819a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/toml_edit/0.22.27/download\"],\n        strip_prefix = \"toml_edit-0.22.27\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.toml_edit-0.22.27.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__toml_write-0.1.2\",\n        sha256 = \"5d99f8c9a7727884afe522e9bd5edbfc91a3312b36a77b5fb8926e4c31a41801\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/toml_write/0.1.2/download\"],\n        strip_prefix = \"toml_write-0.1.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.toml_write-0.1.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__twox-hash-2.1.2\",\n        sha256 = \"9ea3136b675547379c4bd395ca6b938e5ad3c3d20fad76e7fe85f9e0d011419c\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/twox-hash/2.1.2/download\"],\n        strip_prefix = \"twox-hash-2.1.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.twox-hash-2.1.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__typenum-1.19.0\",\n        sha256 = \"562d481066bde0658276a35467c4af00bdc6ee726305698a55b86e61d7ad82bb\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/typenum/1.19.0/download\"],\n        strip_prefix = \"typenum-1.19.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.typenum-1.19.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ucd-trie-0.1.7\",\n        sha256 = \"2896d95c02a80c6d6a5d6e953d479f5ddf2dfdb6a244441010e373ac0fb88971\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ucd-trie/0.1.7/download\"],\n        strip_prefix = \"ucd-trie-0.1.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ucd-trie-0.1.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ufmt-0.2.0\",\n        sha256 = \"1a64846ec02b57e9108d6469d98d1648782ad6bb150a95a9baac26900bbeab9d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ufmt/0.2.0/download\"],\n        strip_prefix = \"ufmt-0.2.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ufmt-0.2.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ufmt-macros-0.3.0\",\n        sha256 = \"d337d3be617449165cb4633c8dece429afd83f84051024079f97ad32a9663716\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ufmt-macros/0.3.0/download\"],\n        strip_prefix = \"ufmt-macros-0.3.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ufmt-macros-0.3.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ufmt-write-0.1.0\",\n        sha256 = \"e87a2ed6b42ec5e28cc3b94c09982969e9227600b2e3dcbc1db927a84c06bd69\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ufmt-write/0.1.0/download\"],\n        strip_prefix = \"ufmt-write-0.1.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ufmt-write-0.1.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__unicode-ident-1.0.24\",\n        sha256 = \"e6e4313cd5fcd3dad5cafa179702e2b244f760991f45397d14d4ebf38247da75\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/unicode-ident/1.0.24/download\"],\n        strip_prefix = \"unicode-ident-1.0.24\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.unicode-ident-1.0.24.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__universal-hash-0.5.1\",\n        sha256 = \"fc1de2c688dc15305988b563c3854064043356019f97a4b46276fe734c4f07ea\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/universal-hash/0.5.1/download\"],\n        strip_prefix = \"universal-hash-0.5.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.universal-hash-0.5.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__utf8parse-0.2.2\",\n        sha256 = \"06abde3611657adf66d383f00b093d7faecc7fa57071cce2578660c9f1010821\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/utf8parse/0.2.2/download\"],\n        strip_prefix = \"utf8parse-0.2.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.utf8parse-0.2.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__vcell-0.1.3\",\n        sha256 = \"77439c1b53d2303b20d9459b1ade71a83c716e3f9c34f3228c00e6f185d6c002\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/vcell/0.1.3/download\"],\n        strip_prefix = \"vcell-0.1.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.vcell-0.1.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__version_check-0.9.5\",\n        sha256 = \"0b928f33d975fc6ad9f86c8f283853ad26bdd5b10b7f1542aa2fa15e2289105a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/version_check/0.9.5/download\"],\n        strip_prefix = \"version_check-0.9.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.version_check-0.9.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__void-1.0.2\",\n        sha256 = \"6a02e4885ed3bc0f2de90ea6dd45ebcbb66dacffe03547fadbb0eeae2770887d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/void/1.0.2/download\"],\n        strip_prefix = \"void-1.0.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.void-1.0.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__volatile-register-0.2.2\",\n        sha256 = \"de437e2a6208b014ab52972a27e59b33fa2920d3e00fe05026167a1c509d19cc\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/volatile-register/0.2.2/download\"],\n        strip_prefix = \"volatile-register-0.2.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.volatile-register-0.2.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__windows-link-0.2.1\",\n        sha256 = \"f0805222e57f7521d6a62e36fa9163bc891acd422f971defe97d64e70d0a4fe5\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/windows-link/0.2.1/download\"],\n        strip_prefix = \"windows-link-0.2.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.windows-link-0.2.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__windows-sys-0.61.2\",\n        sha256 = \"ae137229bcbd6cdf0f7b80a31df61766145077ddf49416a728b02cb3921ff3fc\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/windows-sys/0.61.2/download\"],\n        strip_prefix = \"windows-sys-0.61.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.windows-sys-0.61.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__winnow-0.7.14\",\n        sha256 = \"5a5364e9d77fcdeeaa6062ced926ee3381faa2ee02d3eb83a5c27a8825540829\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/winnow/0.7.14/download\"],\n        strip_prefix = \"winnow-0.7.14\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.winnow-0.7.14.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__zerocopy-0.8.39\",\n        sha256 = \"db6d35d663eadb6c932438e763b262fe1a70987f9ae936e60158176d710cae4a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/zerocopy/0.8.39/download\"],\n        strip_prefix = \"zerocopy-0.8.39\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.zerocopy-0.8.39.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__zerocopy-derive-0.8.39\",\n        sha256 = \"4122cd3169e94605190e77839c9a40d40ed048d305bfdc146e7df40ab0f3e517\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/zerocopy-derive/0.8.39/download\"],\n        strip_prefix = \"zerocopy-derive-0.8.39\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.zerocopy-derive-0.8.39.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__zeroize-1.8.2\",\n        sha256 = \"b97154e67e32c85465826e8bcc1c59429aaaf107c1e4a9e53c8d8ccd5eff88d0\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/zeroize/1.8.2/download\"],\n        strip_prefix = \"zeroize-1.8.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.zeroize-1.8.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__zeroize_derive-1.4.3\",\n        sha256 = \"85a5b4158499876c763cb03bc4e49185d3cccbabb15b33c627f7884f43db852e\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/zeroize_derive/1.4.3/download\"],\n        strip_prefix = \"zeroize_derive-1.4.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.zeroize_derive-1.4.3.bazel\"),\n    )\n\n    return [\n       struct(repo=\"rust_crates__aes-0.8.4\", is_dev_dep = False),\n       struct(repo=\"rust_crates__aes-gcm-0.10.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__aligned-0.4.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__anyhow-1.0.102\", is_dev_dep = False),\n       struct(repo=\"rust_crates__bitfield-struct-0.11.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__bitflags-2.11.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__byteorder-1.5.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__cipher-0.4.4\", is_dev_dep = False),\n       struct(repo=\"rust_crates__clap-4.5.60\", is_dev_dep = False),\n       struct(repo=\"rust_crates__compiler_builtins-0.1.160\", is_dev_dep = False),\n       struct(repo=\"rust_crates__cortex-m-0.7.7\", is_dev_dep = False),\n       struct(repo=\"rust_crates__ctr-0.9.2\", is_dev_dep = False),\n       struct(repo=\"rust_crates__embedded-hal-1.0.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__embedded-hal-async-1.0.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__embedded-hal-nb-1.0.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__embedded-io-0.6.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__hashlink-0.10.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__heapless-0.9.2\", is_dev_dep = False),\n       struct(repo=\"rust_crates__hmac-0.12.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__k256-0.13.4\", is_dev_dep = False),\n       struct(repo=\"rust_crates__minijinja-2.16.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__nb-1.1.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__nom-7.1.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__object-0.37.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__p256-0.13.2\", is_dev_dep = False),\n       struct(repo=\"rust_crates__p384-0.13.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__panic-halt-1.0.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__paste-1.0.15\", is_dev_dep = False),\n       struct(repo=\"rust_crates__proc-macro2-1.0.106\", is_dev_dep = False),\n       struct(repo=\"rust_crates__quote-1.0.44\", is_dev_dep = False),\n       struct(repo=\"rust_crates__rand_core-0.9.5\", is_dev_dep = False),\n       struct(repo=\"rust_crates__riscv-0.12.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__riscv-rt-0.12.2\", is_dev_dep = False),\n       struct(repo=\"rust_crates__riscv-semihosting-0.1.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__rustc-demangle-0.1.27\", is_dev_dep = False),\n       struct(repo=\"rust_crates__serde-1.0.228\", is_dev_dep = False),\n       struct(repo=\"rust_crates__serde_json5-0.2.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__sha2-0.10.9\", is_dev_dep = False),\n       struct(repo=\"rust_crates__sha3-0.10.8\", is_dev_dep = False),\n       struct(repo=\"rust_crates__subtle-2.6.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__syn-2.0.116\", is_dev_dep = False),\n       struct(repo=\"rust_crates__toml-0.8.23\", is_dev_dep = False),\n       struct(repo=\"rust_crates__ufmt-0.2.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__zerocopy-0.8.39\", is_dev_dep = False),\n       struct(repo=\"rust_crates__zeroize-1.8.2\", is_dev_dep = False),\n    ]\n"
               }
             }
           },
@@ -2098,6 +2098,22 @@
               "build_file_content": "###############################################################################\n# @generated\n# DO NOT MODIFY: This file is auto-generated by a crate_universe tool. To \n# regenerate this file, run the following:\n#\n#     bazel mod show_repo 'openprot'\n###############################################################################\n\nload(\"@rules_rust//cargo:defs.bzl\", \"cargo_toml_env_vars\")\n\nload(\"@rules_rust//rust:defs.bzl\", \"rust_library\")\n\n# buildifier: disable=bzl-visibility\nload(\"@rules_rust//crate_universe/private:selects.bzl\", \"selects\")\n\npackage(default_visibility = [\"//visibility:public\"])\n\ncargo_toml_env_vars(\n    name = \"cargo_toml_env_vars\",\n    src = \"Cargo.toml\",\n)\n\nrust_library(\n    name = \"aes_gcm\",\n    deps = [\n        \"@rust_crates__aead-0.5.2//:aead\",\n        \"@rust_crates__aes-0.8.4//:aes\",\n        \"@rust_crates__cipher-0.4.4//:cipher\",\n        \"@rust_crates__ctr-0.9.2//:ctr\",\n        \"@rust_crates__ghash-0.5.1//:ghash\",\n        \"@rust_crates__subtle-2.6.1//:subtle\",\n    ],\n    compile_data = glob(\n        allow_empty = True,\n        include = [\"**\"],\n        exclude = [\n            \"**/* *\",\n            \".tmp_git_root/**/*\",\n            \"BUILD\",\n            \"BUILD.bazel\",\n            \"WORKSPACE\",\n            \"WORKSPACE.bazel\",\n        ],\n    ),\n    crate_features = [\n        \"aes\",\n    ],\n    crate_root = \"src/lib.rs\",\n    edition = \"2021\",\n    rustc_env_files = [\n        \":cargo_toml_env_vars\",\n    ],\n    rustc_flags = [\n        \"--cap-lints=allow\",\n    ],\n    srcs = glob(\n        allow_empty = True,\n        include = [\"**/*.rs\"],\n    ),\n    tags = [\n        \"cargo-bazel\",\n        \"crate-name=aes-gcm\",\n        \"manual\",\n        \"noclippy\",\n        \"norustfmt\",\n    ],\n    target_compatible_with = select({\n        \"@rules_rust//rust/platform:aarch64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\": [],\n        \"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\": [],\n        \"@rules_rust//rust/platform:x86_64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\": [],\n        \"//conditions:default\": [\"@platforms//:incompatible\"],\n    }),\n    version = \"0.10.3\",\n)\n"
             }
           },
+          "rust_crates__aligned-0.4.3": {
+            "repoRuleId": "@@bazel_tools//tools/build_defs/repo:http.bzl%http_archive",
+            "attributes": {
+              "patch_args": [],
+              "patch_tool": "",
+              "patches": [],
+              "remote_patch_strip": 1,
+              "sha256": "ee4508988c62edf04abd8d92897fca0c2995d907ce1dfeaf369dac3716a40685",
+              "type": "tar.gz",
+              "urls": [
+                "https://static.crates.io/crates/aligned/0.4.3/download"
+              ],
+              "strip_prefix": "aligned-0.4.3",
+              "build_file_content": "###############################################################################\n# @generated\n# DO NOT MODIFY: This file is auto-generated by a crate_universe tool. To \n# regenerate this file, run the following:\n#\n#     bazel mod show_repo 'openprot'\n###############################################################################\n\nload(\"@rules_rust//cargo:defs.bzl\", \"cargo_toml_env_vars\")\n\nload(\"@rules_rust//rust:defs.bzl\", \"rust_library\")\n\n# buildifier: disable=bzl-visibility\nload(\"@rules_rust//crate_universe/private:selects.bzl\", \"selects\")\n\npackage(default_visibility = [\"//visibility:public\"])\n\ncargo_toml_env_vars(\n    name = \"cargo_toml_env_vars\",\n    src = \"Cargo.toml\",\n)\n\nrust_library(\n    name = \"aligned\",\n    deps = [\n        \"@rust_crates__as-slice-0.2.1//:as_slice\",\n    ],\n    compile_data = glob(\n        allow_empty = True,\n        include = [\"**\"],\n        exclude = [\n            \"**/* *\",\n            \".tmp_git_root/**/*\",\n            \"BUILD\",\n            \"BUILD.bazel\",\n            \"WORKSPACE\",\n            \"WORKSPACE.bazel\",\n        ],\n    ),\n    crate_root = \"src/lib.rs\",\n    edition = \"2024\",\n    rustc_env_files = [\n        \":cargo_toml_env_vars\",\n    ],\n    rustc_flags = [\n        \"--cap-lints=allow\",\n    ],\n    srcs = glob(\n        allow_empty = True,\n        include = [\"**/*.rs\"],\n    ),\n    tags = [\n        \"cargo-bazel\",\n        \"crate-name=aligned\",\n        \"manual\",\n        \"noclippy\",\n        \"norustfmt\",\n    ],\n    target_compatible_with = select({\n        \"@rules_rust//rust/platform:aarch64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\": [],\n        \"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\": [],\n        \"@rules_rust//rust/platform:x86_64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\": [],\n        \"//conditions:default\": [\"@platforms//:incompatible\"],\n    }),\n    version = \"0.4.3\",\n)\n"
+            }
+          },
           "rust_crates__anstream-0.6.21": {
             "repoRuleId": "@@bazel_tools//tools/build_defs/repo:http.bzl%http_archive",
             "attributes": {
@@ -2194,6 +2210,22 @@
               "build_file_content": "###############################################################################\n# @generated\n# DO NOT MODIFY: This file is auto-generated by a crate_universe tool. To \n# regenerate this file, run the following:\n#\n#     bazel mod show_repo 'openprot'\n###############################################################################\n\nload(\n    \"@rules_rust//cargo:defs.bzl\",\n    \"cargo_build_script\",\n    \"cargo_toml_env_vars\",\n)\n\nload(\"@rules_rust//rust:defs.bzl\", \"rust_library\")\n\n# buildifier: disable=bzl-visibility\nload(\"@rules_rust//crate_universe/private:selects.bzl\", \"selects\")\n\npackage(default_visibility = [\"//visibility:public\"])\n\ncargo_toml_env_vars(\n    name = \"cargo_toml_env_vars\",\n    src = \"Cargo.toml\",\n)\n\nrust_library(\n    name = \"anyhow\",\n    deps = [\n        \"@rust_crates__anyhow-1.0.102//:build_script_build\",\n    ],\n    compile_data = glob(\n        allow_empty = True,\n        include = [\"**\"],\n        exclude = [\n            \"**/* *\",\n            \".tmp_git_root/**/*\",\n            \"BUILD\",\n            \"BUILD.bazel\",\n            \"WORKSPACE\",\n            \"WORKSPACE.bazel\",\n        ],\n    ),\n    crate_features = [\n        \"default\",\n        \"std\",\n    ],\n    crate_root = \"src/lib.rs\",\n    edition = \"2021\",\n    rustc_env_files = [\n        \":cargo_toml_env_vars\",\n    ],\n    rustc_flags = [\n        \"--cap-lints=allow\",\n    ],\n    srcs = glob(\n        allow_empty = True,\n        include = [\"**/*.rs\"],\n    ),\n    tags = [\n        \"cargo-bazel\",\n        \"crate-name=anyhow\",\n        \"manual\",\n        \"noclippy\",\n        \"norustfmt\",\n    ],\n    target_compatible_with = select({\n        \"@rules_rust//rust/platform:aarch64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\": [],\n        \"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\": [],\n        \"@rules_rust//rust/platform:x86_64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\": [],\n        \"//conditions:default\": [\"@platforms//:incompatible\"],\n    }),\n    version = \"1.0.102\",\n)\n\ncargo_build_script(\n    name = \"_bs\",\n    compile_data = glob(\n        allow_empty = True,\n        include = [\"**\"],\n        exclude = [\n            \"**/* *\",\n            \"**/*.rs\",\n            \".tmp_git_root/**/*\",\n            \"BUILD\",\n            \"BUILD.bazel\",\n            \"WORKSPACE\",\n            \"WORKSPACE.bazel\",\n        ],\n    ),\n    crate_features = [\n        \"default\",\n        \"std\",\n    ],\n    crate_name = \"build_script_build\",\n    crate_root = \"build.rs\",\n    data = glob(\n        allow_empty = True,\n        include = [\"**\"],\n        exclude = [\n            \"**/* *\",\n            \".tmp_git_root/**/*\",\n            \"BUILD\",\n            \"BUILD.bazel\",\n            \"WORKSPACE\",\n            \"WORKSPACE.bazel\",\n        ],\n    ),\n    edition = \"2021\",\n    pkg_name = \"anyhow\",\n    rustc_env_files = [\n        \":cargo_toml_env_vars\",\n    ],\n    rustc_flags = [\n        \"--cap-lints=allow\",\n    ],\n    srcs = glob(\n        allow_empty = True,\n        include = [\"**/*.rs\"],\n    ),\n    tags = [\n        \"cargo-bazel\",\n        \"crate-name=anyhow\",\n        \"manual\",\n        \"noclippy\",\n        \"norustfmt\",\n    ],\n    version = \"1.0.102\",\n    visibility = [\"//visibility:private\"],\n)\n\nalias(\n    name = \"build_script_build\",\n    actual = \":_bs\",\n    tags = [\"manual\"],\n)\n"
             }
           },
+          "rust_crates__as-slice-0.2.1": {
+            "repoRuleId": "@@bazel_tools//tools/build_defs/repo:http.bzl%http_archive",
+            "attributes": {
+              "patch_args": [],
+              "patch_tool": "",
+              "patches": [],
+              "remote_patch_strip": 1,
+              "sha256": "516b6b4f0e40d50dcda9365d53964ec74560ad4284da2e7fc97122cd83174516",
+              "type": "tar.gz",
+              "urls": [
+                "https://static.crates.io/crates/as-slice/0.2.1/download"
+              ],
+              "strip_prefix": "as-slice-0.2.1",
+              "build_file_content": "###############################################################################\n# @generated\n# DO NOT MODIFY: This file is auto-generated by a crate_universe tool. To \n# regenerate this file, run the following:\n#\n#     bazel mod show_repo 'openprot'\n###############################################################################\n\nload(\"@rules_rust//cargo:defs.bzl\", \"cargo_toml_env_vars\")\n\nload(\"@rules_rust//rust:defs.bzl\", \"rust_library\")\n\n# buildifier: disable=bzl-visibility\nload(\"@rules_rust//crate_universe/private:selects.bzl\", \"selects\")\n\npackage(default_visibility = [\"//visibility:public\"])\n\ncargo_toml_env_vars(\n    name = \"cargo_toml_env_vars\",\n    src = \"Cargo.toml\",\n)\n\nrust_library(\n    name = \"as_slice\",\n    deps = [\n        \"@rust_crates__stable_deref_trait-1.2.1//:stable_deref_trait\",\n    ],\n    compile_data = glob(\n        allow_empty = True,\n        include = [\"**\"],\n        exclude = [\n            \"**/* *\",\n            \".tmp_git_root/**/*\",\n            \"BUILD\",\n            \"BUILD.bazel\",\n            \"WORKSPACE\",\n            \"WORKSPACE.bazel\",\n        ],\n    ),\n    crate_root = \"src/lib.rs\",\n    edition = \"2015\",\n    rustc_env_files = [\n        \":cargo_toml_env_vars\",\n    ],\n    rustc_flags = [\n        \"--cap-lints=allow\",\n    ],\n    srcs = glob(\n        allow_empty = True,\n        include = [\"**/*.rs\"],\n    ),\n    tags = [\n        \"cargo-bazel\",\n        \"crate-name=as-slice\",\n        \"manual\",\n        \"noclippy\",\n        \"norustfmt\",\n    ],\n    target_compatible_with = select({\n        \"@rules_rust//rust/platform:aarch64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\": [],\n        \"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\": [],\n        \"@rules_rust//rust/platform:x86_64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\": [],\n        \"//conditions:default\": [\"@platforms//:incompatible\"],\n    }),\n    version = \"0.2.1\",\n)\n"
+            }
+          },
           "rust_crates__bare-metal-0.2.5": {
             "repoRuleId": "@@bazel_tools//tools/build_defs/repo:http.bzl%http_archive",
             "attributes": {
@@ -3890,6 +3922,22 @@
               "build_file_content": "###############################################################################\n# @generated\n# DO NOT MODIFY: This file is auto-generated by a crate_universe tool. To \n# regenerate this file, run the following:\n#\n#     bazel mod show_repo 'openprot'\n###############################################################################\n\nload(\"@rules_rust//cargo:defs.bzl\", \"cargo_toml_env_vars\")\n\nload(\"@rules_rust//rust:defs.bzl\", \"rust_library\")\n\n# buildifier: disable=bzl-visibility\nload(\"@rules_rust//crate_universe/private:selects.bzl\", \"selects\")\n\npackage(default_visibility = [\"//visibility:public\"])\n\ncargo_toml_env_vars(\n    name = \"cargo_toml_env_vars\",\n    src = \"Cargo.toml\",\n)\n\nrust_library(\n    name = \"subtle\",\n    compile_data = glob(\n        allow_empty = True,\n        include = [\"**\"],\n        exclude = [\n            \"**/* *\",\n            \".tmp_git_root/**/*\",\n            \"BUILD\",\n            \"BUILD.bazel\",\n            \"WORKSPACE\",\n            \"WORKSPACE.bazel\",\n        ],\n    ),\n    crate_features = [\n        \"i128\",\n    ],\n    crate_root = \"src/lib.rs\",\n    edition = \"2018\",\n    rustc_env_files = [\n        \":cargo_toml_env_vars\",\n    ],\n    rustc_flags = [\n        \"--cap-lints=allow\",\n    ],\n    srcs = glob(\n        allow_empty = True,\n        include = [\"**/*.rs\"],\n    ),\n    tags = [\n        \"cargo-bazel\",\n        \"crate-name=subtle\",\n        \"manual\",\n        \"noclippy\",\n        \"norustfmt\",\n    ],\n    target_compatible_with = select({\n        \"@rules_rust//rust/platform:aarch64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\": [],\n        \"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\": [],\n        \"@rules_rust//rust/platform:x86_64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\": [],\n        \"//conditions:default\": [\"@platforms//:incompatible\"],\n    }),\n    version = \"2.6.1\",\n)\n"
             }
           },
+          "rust_crates__syn-1.0.109": {
+            "repoRuleId": "@@bazel_tools//tools/build_defs/repo:http.bzl%http_archive",
+            "attributes": {
+              "patch_args": [],
+              "patch_tool": "",
+              "patches": [],
+              "remote_patch_strip": 1,
+              "sha256": "72b64191b275b66ffe2469e8af2c1cfe3bafa67b529ead792a6d0160888b4237",
+              "type": "tar.gz",
+              "urls": [
+                "https://static.crates.io/crates/syn/1.0.109/download"
+              ],
+              "strip_prefix": "syn-1.0.109",
+              "build_file_content": "###############################################################################\n# @generated\n# DO NOT MODIFY: This file is auto-generated by a crate_universe tool. To \n# regenerate this file, run the following:\n#\n#     bazel mod show_repo 'openprot'\n###############################################################################\n\nload(\n    \"@rules_rust//cargo:defs.bzl\",\n    \"cargo_build_script\",\n    \"cargo_toml_env_vars\",\n)\n\nload(\"@rules_rust//rust:defs.bzl\", \"rust_library\")\n\n# buildifier: disable=bzl-visibility\nload(\"@rules_rust//crate_universe/private:selects.bzl\", \"selects\")\n\npackage(default_visibility = [\"//visibility:public\"])\n\ncargo_toml_env_vars(\n    name = \"cargo_toml_env_vars\",\n    src = \"Cargo.toml\",\n)\n\nrust_library(\n    name = \"syn\",\n    deps = [\n        \"@rust_crates__proc-macro2-1.0.106//:proc_macro2\",\n        \"@rust_crates__quote-1.0.44//:quote\",\n        \"@rust_crates__syn-1.0.109//:build_script_build\",\n        \"@rust_crates__unicode-ident-1.0.24//:unicode_ident\",\n    ],\n    compile_data = glob(\n        allow_empty = True,\n        include = [\"**\"],\n        exclude = [\n            \"**/* *\",\n            \".tmp_git_root/**/*\",\n            \"BUILD\",\n            \"BUILD.bazel\",\n            \"WORKSPACE\",\n            \"WORKSPACE.bazel\",\n        ],\n    ),\n    crate_features = [\n        \"clone-impls\",\n        \"default\",\n        \"derive\",\n        \"full\",\n        \"parsing\",\n        \"printing\",\n        \"proc-macro\",\n        \"quote\",\n    ],\n    crate_root = \"src/lib.rs\",\n    edition = \"2018\",\n    rustc_env_files = [\n        \":cargo_toml_env_vars\",\n    ],\n    rustc_flags = [\n        \"--cap-lints=allow\",\n    ],\n    srcs = glob(\n        allow_empty = True,\n        include = [\"**/*.rs\"],\n    ),\n    tags = [\n        \"cargo-bazel\",\n        \"crate-name=syn\",\n        \"manual\",\n        \"noclippy\",\n        \"norustfmt\",\n    ],\n    target_compatible_with = select({\n        \"@rules_rust//rust/platform:aarch64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\": [],\n        \"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\": [],\n        \"@rules_rust//rust/platform:x86_64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\": [],\n        \"//conditions:default\": [\"@platforms//:incompatible\"],\n    }),\n    version = \"1.0.109\",\n)\n\ncargo_build_script(\n    name = \"_bs\",\n    compile_data = glob(\n        allow_empty = True,\n        include = [\"**\"],\n        exclude = [\n            \"**/* *\",\n            \"**/*.rs\",\n            \".tmp_git_root/**/*\",\n            \"BUILD\",\n            \"BUILD.bazel\",\n            \"WORKSPACE\",\n            \"WORKSPACE.bazel\",\n        ],\n    ),\n    crate_features = [\n        \"clone-impls\",\n        \"default\",\n        \"derive\",\n        \"full\",\n        \"parsing\",\n        \"printing\",\n        \"proc-macro\",\n        \"quote\",\n    ],\n    crate_name = \"build_script_build\",\n    crate_root = \"build.rs\",\n    data = glob(\n        allow_empty = True,\n        include = [\"**\"],\n        exclude = [\n            \"**/* *\",\n            \".tmp_git_root/**/*\",\n            \"BUILD\",\n            \"BUILD.bazel\",\n            \"WORKSPACE\",\n            \"WORKSPACE.bazel\",\n        ],\n    ),\n    edition = \"2018\",\n    pkg_name = \"syn\",\n    rustc_env_files = [\n        \":cargo_toml_env_vars\",\n    ],\n    rustc_flags = [\n        \"--cap-lints=allow\",\n    ],\n    srcs = glob(\n        allow_empty = True,\n        include = [\"**/*.rs\"],\n    ),\n    tags = [\n        \"cargo-bazel\",\n        \"crate-name=syn\",\n        \"manual\",\n        \"noclippy\",\n        \"norustfmt\",\n    ],\n    version = \"1.0.109\",\n    visibility = [\"//visibility:private\"],\n)\n\nalias(\n    name = \"build_script_build\",\n    actual = \":_bs\",\n    tags = [\"manual\"],\n)\n"
+            }
+          },
           "rust_crates__syn-2.0.116": {
             "repoRuleId": "@@bazel_tools//tools/build_defs/repo:http.bzl%http_archive",
             "attributes": {
@@ -4018,6 +4066,54 @@
               "build_file_content": "###############################################################################\n# @generated\n# DO NOT MODIFY: This file is auto-generated by a crate_universe tool. To \n# regenerate this file, run the following:\n#\n#     bazel mod show_repo 'openprot'\n###############################################################################\n\nload(\"@rules_rust//cargo:defs.bzl\", \"cargo_toml_env_vars\")\n\nload(\"@rules_rust//rust:defs.bzl\", \"rust_library\")\n\n# buildifier: disable=bzl-visibility\nload(\"@rules_rust//crate_universe/private:selects.bzl\", \"selects\")\n\npackage(default_visibility = [\"//visibility:public\"])\n\ncargo_toml_env_vars(\n    name = \"cargo_toml_env_vars\",\n    src = \"Cargo.toml\",\n)\n\nrust_library(\n    name = \"ucd_trie\",\n    compile_data = glob(\n        allow_empty = True,\n        include = [\"**\"],\n        exclude = [\n            \"**/* *\",\n            \".tmp_git_root/**/*\",\n            \"BUILD\",\n            \"BUILD.bazel\",\n            \"WORKSPACE\",\n            \"WORKSPACE.bazel\",\n        ],\n    ),\n    crate_features = [\n        \"std\",\n    ],\n    crate_root = \"src/lib.rs\",\n    edition = \"2021\",\n    rustc_env_files = [\n        \":cargo_toml_env_vars\",\n    ],\n    rustc_flags = [\n        \"--cap-lints=allow\",\n    ],\n    srcs = glob(\n        allow_empty = True,\n        include = [\"**/*.rs\"],\n    ),\n    tags = [\n        \"cargo-bazel\",\n        \"crate-name=ucd-trie\",\n        \"manual\",\n        \"noclippy\",\n        \"norustfmt\",\n    ],\n    target_compatible_with = select({\n        \"@rules_rust//rust/platform:aarch64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\": [],\n        \"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\": [],\n        \"@rules_rust//rust/platform:x86_64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\": [],\n        \"//conditions:default\": [\"@platforms//:incompatible\"],\n    }),\n    version = \"0.1.7\",\n)\n"
             }
           },
+          "rust_crates__ufmt-0.2.0": {
+            "repoRuleId": "@@bazel_tools//tools/build_defs/repo:http.bzl%http_archive",
+            "attributes": {
+              "patch_args": [],
+              "patch_tool": "",
+              "patches": [],
+              "remote_patch_strip": 1,
+              "sha256": "1a64846ec02b57e9108d6469d98d1648782ad6bb150a95a9baac26900bbeab9d",
+              "type": "tar.gz",
+              "urls": [
+                "https://static.crates.io/crates/ufmt/0.2.0/download"
+              ],
+              "strip_prefix": "ufmt-0.2.0",
+              "build_file_content": "###############################################################################\n# @generated\n# DO NOT MODIFY: This file is auto-generated by a crate_universe tool. To \n# regenerate this file, run the following:\n#\n#     bazel mod show_repo 'openprot'\n###############################################################################\n\nload(\"@rules_rust//cargo:defs.bzl\", \"cargo_toml_env_vars\")\n\nload(\"@rules_rust//rust:defs.bzl\", \"rust_library\")\n\n# buildifier: disable=bzl-visibility\nload(\"@rules_rust//crate_universe/private:selects.bzl\", \"selects\")\n\npackage(default_visibility = [\"//visibility:public\"])\n\ncargo_toml_env_vars(\n    name = \"cargo_toml_env_vars\",\n    src = \"Cargo.toml\",\n)\n\nrust_library(\n    name = \"ufmt\",\n    deps = [\n        \"@rust_crates__ufmt-write-0.1.0//:ufmt_write\",\n    ],\n    proc_macro_deps = [\n        \"@rust_crates__ufmt-macros-0.3.0//:ufmt_macros\",\n    ],\n    compile_data = glob(\n        allow_empty = True,\n        include = [\"**\"],\n        exclude = [\n            \"**/* *\",\n            \".tmp_git_root/**/*\",\n            \"BUILD\",\n            \"BUILD.bazel\",\n            \"WORKSPACE\",\n            \"WORKSPACE.bazel\",\n        ],\n    ),\n    crate_root = \"src/lib.rs\",\n    edition = \"2021\",\n    rustc_env_files = [\n        \":cargo_toml_env_vars\",\n    ],\n    rustc_flags = [\n        \"--cap-lints=allow\",\n    ],\n    srcs = glob(\n        allow_empty = True,\n        include = [\"**/*.rs\"],\n    ),\n    tags = [\n        \"cargo-bazel\",\n        \"crate-name=ufmt\",\n        \"manual\",\n        \"noclippy\",\n        \"norustfmt\",\n    ],\n    target_compatible_with = select({\n        \"@rules_rust//rust/platform:aarch64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\": [],\n        \"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\": [],\n        \"@rules_rust//rust/platform:x86_64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\": [],\n        \"//conditions:default\": [\"@platforms//:incompatible\"],\n    }),\n    version = \"0.2.0\",\n)\n"
+            }
+          },
+          "rust_crates__ufmt-macros-0.3.0": {
+            "repoRuleId": "@@bazel_tools//tools/build_defs/repo:http.bzl%http_archive",
+            "attributes": {
+              "patch_args": [],
+              "patch_tool": "",
+              "patches": [],
+              "remote_patch_strip": 1,
+              "sha256": "d337d3be617449165cb4633c8dece429afd83f84051024079f97ad32a9663716",
+              "type": "tar.gz",
+              "urls": [
+                "https://static.crates.io/crates/ufmt-macros/0.3.0/download"
+              ],
+              "strip_prefix": "ufmt-macros-0.3.0",
+              "build_file_content": "###############################################################################\n# @generated\n# DO NOT MODIFY: This file is auto-generated by a crate_universe tool. To \n# regenerate this file, run the following:\n#\n#     bazel mod show_repo 'openprot'\n###############################################################################\n\nload(\"@rules_rust//cargo:defs.bzl\", \"cargo_toml_env_vars\")\n\nload(\"@rules_rust//rust:defs.bzl\", \"rust_proc_macro\")\n\n# buildifier: disable=bzl-visibility\nload(\"@rules_rust//crate_universe/private:selects.bzl\", \"selects\")\n\npackage(default_visibility = [\"//visibility:public\"])\n\ncargo_toml_env_vars(\n    name = \"cargo_toml_env_vars\",\n    src = \"Cargo.toml\",\n)\n\nrust_proc_macro(\n    name = \"ufmt_macros\",\n    deps = [\n        \"@rust_crates__proc-macro2-1.0.106//:proc_macro2\",\n        \"@rust_crates__quote-1.0.44//:quote\",\n        \"@rust_crates__syn-1.0.109//:syn\",\n    ],\n    compile_data = glob(\n        allow_empty = True,\n        include = [\"**\"],\n        exclude = [\n            \"**/* *\",\n            \".tmp_git_root/**/*\",\n            \"BUILD\",\n            \"BUILD.bazel\",\n            \"WORKSPACE\",\n            \"WORKSPACE.bazel\",\n        ],\n    ),\n    crate_root = \"src/lib.rs\",\n    edition = \"2021\",\n    rustc_env_files = [\n        \":cargo_toml_env_vars\",\n    ],\n    rustc_flags = [\n        \"--cap-lints=allow\",\n    ],\n    srcs = glob(\n        allow_empty = True,\n        include = [\"**/*.rs\"],\n    ),\n    tags = [\n        \"cargo-bazel\",\n        \"crate-name=ufmt-macros\",\n        \"manual\",\n        \"noclippy\",\n        \"norustfmt\",\n    ],\n    target_compatible_with = select({\n        \"@rules_rust//rust/platform:aarch64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\": [],\n        \"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\": [],\n        \"@rules_rust//rust/platform:x86_64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\": [],\n        \"//conditions:default\": [\"@platforms//:incompatible\"],\n    }),\n    version = \"0.3.0\",\n)\n"
+            }
+          },
+          "rust_crates__ufmt-write-0.1.0": {
+            "repoRuleId": "@@bazel_tools//tools/build_defs/repo:http.bzl%http_archive",
+            "attributes": {
+              "patch_args": [],
+              "patch_tool": "",
+              "patches": [],
+              "remote_patch_strip": 1,
+              "sha256": "e87a2ed6b42ec5e28cc3b94c09982969e9227600b2e3dcbc1db927a84c06bd69",
+              "type": "tar.gz",
+              "urls": [
+                "https://static.crates.io/crates/ufmt-write/0.1.0/download"
+              ],
+              "strip_prefix": "ufmt-write-0.1.0",
+              "build_file_content": "###############################################################################\n# @generated\n# DO NOT MODIFY: This file is auto-generated by a crate_universe tool. To \n# regenerate this file, run the following:\n#\n#     bazel mod show_repo 'openprot'\n###############################################################################\n\nload(\"@rules_rust//cargo:defs.bzl\", \"cargo_toml_env_vars\")\n\nload(\"@rules_rust//rust:defs.bzl\", \"rust_library\")\n\n# buildifier: disable=bzl-visibility\nload(\"@rules_rust//crate_universe/private:selects.bzl\", \"selects\")\n\npackage(default_visibility = [\"//visibility:public\"])\n\ncargo_toml_env_vars(\n    name = \"cargo_toml_env_vars\",\n    src = \"Cargo.toml\",\n)\n\nrust_library(\n    name = \"ufmt_write\",\n    compile_data = glob(\n        allow_empty = True,\n        include = [\"**\"],\n        exclude = [\n            \"**/* *\",\n            \".tmp_git_root/**/*\",\n            \"BUILD\",\n            \"BUILD.bazel\",\n            \"WORKSPACE\",\n            \"WORKSPACE.bazel\",\n        ],\n    ),\n    crate_root = \"src/lib.rs\",\n    edition = \"2018\",\n    rustc_env_files = [\n        \":cargo_toml_env_vars\",\n    ],\n    rustc_flags = [\n        \"--cap-lints=allow\",\n    ],\n    srcs = glob(\n        allow_empty = True,\n        include = [\"**/*.rs\"],\n    ),\n    tags = [\n        \"cargo-bazel\",\n        \"crate-name=ufmt-write\",\n        \"manual\",\n        \"noclippy\",\n        \"norustfmt\",\n    ],\n    target_compatible_with = select({\n        \"@rules_rust//rust/platform:aarch64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\": [],\n        \"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\": [],\n        \"@rules_rust//rust/platform:x86_64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\": [],\n        \"//conditions:default\": [\"@platforms//:incompatible\"],\n    }),\n    version = \"0.1.0\",\n)\n"
+            }
+          },
           "rust_crates__unicode-ident-1.0.24": {
             "repoRuleId": "@@bazel_tools//tools/build_defs/repo:http.bzl%http_archive",
             "attributes": {
diff --git a/hal/blocking/usb/BUILD.bazel b/hal/blocking/usb/BUILD.bazel
new file mode 100644
index 00000000..e9989f4c
--- /dev/null
+++ b/hal/blocking/usb/BUILD.bazel
@@ -0,0 +1,27 @@
+load("@rules_rust//rust:defs.bzl", "rust_library", "rust_test")
+
+rust_library(
+    name = "hal_usb",
+    srcs = [
+        "descriptor.rs",
+        "driver.rs",
+        "lib.rs",
+    ],
+    crate_name = "hal_usb",
+    edition = "2024",
+    visibility = ["//visibility:public"],
+    deps = [
+        "@rust_crates//:aligned",
+        "@rust_crates//:ufmt",
+        "@rust_crates//:zerocopy",
+    ],
+)
+
+rust_test(
+    name = "hal_usb_test",
+    crate = ":hal_usb",
+    rustc_flags = [
+        "-C",
+        "debug-assertions",
+    ],
+)
diff --git a/hal/blocking/usb/descriptor.rs b/hal/blocking/usb/descriptor.rs
new file mode 100644
index 00000000..e0f06c30
--- /dev/null
+++ b/hal/blocking/usb/descriptor.rs
@@ -0,0 +1,760 @@
+use aligned::Aligned;
+use aligned::A4;
+use ufmt::uWrite;
+
+pub const USB_CLASS_AUDIO: u8 = 0x01;
+pub const USB_CLASS_COMMUNIATIONS: u8 = 0x02;
+pub const USB_CLASS_HID: u8 = 0x03;
+pub const USB_CLASS_PHYSICAL: u8 = 0x05;
+pub const USB_CLASS_IMAGE: u8 = 0x06;
+pub const USB_CLASS_PRINTER: u8 = 0x07;
+pub const USB_CLASS_MASS_STORAGE: u8 = 0x08;
+pub const USB_CLASS_HUB: u8 = 0x09;
+pub const USB_CLASS_CDC_DATA: u8 = 0x0a;
+pub const USB_CLASS_SMART_CARD: u8 = 0x0b;
+pub const USB_CLASS_CONTENT_SECURITY: u8 = 0x0d;
+pub const USB_CLASS_VIDEO: u8 = 0x0e;
+pub const USB_CLASS_PERSONAL_HEALTHCARE: u8 = 0x0f;
+pub const USB_CLASS_AUDIO_VIDEO: u8 = 0x10;
+pub const USB_CLASS_BILLBOARD: u8 = 0x11;
+pub const USB_CLASS_USB_TYPEC_BRIDGE: u8 = 0x12;
+pub const USB_CLASS_BULK_DISPLAY: u8 = 0x13;
+pub const USB_CLASS_MCTP: u8 = 0x14;
+pub const USB_CLASS_I3C: u8 = 0x3c;
+pub const USB_CLASS_DIAGNOSTIC_DEVICE: u8 = 0xdc;
+pub const USB_CLASS_WIRELESS_CONTROLLER: u8 = 0xe0;
+pub const USB_CLASS_MISC: u8 = 0xef;
+pub const USB_CLASS_APPLICATION_SPECIFIC: u8 = 0xfe;
+pub const USB_CLASS_VENDOR: u8 = 0xff;
+
+pub const USB_SUBCLASS_APPLICATION_SPECIFIC_DFU: u8 = 0x01;
+
+pub const USB_PROTOCOL_APPLICATION_SPECIFIC_DFU_RUNTIME_MODE: u8 = 0x01;
+pub const USB_PROTOCOL_APPLICATION_SPECIFIC_DFU_DFU_MODE: u8 = 0x02;
+
+use crate::DescriptorType;
+use crate::Direction;
+
+#[derive(Clone, Copy, Eq, PartialEq)]
+#[repr(transparent)]
+pub struct StringHandle(pub u8);
+impl StringHandle {
+    pub const NONE: Self = StringHandle(0);
+}
+
+pub struct DeviceDescriptor {
+    pub device_class: DeviceClass,
+    pub device_sub_class: u8,
+    pub device_protocol: u8,
+    pub max_packet_size: u8,
+    pub vendor_id: u16,
+    pub product_id: u16,
+    pub device_release_num: u16,
+    pub manufacturer: StringHandle,
+    pub product: StringHandle,
+    pub serial_num: StringHandle,
+}
+impl DeviceDescriptor {
+    const SIZE: usize = 18;
+
+    #[allow(dead_code)]
+    pub(crate) const fn total_size(&self) -> usize {
+        Self::SIZE
+    }
+
+    #[allow(clippy::identity_op)]
+    pub const fn serialize(&self) -> [u8; Self::SIZE] {
+        let mut buf = [0u8; Self::SIZE];
+
+        // sizeof descriptor
+        buf[0] = 18;
+        // bDescriptorType = Device
+        buf[1] = 1;
+        // USB version 2.0
+        buf[2] = 0x00;
+        buf[3] = 0x02;
+
+        buf[4] = self.device_class.0;
+        buf[5] = self.device_sub_class;
+        buf[6] = self.device_protocol;
+        buf[7] = self.max_packet_size;
+
+        buf[8] = ((self.vendor_id & 0x00ff) >> 0) as u8;
+        buf[9] = ((self.vendor_id & 0xff00) >> 8) as u8;
+
+        buf[10] = ((self.product_id & 0x00ff) >> 0) as u8;
+        buf[11] = ((self.product_id & 0xff00) >> 8) as u8;
+
+        buf[12] = ((self.device_release_num & 0x00ff) >> 0) as u8;
+        buf[13] = ((self.device_release_num & 0xff00) >> 8) as u8;
+
+        buf[14] = self.manufacturer.0;
+        buf[15] = self.product.0;
+        buf[16] = self.serial_num.0;
+
+        // num configurations
+        buf[17] = 1;
+        buf
+    }
+}
+
+pub struct ConfigDescriptor {
+    pub configuration_value: u8,
+    // in 2 mA units
+    pub max_power: u8,
+    pub self_powered: bool,
+    pub remote_wakeup: bool,
+    pub interfaces: &'static [InterfaceDescriptor],
+}
+
+impl ConfigDescriptor {
+    const SIZE: usize = 9;
+
+    pub const fn total_size(&self) -> usize {
+        let mut result = Self::SIZE;
+        let mut i = 0;
+        while i < self.interfaces.len() {
+            result += self.interfaces[i].total_size();
+            i += 1;
+        }
+        result
+    }
+
+    #[allow(clippy::identity_op)]
+    pub const fn serialize<const RESULT_SIZE: usize>(&self) -> [u8; RESULT_SIZE] {
+        assert!(self.total_size() == RESULT_SIZE);
+        let mut buf = [0u8; RESULT_SIZE];
+
+        // alternates don't count towards total
+        // as interfaces numbers are per spec monotonically increasing, we can use that as the count
+        let mut uniq_interface_count = 0;
+        let mut i = 0;
+        while i < self.interfaces.len() {
+            if self.interfaces[i].interface_number + 1 > uniq_interface_count {
+                uniq_interface_count = self.interfaces[i].interface_number + 1
+            }
+            i += 1;
+        }
+
+        // sizeof descriptor
+        buf[0] = 9;
+        // bDescriptorType = Configuration
+        buf[1] = 2;
+        buf[2] = ((RESULT_SIZE & 0x00ff) >> 0) as u8;
+        buf[3] = ((RESULT_SIZE & 0xff00) >> 8) as u8;
+        buf[4] = uniq_interface_count;
+        buf[5] = self.configuration_value;
+        // iConfiguration
+        buf[6] = 0;
+        buf[7] = (1 << 7) | // must be 1 (USB 1.0 bus powered)
+                 if self.self_powered { 1 << 6 } else { 0 } |
+                 if self.remote_wakeup { 1 << 5 } else { 0 };
+        buf[8] = self.max_power;
+
+        let mut offset = 9;
+
+        let mut i = 0;
+        while i < self.interfaces.len() {
+            let (iface_buf, iface_buf_len) = self.interfaces[i].serialize::<RESULT_SIZE>();
+            let mut iface_offset = 0;
+            while iface_offset < iface_buf_len {
+                buf[offset] = iface_buf[iface_offset];
+                iface_offset += 1;
+                offset += 1;
+            }
+            i += 1;
+        }
+        buf
+    }
+}
+
+pub struct InterfaceDescriptor {
+    pub name: StringHandle,
+    pub alternate_setting: u8,
+    pub interface_number: u8,
+    pub interface_class: u8,
+    pub interface_sub_class: u8,
+    pub interface_protocol: u8,
+    pub func_descs: &'static [FunctionalDescriptor],
+    pub endpoints: &'static [EndpointDescriptor],
+}
+impl InterfaceDescriptor {
+    const SIZE: usize = 9;
+
+    const fn total_size(&self) -> usize {
+        let mut result = Self::SIZE;
+        let mut i = 0;
+        while i < self.func_descs.len() {
+            result += self.func_descs[i].total_size();
+            i += 1;
+        }
+        let mut i = 0;
+        while i < self.endpoints.len() {
+            result += self.endpoints[i].total_size();
+            i += 1;
+        }
+        result
+    }
+    pub const fn serialize<const RESULT_SIZE: usize>(&self) -> ([u8; RESULT_SIZE], usize) {
+        assert!(RESULT_SIZE >= self.total_size());
+
+        let mut buf = [0u8; RESULT_SIZE];
+
+        // sizeof descriptor
+        buf[0] = 9;
+        // bDescriptorType = Interface
+        buf[1] = 4;
+        buf[2] = self.interface_number;
+        buf[3] = self.alternate_setting;
+        buf[4] = self.endpoints.len() as u8;
+        buf[5] = self.interface_class;
+        buf[6] = self.interface_sub_class;
+        buf[7] = self.interface_protocol;
+        // iInterface: Index of string descriptor describing this interface
+        buf[8] = self.name.0;
+        let mut offset = 9;
+
+        let mut i = 0;
+        while i < self.func_descs.len() {
+            self.func_descs[i].serialize(&mut buf, offset);
+            offset += self.func_descs[i].total_size();
+            i += 1;
+        }
+
+        let mut i = 0;
+        while i < self.endpoints.len() {
+            let ep_buf = self.endpoints[i].serialize(i as u8);
+            let mut ep_offset = 0;
+            while ep_offset < ep_buf.len() {
+                buf[offset] = ep_buf[ep_offset];
+                offset += 1;
+                ep_offset += 1;
+            }
+            i += 1;
+        }
+        (buf, offset)
+    }
+}
+
+pub struct EndpointDescriptor {
+    pub direction: Direction,
+    pub endpoint_num: u8,
+    pub transfer_type: TransferType,
+    pub max_packet_size: u16,
+    pub interval: u8,
+}
+impl EndpointDescriptor {
+    const SIZE: usize = 7;
+
+    const fn total_size(&self) -> usize {
+        Self::SIZE
+    }
+
+    #[allow(clippy::identity_op)]
+    const fn serialize(&self, _index: u8) -> [u8; Self::SIZE] {
+        let mut buf = [0u8; Self::SIZE];
+
+        // sizeof descriptor
+        buf[0] = Self::SIZE as u8;
+        // bDescriptorType = endpoint
+        buf[1] = 5;
+        buf[2] = self.endpoint_num & 0x7
+            | match self.direction {
+                Direction::HostToDevice => 0,
+                Direction::DeviceToHost => 1 << 7,
+            };
+        buf[3] = match self.transfer_type {
+            TransferType::Control => 0,
+            TransferType::Isochronous(sync_type, usage_type) => {
+                1 | match sync_type {
+                    SynchronizationType::None => 0 << 2,
+                    SynchronizationType::Asynchronous => 1 << 2,
+                    SynchronizationType::Adaptive => 2 << 2,
+                    SynchronizationType::Synchronous => 3 << 3,
+                } | match usage_type {
+                    UsageType::DataEndpoint => 0 << 4,
+                    UsageType::FeedbackEndpoint => 1 << 4,
+                    UsageType::ExplicitFeedbackDataEndpoint => 2 << 4,
+                }
+            }
+            TransferType::Bulk => 2,
+            TransferType::Interrupt => 3,
+        };
+
+        buf[4] = ((self.max_packet_size & 0x00ff) >> 0) as u8;
+        buf[5] = ((self.max_packet_size & 0xff00) >> 8) as u8;
+        buf[6] = self.interval;
+        buf
+    }
+}
+
+pub struct StringDescriptor0 {
+    pub langs: &'static [u16],
+}
+impl StringDescriptor0 {
+    pub const fn total_size(&self) -> usize {
+        2 + core::mem::size_of_val(self.langs)
+    }
+
+    #[allow(clippy::identity_op)]
+    pub const fn serialize<const RESULT_SIZE: usize>(&self) -> [u8; RESULT_SIZE] {
+        assert!(RESULT_SIZE == self.total_size());
+        assert!(self.total_size() <= (u8::MAX as usize));
+
+        let mut buf = [0u8; RESULT_SIZE];
+        // sizeof descriptor
+        buf[0] = self.total_size() as u8;
+        // bDescriptorType = String
+        buf[1] = 3;
+
+        let mut offset = 2;
+        let mut i = 0;
+        while i < self.langs.len() {
+            let bytes = self.langs[i].to_le_bytes();
+            buf[offset + 0] = bytes[0];
+            buf[offset + 1] = bytes[1];
+            i += 1;
+            offset += 2;
+        }
+        buf
+    }
+}
+
+#[derive(Clone, Copy, Debug)]
+#[allow(dead_code)]
+pub enum TransferType {
+    Control,
+    Isochronous(SynchronizationType, UsageType),
+    Bulk,
+    Interrupt,
+}
+impl TransferType {
+    #[allow(dead_code)]
+    fn as_eptyp(self) -> u32 {
+        match self {
+            TransferType::Control => 0,
+            TransferType::Isochronous(_, _) => 1,
+            TransferType::Bulk => 2,
+            TransferType::Interrupt => 3,
+        }
+    }
+}
+
+#[derive(Clone, Copy, Debug)]
+#[allow(dead_code)]
+pub enum SynchronizationType {
+    None = 0,
+    Asynchronous = 1,
+    Adaptive = 2,
+    Synchronous = 3,
+}
+
+#[derive(Clone, Copy, Debug)]
+#[allow(dead_code, clippy::enum_variant_names)]
+pub enum UsageType {
+    DataEndpoint,
+    FeedbackEndpoint,
+    ExplicitFeedbackDataEndpoint,
+}
+
+pub struct DeviceClass(pub u8);
+impl DeviceClass {
+    pub const SPECIFIED_BY_INTERFACE: Self = Self(0x00);
+    pub const COMMUNICATIONS_AND_CDC: Self = Self(0x02);
+    pub const HUB: Self = Self(0x09);
+    pub const BILLBOARD: Self = Self(0x11);
+    pub const DIAGNOSTIC_DEVICE: Self = Self(0x3c);
+    pub const MISCELLANEOUS: Self = Self(0xef);
+    pub const VENDOR_SPECIFIED: Self = Self(0xff);
+}
+impl From<DeviceClass> for u8 {
+    fn from(val: DeviceClass) -> Self {
+        val.0
+    }
+}
+
+pub struct StringDescriptor<const BYTE_LEN: usize>(Aligned<A4, [u8; BYTE_LEN]>);
+
+impl<const BYTE_LEN: usize> StringDescriptor<BYTE_LEN> {
+    pub const fn const_from_ascii(s: &str) -> Self {
+        assert!(BYTE_LEN <= (u8::MAX as usize));
+        assert!(s.len() * 2 + 2 == BYTE_LEN);
+        let mut result = [0u8; BYTE_LEN];
+        result[0] = BYTE_LEN as u8;
+        result[1] = 0x03; // DescriptorType string
+
+        let s = s.as_bytes();
+        let mut i = 0;
+        while i < s.len() {
+            if s[i] >= 0x80 {
+                panic!("ascii characters only");
+            }
+            result[2 + i * 2] = s[i];
+            i += 1;
+        }
+        StringDescriptor(Aligned(result))
+    }
+    pub const fn as_ref(&self) -> StringDescriptorRef<'_> {
+        StringDescriptorRef(&self.0)
+    }
+}
+
+#[derive(Clone, Copy)]
+pub struct StringDescriptorRef<'a>(pub &'a Aligned<A4, [u8]>);
+impl<'a> StringDescriptorRef<'a> {
+    pub const fn as_bytes(self) -> &'a Aligned<A4, [u8]> {
+        self.0
+    }
+}
+
+#[macro_export]
+macro_rules! string_descriptor {
+    ($s:expr) => {
+        $crate::StringDescriptor::<{ $s.len() * 2 + 2 }>::const_from_ascii($s)
+    };
+}
+
+#[derive(Debug)]
+pub enum DescriptorErr {
+    Overflow,
+    Encoding,
+}
+
+#[inline(always)]
+pub fn hex_utf16_descriptor(dest: &mut [u8], src: &[u8]) -> Result<usize, DescriptorErr> {
+    const { assert!(cfg!(target_endian = "little")) };
+    const HEX_CHARS: [u8; 16] = *b"0123456789abcdef";
+    let total_len = src.len() * 4 + 2;
+    if dest.len() < total_len || total_len > 255 {
+        return Err(DescriptorErr::Overflow);
+    }
+    dest[0] = total_len as u8;
+    dest[1] = DescriptorType::STRING.0;
+
+    let mut i = 2;
+    for src_byte in src.iter() {
+        dest[i] = HEX_CHARS[usize::from(*src_byte >> 4)];
+        dest[i + 1] = 0;
+        dest[i + 2] = HEX_CHARS[usize::from(*src_byte & 0xf)];
+        dest[i + 3] = 0;
+        i += 4;
+    }
+    Ok(total_len)
+}
+
+#[inline(always)]
+pub fn hex_utf16_descriptor_aligned<'a>(
+    dest: &'a mut Aligned<A4, [u8]>,
+    src: &[u8],
+) -> Result<StringDescriptorRef<'a>, DescriptorErr> {
+    let len = hex_utf16_descriptor(dest, src)?;
+    Ok(StringDescriptorRef(&dest[..len]))
+}
+
+pub struct StringDescriptorWritter<'a> {
+    buf: &'a mut Aligned<A4, [u8]>,
+    index: usize,
+}
+impl<'a> StringDescriptorWritter<'a> {
+    pub fn new(buf: &'a mut Aligned<A4, [u8]>) -> Result<Self, DescriptorErr> {
+        if buf.len() < 2 || buf.len() > 2 + 255 {
+            return Err(DescriptorErr::Overflow);
+        }
+        *buf.get_mut(1).unwrap() = DescriptorType::STRING.0;
+        Ok(StringDescriptorWritter { buf, index: 2 })
+    }
+    pub fn finalize(self) -> Result<StringDescriptorRef<'a>, DescriptorErr> {
+        *self.buf.get_mut(0).ok_or(DescriptorErr::Overflow)? =
+            u8::try_from(self.index).map_err(|_| DescriptorErr::Overflow)?;
+
+        if self.index > self.buf.len() {
+            return Err(DescriptorErr::Overflow);
+        }
+        Ok(StringDescriptorRef(&self.buf[..self.index]))
+    }
+}
+impl uWrite for StringDescriptorWritter<'_> {
+    type Error = core::fmt::Error;
+
+    fn write_str(&mut self, s: &str) -> Result<(), Self::Error> {
+        let bytes = s.as_bytes();
+        let remaining_buf = self.buf.get_mut(self.index..).ok_or(core::fmt::Error)?;
+
+        if remaining_buf.len() < bytes.len() * 2 {
+            return Err(core::fmt::Error);
+        }
+
+        for &b in bytes {
+            if b >= 0x80 {
+                return Err(core::fmt::Error);
+            }
+            *self.buf.get_mut(self.index).ok_or(core::fmt::Error)? = b;
+            *self.buf.get_mut(self.index + 1).ok_or(core::fmt::Error)? = 0;
+            self.index += 2;
+        }
+
+        Ok(())
+    }
+}
+
+#[cfg(test)]
+mod test_string_descriptor_writter {
+    use aligned::Aligned;
+    use aligned::A4;
+    use core::ops::Deref;
+    use ufmt::uwrite;
+
+    use crate::StringDescriptorWritter;
+
+    #[test]
+    fn works() {
+        let mut buf = Aligned::<A4, _>([0u8; 30]);
+        let mut writter = StringDescriptorWritter::new(&mut buf).unwrap();
+        uwrite!(writter, "Hello").unwrap();
+        uwrite!(writter, " ").unwrap();
+        uwrite!(writter, "World").unwrap();
+        let result = writter.finalize().unwrap();
+        assert_eq!(
+            result.as_bytes().deref(),
+            &[
+                24, 3, b'H', 0, b'e', 0, b'l', 0, b'l', 0, b'o', 0, b' ', 0, b'W', 0, b'o', 0,
+                b'r', 0, b'l', 0, b'd', 0
+            ]
+        );
+    }
+
+    #[test]
+    fn too_small_buffer() {
+        let mut buf = Aligned::<A4, _>([0u8; 1]);
+        assert!(StringDescriptorWritter::new(&mut buf).is_err());
+    }
+
+    #[test]
+    fn too_big_buffer() {
+        let mut buf = Aligned::<A4, _>([0u8; 258]);
+        assert!(StringDescriptorWritter::new(&mut buf).is_err());
+    }
+
+    #[test]
+    fn too_small_to_fit() {
+        let mut buf = Aligned::<A4, _>([0u8; 12]);
+        let mut writter = StringDescriptorWritter::new(&mut buf).unwrap();
+        uwrite!(writter, "Hello").unwrap();
+        assert!(uwrite!(writter, " ").is_err());
+    }
+
+    #[test]
+    fn non_ascii_char() {
+        let mut buf = Aligned::<A4, _>([0u8; 20]);
+        let mut writter = StringDescriptorWritter::new(&mut buf).unwrap();
+        assert!(uwrite!(writter, "Héllö").is_err());
+    }
+}
+
+pub struct DfuFunctionalDescriptor {
+    /// New firmware can be received from the host
+    pub can_download: bool,
+    /// Current firmware can be sent back to the host
+    pub can_upload: bool,
+    /// Device can still communicate with the host after the manifestation phase.
+    pub manifestation_tolerant: bool,
+    /// Device will detach from the USB bus autonomously after receiving
+    /// DFU_DETACH; the host does not need to explicitly issue a bus reset.
+    pub will_detach: bool,
+    /// Timeout the device will wait to be reset by host after receiving DFU_DETACH.
+    pub detach_timeout_ms: u16,
+    /// The number of bytes the device can receive per control request.
+    pub transfer_size: u16,
+}
+impl DfuFunctionalDescriptor {
+    pub const fn total_size(&self) -> usize {
+        9
+    }
+    pub const fn serialize(&self, dest: &mut [u8], offset: usize) {
+        const fn bit(index: u8, val: bool) -> u8 {
+            (if val { 1 } else { 0 }) << index
+        }
+        const fn copy_u16(dest: &mut [u8], index: usize, val: u16) {
+            let bytes = val.to_le_bytes();
+            dest[index] = bytes[0];
+            dest[index + 1] = bytes[1];
+        }
+        // sizeof descriptor
+        dest[offset] = 9;
+        // bDescriptorType = DFU Functional
+        dest[offset + 1] = 0x21;
+        // bmAttributes
+        dest[offset + 2] = bit(0, self.can_download)
+            | bit(1, self.can_upload)
+            | bit(2, self.manifestation_tolerant)
+            | bit(3, self.will_detach);
+        copy_u16(dest, offset + 3, self.detach_timeout_ms);
+        copy_u16(dest, offset + 5, self.transfer_size);
+        // bcdDFUVersion
+        copy_u16(dest, offset + 7, 0x0100);
+    }
+}
+
+// This should be a trait, but traits can't be used from const functions :(
+pub enum FunctionalDescriptor {
+    Dfu(DfuFunctionalDescriptor),
+}
+
+impl FunctionalDescriptor {
+    pub const fn total_size(&self) -> usize {
+        match self {
+            Self::Dfu(dfu) => dfu.total_size(),
+        }
+    }
+    #[allow(clippy::identity_op)]
+    pub const fn serialize(&self, dest: &mut [u8], offset: usize) {
+        assert!(offset + self.total_size() <= dest.len());
+        match self {
+            Self::Dfu(dfu) => dfu.serialize(dest, offset),
+        }
+    }
+}
+
+#[cfg(test)]
+mod tests {
+
+    use super::*;
+
+    const INTERFACE_NAME_HANDLE: StringHandle = StringHandle(5);
+
+    const CONFIG_DESC: ConfigDescriptor = ConfigDescriptor {
+        configuration_value: 1,
+        max_power: 250,
+        self_powered: false,
+        remote_wakeup: false,
+        interfaces: &[InterfaceDescriptor {
+            name: INTERFACE_NAME_HANDLE,
+            interface_number: 0,
+            alternate_setting: 0,
+            interface_class: 0xff,
+            interface_sub_class: 0xff,
+            interface_protocol: 0xff,
+            func_descs: &[],
+            endpoints: &[
+                EndpointDescriptor {
+                    direction: Direction::DeviceToHost,
+                    endpoint_num: 1,
+                    transfer_type: TransferType::Bulk,
+                    max_packet_size: 64,
+                    interval: 0,
+                },
+                EndpointDescriptor {
+                    direction: Direction::HostToDevice,
+                    endpoint_num: 2,
+                    transfer_type: TransferType::Bulk,
+                    max_packet_size: 64,
+                    interval: 0,
+                },
+            ],
+        }],
+    };
+    const CONFIG_DESC_RAW: [u8; CONFIG_DESC.total_size()] = CONFIG_DESC.serialize();
+
+    #[test]
+    fn test_config_desc() {
+        assert_eq!(
+            &CONFIG_DESC_RAW,
+            &[
+                0x09, 0x02, 0x20, 0x00, 0x01, 0x01, 0x00, 0x80, 0xfa, 0x09, 0x04, 0x00, 0x00, 0x02,
+                0xff, 0xff, 0xff, 0x05, 0x07, 0x05, 0x81, 0x02, 0x40, 0x00, 0x00, 0x07, 0x05, 0x02,
+                0x02, 0x40, 0x00, 0x00
+            ]
+        )
+    }
+
+    #[test]
+    fn test_config_desc_dfu() {
+        const CONFIG_DESC_DFU: ConfigDescriptor = ConfigDescriptor {
+            configuration_value: 1,
+            max_power: 250,
+            self_powered: false,
+            remote_wakeup: false,
+            interfaces: &[InterfaceDescriptor {
+                name: INTERFACE_NAME_HANDLE,
+                interface_number: 0,
+                alternate_setting: 0,
+                interface_class: 0xfe,
+                interface_sub_class: 0x01,
+                interface_protocol: 0x02,
+                func_descs: &[FunctionalDescriptor::Dfu(DfuFunctionalDescriptor {
+                    can_download: true,
+                    can_upload: false,
+                    manifestation_tolerant: true,
+                    will_detach: true,
+                    transfer_size: 2048,
+                    detach_timeout_ms: 8000,
+                })],
+                endpoints: &[],
+            }],
+        };
+        const CONFIG_DESC_BYTES: [u8; CONFIG_DESC_DFU.total_size()] = CONFIG_DESC_DFU.serialize();
+
+        assert_eq!(
+            &CONFIG_DESC_BYTES,
+            &[
+                0x09, 0x02, 0x1b, 0x00, 0x01, 0x01, 0x00, 0x80, 0xfa, 0x09, 0x04, 0x00, 0x00, 0x00,
+                0xfe, 0x01, 0x02, 0x05, 0x09, 0x21, 0x0d, 0x40, 0x1f, 0x00, 0x08, 0x00, 0x01
+            ]
+        )
+    }
+
+    #[test]
+    fn test_string_descriptor() {
+        use core::ops::Deref;
+        const USB_VENDOR: StringDescriptorRef = string_descriptor!("Mutask").as_ref();
+        assert_eq!(
+            USB_VENDOR.as_bytes().deref(),
+            &[14, 3, b'M', 0, b'u', 0, b't', 0, b'a', 0, b's', 0, b'k', 0,]
+        );
+    }
+
+    #[test]
+    pub fn test_hex_utf16_descriptor() {
+        let mut buf = [0_u8; 80];
+        let len = hex_utf16_descriptor(&mut buf, &[0xab, 0x1c, 0xd2, 0xe3, 0x4f, 0x56, 0x78, 0x90])
+            .unwrap();
+        assert_eq!(
+            [
+                34, 3, b'a', 0, b'b', 0, b'1', 0, b'c', 0, b'd', 0, b'2', 0, b'e', 0, b'3', 0,
+                b'4', 0, b'f', 0, b'5', 0, b'6', 0, b'7', 0, b'8', 0, b'9', 0, b'0', 0
+            ],
+            &buf[..len]
+        );
+
+        // empty string; tight fit
+        let mut buf = [0_u8; 2];
+        let len = hex_utf16_descriptor(&mut buf, b"").unwrap();
+        assert_eq!(&[2, 3], &buf[..len]);
+
+        // 1 byte; tight fit
+        let mut buf = [0_u8; 6];
+        let len = hex_utf16_descriptor(&mut buf, &[0xca]).unwrap();
+        assert_eq!(&[6, 3, b'c', 0, b'a', 0], &buf[..len]);
+
+        // 2 bytes; tight fit
+        let mut buf = [0_u8; 10];
+        let len = hex_utf16_descriptor(&mut buf, &[0xca, 0xfe]).unwrap();
+        assert_eq!(&[10, 3, b'c', 0, b'a', 0, b'f', 0, b'e', 0], &buf[..len]);
+
+        // too small to fit descriptor
+        let mut buf = [0_u8; 1];
+        hex_utf16_descriptor(&mut buf, b"").unwrap_err();
+
+        // too small to fit 1 byte hex string
+        let mut buf = [0_u8; 5];
+        hex_utf16_descriptor(&mut buf, b"H").unwrap_err();
+
+        // too small to fit 2 byte hex string
+        let mut buf = [0_u8; 9];
+        hex_utf16_descriptor(&mut buf, b"Hi").unwrap_err();
+
+        // length too big to fit in length field
+        let mut buf = [0_u8; 258];
+        hex_utf16_descriptor(&mut buf, &[0x42_u8; 64]).unwrap_err();
+    }
+}
diff --git a/hal/blocking/usb/driver.rs b/hal/blocking/usb/driver.rs
new file mode 100644
index 00000000..9a529441
--- /dev/null
+++ b/hal/blocking/usb/driver.rs
@@ -0,0 +1,88 @@
+use aligned::Aligned;
+use aligned::A4;
+use core::mem::MaybeUninit;
+
+use crate::SetupPacket;
+
+/// A trait implemented by drivers for USB peripheral controllers.
+pub trait UsbDriver {
+    const MAX_PACKET_SIZE: usize;
+    type Packet<'a>: UsbPacket
+    where
+        Self: 'a;
+
+    /// Store data in a peripheral buffer that will be transferred to the host
+    /// when it requests data from the IN endpoint at `endpoint_idx`. If
+    /// zlp=true and `data.len()` is a multiple of MAX_PACKET_SIZE,
+    /// send a zero-length packet after sending all the data.
+    ///
+    /// The return value is the number of bytes that were copied into the
+    /// peripheral buffer. It will be either a multiple of MAX_PACKET_SIZE, or `data.len()`.
+    ///
+    /// This function may fault or panic if endpoint_idx is invalid, or the hardware is misbehaving.
+    fn transfer_in(&mut self, endpoint_idx: u8, data: &Aligned<A4, [u8]>, zlp: bool) -> usize;
+
+    /// Stalls an input endpoint. Note: the driver will automatically unstall all endpoints upon a USB reset or a new SETUP packet.
+    fn stall_in(&mut self, endpoint_idx: u8, stalled: bool);
+
+    /// Stalls an output endpoint. Note: the driver will automatically unstall all endpoints upon a USB reset or a new SETUP packet.
+    fn stall_out(&mut self, endpoint_idx: u8, stalled: bool);
+
+    /// Sets the address the peripheral responds to. The USB stack must call
+    /// this function in response to a SET_ADDRESS control request on endpoint 0.
+    fn set_address(&mut self, address: u8);
+
+    /// Polls the driver for an event. When a USB interrupt occurs, the USB
+    /// stack should call this function repeatedly until it returns None and
+    /// process the returned events.
+    fn poll(&mut self) -> Option<UsbEvent<Self::Packet<'_>>>;
+}
+
+pub trait UsbPacket {
+    /// The endpoint the packet was received on.
+    fn endpoint_index(&self) -> usize;
+
+    /// The length of the packet in bytes
+    fn len(&self) -> usize;
+
+    /// Copy the packet data from the peripheral buffer into SRAM. Will fault if
+    /// `self.len()` > `dest.len()`.
+    fn copy_to_uninit(self, dest: &mut [MaybeUninit<u32>]) -> &Aligned<A4, [u8]>;
+
+    /// Copy the packet data from the peripheral buffer into SRAM.
+    fn copy_to(self, dest: &mut [u32]) -> &Aligned<A4, [u8]>;
+
+    fn is_empty(&self) -> bool {
+        self.len() == 0
+    }
+}
+
+pub enum UsbEvent<TPacket: UsbPacket> {
+    /// A SETUP packet has been received from the host. It can be read with TPacket::copy_to()...
+    SetupPacket {
+        pkt: SetupPacket,
+        endpoint: u8,
+    },
+
+    /// An OUT packet has been received from the host. It can be read with TPacket::copy_to()...
+    DataOutPacket(TPacket),
+
+    /// A packet has been sent by the peripheral and an ACK has been received
+    /// from the host. This will have freed up some buffer space, so if the USB
+    /// stack has more data to send on this endpoint, it should attempt to
+    /// buffer it now with `UsbDriver::transfer_in()`.
+    PacketSent {
+        endpoint: u32,
+    },
+
+    VBus,
+    VBusLost,
+    LinkDown,
+    LinkUp,
+    UsbReset,
+    Suspend,
+    Resume,
+
+    // TODO: Put these into the global error namespace...
+    ErrorUnexpectedBufId,
+}
diff --git a/hal/blocking/usb/lib.rs b/hal/blocking/usb/lib.rs
new file mode 100644
index 00000000..02a6721c
--- /dev/null
+++ b/hal/blocking/usb/lib.rs
@@ -0,0 +1,412 @@
+#![cfg_attr(not(test), no_std)]
+
+mod descriptor;
+pub mod driver;
+
+use ufmt::derive::uDebug;
+
+pub use descriptor::*;
+
+// Big endian is dead; code in this file assumes little-endian
+const _: () = assert!(cfg!(target_endian = "little"));
+
+#[derive(Clone, Copy, Eq, PartialEq)]
+#[repr(transparent)]
+pub struct Request(u16);
+#[allow(clippy::identity_op)]
+impl Request {
+    pub const fn new(
+        direction: Direction,
+        ty: RequestType,
+        recipient: Recipient,
+        request: u8,
+    ) -> Self {
+        Self(
+            ((direction as u16) << 7)
+                | ((ty as u16) << 5)
+                | ((recipient as u16) << 0)
+                | ((request as u16) << 8),
+        )
+    }
+    pub fn direction(&self) -> Direction {
+        Direction::try_from((u32::from(self.0) >> 7) & 0x1).unwrap()
+    }
+    pub fn request_type(&self) -> RequestType {
+        RequestType::try_from(u32::from((self.0 >> 5) & 0x3)).unwrap()
+    }
+    pub fn recipient(&self) -> Recipient {
+        Recipient::try_from(u32::from((self.0 >> 0) & 0x1f)).unwrap()
+    }
+    pub fn request(&self) -> u8 {
+        u8::try_from((self.0 >> 8) & 0xff).unwrap()
+    }
+}
+impl ufmt::uDebug for Request {
+    fn fmt<W: ufmt::uWrite + ?Sized>(
+        &self,
+        f: &mut ufmt::Formatter<'_, W>,
+    ) -> Result<(), W::Error> {
+        f.debug_struct("usb::Request")?
+            .field("request_type", &self.request_type())?
+            .field("direction", &self.direction())?
+            .field("recipient", &self.recipient())?
+            .field("request", &self.request())?
+            .finish()
+    }
+}
+impl Request {
+    pub const DEVICE_GET_STATUS: Self = Self::new(
+        Direction::DeviceToHost,
+        RequestType::Standard,
+        Recipient::Device,
+        0x00,
+    );
+    pub const DEVICE_CLEAR_FEATURE: Self = Self::new(
+        Direction::HostToDevice,
+        RequestType::Standard,
+        Recipient::Device,
+        0x01,
+    );
+    pub const DEVICE_SET_FEATURE: Self = Self::new(
+        Direction::HostToDevice,
+        RequestType::Standard,
+        Recipient::Device,
+        0x03,
+    );
+    pub const DEVICE_SET_ADDRESS: Self = Self::new(
+        Direction::HostToDevice,
+        RequestType::Standard,
+        Recipient::Device,
+        0x05,
+    );
+    pub const DEVICE_GET_DESCRIPTOR: Self = Self::new(
+        Direction::DeviceToHost,
+        RequestType::Standard,
+        Recipient::Device,
+        0x06,
+    );
+    pub const DEVICE_SET_DESCRIPTOR: Self = Self::new(
+        Direction::HostToDevice,
+        RequestType::Standard,
+        Recipient::Device,
+        0x07,
+    );
+    pub const DEVICE_GET_CONFIGURATION: Self = Self::new(
+        Direction::DeviceToHost,
+        RequestType::Standard,
+        Recipient::Device,
+        0x08,
+    );
+    pub const DEVICE_SET_CONFIGURATION: Self = Self::new(
+        Direction::HostToDevice,
+        RequestType::Standard,
+        Recipient::Device,
+        0x09,
+    );
+    pub const INTERFACE_GET_STATUS: Self = Self::new(
+        Direction::DeviceToHost,
+        RequestType::Standard,
+        Recipient::Interface,
+        0x00,
+    );
+    pub const INTERFACE_CLEAR_FEATURE: Self = Self::new(
+        Direction::HostToDevice,
+        RequestType::Standard,
+        Recipient::Interface,
+        0x01,
+    );
+    pub const INTERFACE_SET_FEATURE: Self = Self::new(
+        Direction::HostToDevice,
+        RequestType::Standard,
+        Recipient::Interface,
+        0x03,
+    );
+    pub const INTERFACE_GET_INTERFACE: Self = Self::new(
+        Direction::DeviceToHost,
+        RequestType::Standard,
+        Recipient::Interface,
+        0x0a,
+    );
+    pub const INTERFACE_SET_INTERFACE: Self = Self::new(
+        Direction::HostToDevice,
+        RequestType::Standard,
+        Recipient::Interface,
+        0x0b,
+    );
+    pub const ENDPOINT_GET_STATUS: Self = Self::new(
+        Direction::DeviceToHost,
+        RequestType::Standard,
+        Recipient::Endpoint,
+        0x00,
+    );
+    pub const ENDPOINT_CLEAR_FEATURE: Self = Self::new(
+        Direction::HostToDevice,
+        RequestType::Standard,
+        Recipient::Endpoint,
+        0x01,
+    );
+    pub const ENDPOINT_SET_FEATURE: Self = Self::new(
+        Direction::HostToDevice,
+        RequestType::Standard,
+        Recipient::Endpoint,
+        0x03,
+    );
+    pub const ENDPOINT_SYNCH_FRAME: Self = Self::new(
+        Direction::DeviceToHost,
+        RequestType::Standard,
+        Recipient::Endpoint,
+        0x12,
+    );
+}
+impl From<Request> for u16 {
+    fn from(val: Request) -> Self {
+        val.0
+    }
+}
+#[cfg(test)]
+mod request_tests {
+    use super::*;
+    #[test]
+    fn test_constants() {
+        assert_eq!(u16::from(Request::DEVICE_GET_STATUS), 0x0080);
+        assert_eq!(u16::from(Request::DEVICE_CLEAR_FEATURE), 0x0100);
+        assert_eq!(u16::from(Request::DEVICE_SET_FEATURE), 0x0300);
+        assert_eq!(u16::from(Request::DEVICE_SET_ADDRESS), 0x0500);
+        assert_eq!(u16::from(Request::DEVICE_GET_DESCRIPTOR), 0x0680);
+        assert_eq!(u16::from(Request::DEVICE_SET_DESCRIPTOR), 0x0700);
+        assert_eq!(u16::from(Request::DEVICE_GET_CONFIGURATION), 0x0880);
+        assert_eq!(u16::from(Request::DEVICE_SET_CONFIGURATION), 0x0900);
+        assert_eq!(u16::from(Request::INTERFACE_GET_STATUS), 0x0081);
+        assert_eq!(u16::from(Request::INTERFACE_CLEAR_FEATURE), 0x0101);
+        assert_eq!(u16::from(Request::INTERFACE_SET_FEATURE), 0x0301);
+        assert_eq!(u16::from(Request::INTERFACE_GET_INTERFACE), 0x0a81);
+        assert_eq!(u16::from(Request::INTERFACE_SET_INTERFACE), 0x0b01);
+        assert_eq!(u16::from(Request::ENDPOINT_GET_STATUS), 0x0082);
+        assert_eq!(u16::from(Request::ENDPOINT_CLEAR_FEATURE), 0x0102);
+        assert_eq!(u16::from(Request::ENDPOINT_SET_FEATURE), 0x0302);
+        assert_eq!(u16::from(Request::ENDPOINT_SYNCH_FRAME), 0x1282);
+    }
+}
+
+#[derive(Clone, Copy, Eq, PartialEq, uDebug)]
+pub struct DescriptorInfo {
+    pub index: u8,
+    pub ty: DescriptorType,
+    pub lang: u16,
+}
+impl From<&SetupPacket> for DescriptorInfo {
+    fn from(pkt: &SetupPacket) -> Self {
+        DescriptorInfo {
+            index: u8::try_from(pkt.value() & 0xff).unwrap(),
+            ty: DescriptorType::from(u8::try_from((pkt.value() >> 8) & 0xff).unwrap()),
+            lang: pkt.index(),
+        }
+    }
+}
+#[derive(Clone, Copy)]
+#[repr(C)]
+pub struct SetupPacket {
+    buf: [u32; 2],
+}
+impl SetupPacket {
+    pub fn new(buf: [u32; 2]) -> SetupPacket {
+        SetupPacket { buf }
+    }
+    pub fn request(&self) -> Request {
+        Request(u16::try_from(self.buf[0] & 0xffff).unwrap())
+    }
+    pub fn value(&self) -> u16 {
+        u16::try_from((self.buf[0] >> 16) & 0xffff).unwrap()
+    }
+    #[allow(clippy::identity_op)]
+    pub fn index(&self) -> u16 {
+        u16::try_from((self.buf[1] >> 0) & 0xffff).unwrap()
+    }
+    pub fn length(&self) -> u16 {
+        u16::try_from((self.buf[1] >> 16) & 0xffff).unwrap()
+    }
+}
+impl ufmt::uDebug for SetupPacket {
+    fn fmt<W: ufmt::uWrite + ?Sized>(
+        &self,
+        f: &mut ufmt::Formatter<'_, W>,
+    ) -> Result<(), W::Error> {
+        f.debug_struct("usb::SetupPacket")?
+            .field("request", &self.request())?
+            .field("value", &self.value())?
+            .field("index", &self.index())?
+            .field("length", &self.length())?
+            .finish()
+    }
+}
+
+#[derive(Clone, Copy, Eq, PartialEq, uDebug)]
+pub enum Direction {
+    HostToDevice = 0,
+    DeviceToHost = 1,
+}
+impl From<Direction> for u32 {
+    fn from(val: Direction) -> u32 {
+        val as u32
+    }
+}
+impl TryFrom<u32> for Direction {
+    type Error = ();
+    #[inline(always)]
+    fn try_from(val: u32) -> Result<Direction, ()> {
+        match val {
+            0 => Ok(Self::HostToDevice),
+            1 => Ok(Self::DeviceToHost),
+            _ => Err(()),
+        }
+    }
+}
+#[derive(Clone, Copy, Eq, PartialEq, uDebug)]
+pub enum RequestType {
+    Standard = 0,
+    Class = 1,
+    Vendor = 2,
+    Reserved = 3,
+}
+impl TryFrom<u32> for RequestType {
+    type Error = ();
+    #[inline(always)]
+    fn try_from(val: u32) -> Result<RequestType, ()> {
+        match val {
+            0 => Ok(Self::Standard),
+            1 => Ok(Self::Class),
+            2 => Ok(Self::Vendor),
+            3 => Ok(Self::Reserved),
+            _ => Err(()),
+        }
+    }
+}
+impl From<RequestType> for u32 {
+    fn from(val: RequestType) -> Self {
+        val as u32
+    }
+}
+#[derive(Clone, Copy, Eq, PartialEq, uDebug)]
+pub enum Recipient {
+    Device = 0,
+    Interface = 1,
+    Endpoint = 2,
+    Other = 3,
+    Reserved4 = 4,
+    Reserved5 = 5,
+    Reserved6 = 6,
+    Reserved7 = 7,
+    Reserved8 = 8,
+    Reserved9 = 9,
+    Reserved10 = 10,
+    Reserved11 = 11,
+    Reserved12 = 12,
+    Reserved13 = 13,
+    Reserved14 = 14,
+    Reserved15 = 15,
+    Reserved16 = 16,
+    Reserved17 = 17,
+    Reserved18 = 18,
+    Reserved19 = 19,
+    Reserved20 = 20,
+    Reserved21 = 21,
+    Reserved22 = 22,
+    Reserved23 = 23,
+    Reserved24 = 24,
+    Reserved25 = 25,
+    Reserved26 = 26,
+    Reserved27 = 27,
+    Reserved28 = 28,
+    Reserved29 = 29,
+    Reserved30 = 30,
+    Reserved31 = 31,
+}
+impl TryFrom<u32> for Recipient {
+    type Error = ();
+    #[inline(always)]
+    fn try_from(val: u32) -> Result<Recipient, ()> {
+        // TODO: Evaluate whether the optimizer is smart enough for this, and use
+        // transmute if it's not.
+        match val {
+            0 => Ok(Self::Device),
+            1 => Ok(Self::Interface),
+            2 => Ok(Self::Endpoint),
+            3 => Ok(Self::Other),
+            4 => Ok(Self::Reserved4),
+            5 => Ok(Self::Reserved5),
+            6 => Ok(Self::Reserved6),
+            7 => Ok(Self::Reserved7),
+            8 => Ok(Self::Reserved8),
+            9 => Ok(Self::Reserved9),
+            10 => Ok(Self::Reserved10),
+            11 => Ok(Self::Reserved11),
+            12 => Ok(Self::Reserved12),
+            13 => Ok(Self::Reserved13),
+            14 => Ok(Self::Reserved14),
+            15 => Ok(Self::Reserved15),
+            16 => Ok(Self::Reserved16),
+            17 => Ok(Self::Reserved17),
+            18 => Ok(Self::Reserved18),
+            19 => Ok(Self::Reserved19),
+            20 => Ok(Self::Reserved20),
+            21 => Ok(Self::Reserved21),
+            22 => Ok(Self::Reserved22),
+            23 => Ok(Self::Reserved23),
+            24 => Ok(Self::Reserved24),
+            25 => Ok(Self::Reserved25),
+            26 => Ok(Self::Reserved26),
+            27 => Ok(Self::Reserved27),
+            28 => Ok(Self::Reserved28),
+            29 => Ok(Self::Reserved29),
+            30 => Ok(Self::Reserved30),
+            31 => Ok(Self::Reserved31),
+            _ => Err(()),
+        }
+    }
+}
+impl From<Recipient> for u32 {
+    fn from(val: Recipient) -> Self {
+        val as u32
+    }
+}
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub struct DescriptorType(u8);
+impl DescriptorType {
+    pub const DEVICE: Self = Self(1);
+    pub const CONFIGURATION: Self = Self(2);
+    pub const STRING: Self = Self(3);
+    pub const INTERFACE: Self = Self(4);
+    pub const ENDPOINT: Self = Self(5);
+    pub const DEVICE_QUALIFIER: Self = Self(6);
+}
+impl From<u8> for DescriptorType {
+    fn from(val: u8) -> Self {
+        DescriptorType(val)
+    }
+}
+impl From<DescriptorType> for u8 {
+    fn from(val: DescriptorType) -> Self {
+        val.0
+    }
+}
+impl From<DescriptorType> for u32 {
+    fn from(val: DescriptorType) -> Self {
+        u32::from(val.0)
+    }
+}
+impl ufmt::uDebug for DescriptorType {
+    fn fmt<W: ufmt::uWrite + ?Sized>(
+        &self,
+        f: &mut ufmt::Formatter<'_, W>,
+    ) -> Result<(), W::Error> {
+        match *self {
+            Self::DEVICE => f.write_str("DEVICE"),
+            Self::CONFIGURATION => f.write_str("CONFIGURATION"),
+            Self::STRING => f.write_str("STRING"),
+            Self::INTERFACE => f.write_str("INTERFACE"),
+            Self::ENDPOINT => f.write_str("ENDPOINT"),
+            Self::DEVICE_QUALIFIER => f.write_str("DEVICE_QUALIFIER"),
+            other => ufmt::uwrite!(f, "{}", other.0),
+        }
+    }
+}
diff --git a/protocol/usb/stack/BUILD.bazel b/protocol/usb/stack/BUILD.bazel
new file mode 100644
index 00000000..cdd47328
--- /dev/null
+++ b/protocol/usb/stack/BUILD.bazel
@@ -0,0 +1,26 @@
+load("@rules_rust//rust:defs.bzl", "rust_library", "rust_test")
+
+rust_library(
+    name = "stack",
+    srcs = [
+        "lib.rs",
+    ],
+    crate_name = "usb_stack",
+    edition = "2024",
+    visibility = ["//visibility:public"],
+    deps = [
+        "//hal/blocking/usb:hal_usb",
+        "//util/error",
+        "@rust_crates//:aligned",
+        "@rust_crates//:zerocopy",
+    ],
+)
+
+rust_test(
+    name = "stack_test",
+    crate = ":stack",
+    rustc_flags = [
+        "-C",
+        "debug-assertions",
+    ],
+)
diff --git a/protocol/usb/stack/lib.rs b/protocol/usb/stack/lib.rs
new file mode 100644
index 00000000..08427fcf
--- /dev/null
+++ b/protocol/usb/stack/lib.rs
@@ -0,0 +1,448 @@
+#![no_std]
+
+use aligned::Aligned;
+use aligned::A4;
+use core::mem::size_of;
+use hal_usb::driver::UsbDriver;
+use hal_usb::driver::UsbEvent;
+use hal_usb::driver::UsbPacket;
+use hal_usb::DescriptorInfo;
+use hal_usb::DescriptorType;
+use hal_usb::Request;
+use hal_usb::SetupPacket;
+use hal_usb::StringDescriptorRef;
+use hal_usb::StringHandle;
+use util_error::{ErrorCode, ErrorModule};
+use zerocopy::IntoBytes;
+
+pub const MODULE_USB: ErrorModule = ErrorModule::new(0x5550); // ascii `US`
+pub const USB_TRANSFER_BUFFER_OVERFLOW: ErrorCode = MODULE_USB.error(0x0001);
+
+pub trait DescriptorSource {
+    const DEVICE_DESC_BYTES: &'static Aligned<A4, [u8]>;
+    const CONFIG_DESC_BYTES: &'static Aligned<A4, [u8]>;
+    const STRING_DESC_0_BYTES: &'static Aligned<A4, [u8]>;
+
+    fn get_string(&self, handle: StringHandle, lang: u16) -> Option<StringDescriptorRef<'_>>;
+}
+
+pub const EMPTY: &Aligned<A4, [u8]> = &Aligned([]);
+
+pub struct SimpleEp0 {
+    new_address: Option<u8>,
+}
+
+#[derive(Copy, Clone, PartialEq, Eq)]
+pub enum UsbActionRun {
+    NoOp,
+    HasMoreData,
+    Done,
+}
+
+pub enum UsbAction<'a> {
+    None,
+    TransferIn {
+        endpoint: u8,
+        data: &'a Aligned<A4, [u8]>,
+        /// If zlp=true and `data.len()` is a multiple of MAX_PACKET_SIZE,
+        /// send a zero-length packet after sending all the data.
+        zlp: bool,
+    },
+    StallInAndOut {
+        endpoint: u8,
+    },
+    SetAddress {
+        new_address: u8,
+    },
+}
+impl<'a> UsbAction<'a> {
+    #[inline(always)]
+    #[track_caller]
+    pub fn control_transfer_in_or_stall(
+        endpoint: u8,
+        pkt: &SetupPacket,
+        data: &'a Aligned<A4, [u8]>,
+    ) -> Self {
+        if data.len() > pkt.length().into() {
+            Self::StallInAndOut { endpoint }
+        } else {
+            Self::TransferIn {
+                endpoint,
+                data,
+                // Per USB Specs 5.5.3, we need to send ZLP for control transfers
+                // if the response is less than requested.
+                zlp: data.is_empty() || data.len() < pkt.length().into(),
+            }
+        }
+    }
+    pub fn merge(&mut self, new_action: UsbAction<'a>) {
+        match new_action {
+            UsbAction::None => {}
+            _ => *self = new_action,
+        }
+    }
+
+    pub fn run<TDriver: UsbDriver>(&mut self, driver: &mut TDriver) -> UsbActionRun {
+        match self {
+            Self::None => return UsbActionRun::NoOp,
+            Self::TransferIn {
+                endpoint,
+                data,
+                zlp,
+            } => {
+                let bytes_transferred = driver.transfer_in(*endpoint, data, *zlp);
+                // Note: bytes_transferred is guaranteed to be a multiple of
+                // UsbDriver::MAX_PACKET_SIZE, which is guaranteed to be a
+                // multiple of 4.
+                if bytes_transferred < data.len() && (bytes_transferred & 3) == 0 {
+                    // We're not done yet...
+                    *data = &data[bytes_transferred..];
+                    return UsbActionRun::HasMoreData;
+                }
+            }
+            Self::SetAddress { new_address } => driver.set_address(*new_address),
+            Self::StallInAndOut { endpoint } => {
+                driver.stall_in(*endpoint, true);
+                driver.stall_out(*endpoint, true);
+            }
+        }
+        *self = UsbAction::None;
+        UsbActionRun::Done
+    }
+}
+
+impl SimpleEp0 {
+    pub fn new() -> Self {
+        Self { new_address: None }
+    }
+    /// A helper function to process a driver UsbEvent.
+    ///
+    /// This function returns the action that should be performed on the driver
+    /// (we can't take the driver as a parameter because the UsbPacket in the
+    /// event may capture the driver's lifetime).
+    pub fn handle_event<'a>(
+        &mut self,
+        ev: UsbEvent<impl UsbPacket>,
+        descriptor_source: &'a impl DescriptorSource,
+    ) -> UsbAction<'a> {
+        match ev {
+            UsbEvent::SetupPacket { endpoint, pkt } => {
+                if endpoint == 0 {
+                    return self.handle_setup(pkt, descriptor_source);
+                }
+            }
+            UsbEvent::PacketSent { endpoint } => {
+                if endpoint == 0 {
+                    return self.handle_packet_sent();
+                }
+            }
+            _ => {}
+        }
+        UsbAction::None
+    }
+
+    /// Process a SETUP transfer, and return the action that should be performed.
+    fn handle_setup<'a, TDescriptorSource: DescriptorSource>(
+        &mut self,
+        setup_pkt: SetupPacket,
+        descriptor_source: &'a TDescriptorSource,
+    ) -> UsbAction<'a> {
+        match setup_pkt.request() {
+            Request::DEVICE_GET_DESCRIPTOR => {
+                let descriptor = DescriptorInfo::from(&setup_pkt);
+                #[rustfmt::skip]
+                let mut response: Option<&Aligned<A4, [u8]>> = match descriptor {
+                    DescriptorInfo { ty: DescriptorType::DEVICE, index: 0, .. } => {
+                        Some(TDescriptorSource::DEVICE_DESC_BYTES)
+                    }
+                    DescriptorInfo { ty: DescriptorType::CONFIGURATION, index: 0, .. } => {
+                        Some(TDescriptorSource::CONFIG_DESC_BYTES)
+                    }
+                    DescriptorInfo { ty: DescriptorType::STRING, index: 0, .. } => {
+                        Some(TDescriptorSource::STRING_DESC_0_BYTES)
+                    }
+                    DescriptorInfo { ty: DescriptorType::STRING, index, .. } => {
+                        descriptor_source
+                            .get_string(StringHandle(index), setup_pkt.index())
+                            .map(|desc| desc.as_bytes())
+                    }
+                    _ => None,
+                };
+                if let Some(response) = &mut response {
+                    if response.len() > setup_pkt.length().into() {
+                        *response = &(*response)[..setup_pkt.length().into()];
+                    }
+                    UsbAction::control_transfer_in_or_stall(0, &setup_pkt, response)
+                } else {
+                    UsbAction::StallInAndOut { endpoint: 0 }
+                }
+            }
+            Request::DEVICE_SET_ADDRESS => {
+                self.new_address = Some(setup_pkt.value() as u8);
+                UsbAction::TransferIn {
+                    endpoint: 0,
+                    data: EMPTY,
+                    zlp: true,
+                }
+            }
+            Request::DEVICE_SET_CONFIGURATION => {
+                if setup_pkt.value() == 1 {
+                    UsbAction::TransferIn {
+                        endpoint: 0,
+                        data: EMPTY,
+                        zlp: true,
+                    }
+                } else {
+                    UsbAction::StallInAndOut { endpoint: 0 }
+                }
+            }
+            _ => UsbAction::StallInAndOut { endpoint: 0 },
+        }
+    }
+    fn handle_packet_sent(&mut self) -> UsbAction<'static> {
+        if let Some(new_address) = self.new_address.take() {
+            // Now that the transfer is complete it's safe to change the address..
+            return UsbAction::SetAddress { new_address };
+        }
+        UsbAction::None
+    }
+}
+
+impl Default for SimpleEp0 {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+/// A helper struct to handle multi-packet USB transfers.
+///
+/// It accumulates incoming USB packets into an internal buffer until a short
+/// packet or a zero-length packet (ZLP) is received, indicating the end of a transfer.
+///
+/// `N` is the number of **words** (`u32`s) in the internal buffer and NOT bytes.
+#[derive(Debug, PartialEq, Eq)]
+pub struct Transfer<const N: usize> {
+    buffer: [u32; N],
+    word_offset: usize,
+}
+
+impl<const N: usize> Transfer<N> {
+    // TODO: ckungler - This could be a const generic if we need to support
+    // other packet sizes.
+    pub const MAX_PACKET_SIZE: usize = 64;
+
+    pub fn new() -> Self {
+        Self {
+            buffer: [0; N],
+            word_offset: 0,
+        }
+    }
+
+    /// Splices a USB packet into the buffer.
+    ///
+    /// Returns `Ok(Some(slice))` if the transfer is complete, `Ok(None)` otherwise.
+    pub fn splice(
+        &mut self,
+        packet: impl UsbPacket,
+    ) -> Result<Option<&Aligned<A4, [u8]>>, ErrorCode> {
+        const {
+            assert!(Self::MAX_PACKET_SIZE % size_of::<u32>() == 0);
+        }
+        let packet_len = packet.len();
+        let dest = {
+            let start = self.word_offset;
+            let end = start + packet_len.div_ceil(size_of::<u32>());
+            self.buffer
+                .get_mut(start..end)
+                .ok_or(USB_TRANSFER_BUFFER_OVERFLOW)?
+        };
+        packet.copy_to(dest);
+        if packet_len < Self::MAX_PACKET_SIZE {
+            let result = &self
+                .buffer
+                .as_bytes()
+                .get(..self.word_offset * size_of::<u32>() + packet_len)
+                .ok_or(USB_TRANSFER_BUFFER_OVERFLOW)?;
+            self.word_offset = 0;
+            // This is safe because `self.buffer` is `[u32]` which has alignment of 4.
+            Ok(Some(unsafe {
+                core::mem::transmute::<&[u8], &Aligned<A4, [u8]>>(result)
+            }))
+        } else {
+            self.word_offset += Self::MAX_PACKET_SIZE / size_of::<u32>();
+            Ok(None)
+        }
+    }
+}
+
+impl<const N: usize> Default for Transfer<N> {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+pub mod testing {
+    use aligned::Aligned;
+    use aligned::A4;
+    use hal_usb::driver::UsbPacket;
+    use zerocopy::IntoBytes;
+
+    #[derive(Debug)]
+    pub struct FakeUsbPacket<'a> {
+        pub data: &'a [u8],
+        pub ep: usize,
+    }
+
+    impl UsbPacket for FakeUsbPacket<'_> {
+        fn endpoint_index(&self) -> usize {
+            self.ep
+        }
+
+        fn len(&self) -> usize {
+            self.data.len()
+        }
+
+        fn copy_to_uninit(self, _dest: &mut [core::mem::MaybeUninit<u32>]) -> &Aligned<A4, [u8]> {
+            unimplemented!()
+        }
+
+        fn copy_to(self, dest: &mut [u32]) -> &Aligned<A4, [u8]> {
+            let dest_bytes = dest.as_mut_bytes();
+            let copy_len = self.data.len().min(dest_bytes.len());
+            dest_bytes[..copy_len].copy_from_slice(&self.data[..copy_len]);
+            // This is safe because `dest` is a `&mut [u32]`, which is guaranteed to be 4-byte
+            // aligned. `dest_bytes` is a byte slice view of the same memory, so it's also
+            // 4-byte aligned. The subslice `&dest_bytes[..copy_len]` maintains this alignment.
+            unsafe { core::mem::transmute::<&[u8], &Aligned<A4, [u8]>>(&dest_bytes[..copy_len]) }
+        }
+    }
+}
+
+#[cfg(test)]
+mod splice_tests {
+    use super::testing::FakeUsbPacket;
+    use super::*;
+
+    const MAX_PACKET_SIZE: usize = Transfer::<0>::MAX_PACKET_SIZE;
+
+    #[test]
+    fn test_splice_single_short_packet() {
+        let packet_data = [1, 2, 3, 4];
+        let packet = FakeUsbPacket {
+            data: &packet_data,
+            ep: 0,
+        };
+
+        let mut transfer = Transfer::<32>::new();
+        let result = transfer.splice(packet).unwrap();
+
+        assert!(result.is_some());
+        assert_eq!(result.unwrap().as_ref(), &packet_data[..]);
+    }
+
+    #[test]
+    fn test_splice_single_full_packet_then_zlp() {
+        let packet_data = [42; MAX_PACKET_SIZE];
+        let packet = FakeUsbPacket {
+            data: &packet_data,
+            ep: 0,
+        };
+
+        let mut transfer = Transfer::<32>::new();
+        let result = transfer.splice(packet).unwrap();
+
+        assert!(result.is_none());
+
+        let zlp = FakeUsbPacket { data: &[], ep: 0 };
+        let result = transfer.splice(zlp).unwrap();
+        assert!(result.is_some());
+        assert_eq!(result.unwrap().as_ref(), &packet_data[..]);
+    }
+
+    #[test]
+    fn test_splice_multiple_packets() {
+        let packet1_data = [1; MAX_PACKET_SIZE];
+        let packet2_data = [2; MAX_PACKET_SIZE];
+        let packet3_data = [3; 32];
+
+        // Packet 1
+        let packet1 = FakeUsbPacket {
+            data: &packet1_data,
+            ep: 0,
+        };
+        let mut transfer = Transfer::<64>::new();
+        let result = transfer.splice(packet1).unwrap();
+        assert!(result.is_none());
+
+        // Packet 2
+        let packet2 = FakeUsbPacket {
+            data: &packet2_data,
+            ep: 0,
+        };
+        let result = transfer.splice(packet2).unwrap();
+        assert!(result.is_none());
+
+        // Packet 3 (short packet)
+        let packet3 = FakeUsbPacket {
+            data: &packet3_data,
+            ep: 0,
+        };
+        let result = transfer.splice(packet3).unwrap();
+        assert!(result.is_some());
+
+        let mut expected_data = [0u8; 2 * MAX_PACKET_SIZE + 32];
+        expected_data[..MAX_PACKET_SIZE].copy_from_slice(&packet1_data);
+        expected_data[MAX_PACKET_SIZE..2 * MAX_PACKET_SIZE].copy_from_slice(&packet2_data);
+        expected_data[2 * MAX_PACKET_SIZE..].copy_from_slice(&packet3_data);
+
+        assert_eq!(result.unwrap().as_ref(), &expected_data[..]);
+    }
+
+    #[test]
+    fn test_splice_buffer_overflow() {
+        let packet_data = [1; 1];
+        let packet = FakeUsbPacket {
+            data: &packet_data,
+            ep: 0,
+        };
+
+        let mut transfer = Transfer::<16>::new();
+        transfer
+            .splice(FakeUsbPacket {
+                data: &[0; MAX_PACKET_SIZE],
+                ep: 0,
+            })
+            .unwrap();
+        let result = transfer.splice(packet);
+        assert_eq!(result.err(), Some(USB_TRANSFER_BUFFER_OVERFLOW));
+    }
+
+    #[test]
+    fn test_full_capacity_with_full_packets_then_partial_packet() {
+        const PARTIAL_SIZE: usize = 16;
+        const FULL1_DATA: &[u8] = &[0xaa; MAX_PACKET_SIZE];
+        const FULL2_DATA: &[u8] = &[0xbb; MAX_PACKET_SIZE];
+        const PARTIAL_DATA: &[u8] = &[0xcc; PARTIAL_SIZE];
+        const RECEIVE_BUFFER_WORDS: usize =
+            (FULL1_DATA.len() + FULL2_DATA.len() + PARTIAL_DATA.len()) / size_of::<u32>();
+        let full1 = FakeUsbPacket {
+            data: FULL1_DATA,
+            ep: 0,
+        };
+        let full2 = FakeUsbPacket {
+            data: FULL2_DATA,
+            ep: 0,
+        };
+        let partial = FakeUsbPacket {
+            data: PARTIAL_DATA,
+            ep: 0,
+        };
+        let mut transfer = Transfer::<RECEIVE_BUFFER_WORDS>::new();
+        assert!(transfer.splice(full1).unwrap().is_none());
+        assert!(transfer.splice(full2).unwrap().is_none());
+        let buffer = transfer.splice(partial).unwrap().unwrap().as_ref();
+        assert_eq!(&buffer[..MAX_PACKET_SIZE], FULL1_DATA);
+        assert_eq!(&buffer[MAX_PACKET_SIZE..2 * MAX_PACKET_SIZE], FULL2_DATA);
+        assert_eq!(&buffer[2 * MAX_PACKET_SIZE..], PARTIAL_DATA);
+    }
+}
diff --git a/target/earlgrey/drivers/BUILD.bazel b/target/earlgrey/drivers/BUILD.bazel
new file mode 100644
index 00000000..558425ee
--- /dev/null
+++ b/target/earlgrey/drivers/BUILD.bazel
@@ -0,0 +1,21 @@
+# Licensed under the Apache-2.0 license
+# SPDX-License-Identifier: Apache-2.0
+
+load("@rules_rust//rust:defs.bzl", "rust_library")
+
+rust_library(
+    name = "usb_driver",
+    srcs = ["usb_driver.rs"],
+    edition = "2024",
+    visibility = ["//visibility:public"],
+    deps = [
+        "//hal/blocking/usb:hal_usb",
+        "//target/earlgrey/registers:usbdev",
+        "//util/console",
+        "//util/regcpy",
+        "@rust_crates//:aligned",
+        "@rust_crates//:ufmt",
+        "@rust_crates//:zerocopy",
+        "@ureg",
+    ],
+)
diff --git a/target/earlgrey/drivers/usb_driver.rs b/target/earlgrey/drivers/usb_driver.rs
new file mode 100644
index 00000000..dcb3b0c3
--- /dev/null
+++ b/target/earlgrey/drivers/usb_driver.rs
@@ -0,0 +1,1092 @@
+#![no_std]
+
+use aligned::A4;
+use aligned::Aligned;
+use core::cmp::min;
+use util_regcpy::copy_to_reg_array;
+use console::traceln;
+use hal_usb::SetupPacket;
+use hal_usb::driver::UsbDriver;
+use hal_usb::driver::UsbEvent;
+use hal_usb::driver::UsbPacket;
+use zerocopy::IntoBytes;
+
+const MAX_PACKET_SIZE: usize = 64;
+const BUFFER_SLOT_SIZE_WORDS: usize = MAX_PACKET_SIZE / 4;
+const BUFFER_SLOT_COUNT: usize = 32;
+
+const EMPTY_A4: &Aligned<A4, [u8]> = &Aligned([]);
+
+use buf_pool::BufId;
+use buf_pool::BufPool;
+use buf_pool::BuffPoolAllocator;
+use core::cmp;
+use ureg::RealMmio;
+
+use crate::transmit_queue::TransmitQueues;
+
+pub struct PacketHandle<TMmio: ureg::Mmio + Copy> {
+    // A reference to 16 words of packet data in the peripheral MMIO memory.
+    data: ureg::Array<16, ureg::RegRef<ureg::ReadWriteReg32<0, u32, u32>, TMmio>>,
+    // The length of the packet in bytes
+    packet_len: u16,
+    ep: u8,
+}
+
+impl<TMmio: ureg::Mmio + Copy> UsbPacket for PacketHandle<TMmio> {
+    fn endpoint_index(&self) -> usize {
+        self.ep.into()
+    }
+    fn len(&self) -> usize {
+        self.packet_len.into()
+    }
+
+    fn copy_to_uninit(self, dest: &mut [core::mem::MaybeUninit<u32>]) -> &Aligned<A4, [u8]> {
+        #![allow(clippy::needless_range_loop)]
+
+        // TODO: Are we sure we want to silently truncate if dest isn't big enough?
+        let word_len = min(min(dest.len(), MAX_PACKET_SIZE / 4), self.len().div_ceil(4));
+        for i in 0..word_len {
+            dest[i].write(self.data.at(i).read());
+        }
+        //let result = unsafe { mutask_subtle::slice_assume_init(&dest[..word_len]) };
+
+        // This is feature(maybe_uninit_slice).
+        let result = &dest[..word_len];
+        let result = unsafe { &*(result as *const [core::mem::MaybeUninit<u32>] as *const [u32]) };
+
+        // TODO: add a Aligned::try_from() function to the aligned crate and use it here with unwrap.
+        unsafe {
+            core::mem::transmute::<&[u8], &Aligned<A4, [u8]>>(
+                &result.as_bytes()[..min(self.len(), word_len * 4)],
+            )
+        }
+    }
+
+    fn copy_to(self, dest: &mut [u32]) -> &Aligned<A4, [u8]> {
+        #![allow(clippy::needless_range_loop)]
+
+        // TODO: Are we sure we want to silently truncate if dest isn't big enough?
+        let word_len = min(min(dest.len(), MAX_PACKET_SIZE / 4), self.len().div_ceil(4));
+        for i in 0..word_len {
+            dest[i] = self.data.at(i).read();
+        }
+        // TODO: add a Aligned::try_from() function to the aligned crate and use it here with unwrap.
+        unsafe {
+            core::mem::transmute::<&[u8], &Aligned<A4, [u8]>>(
+                &dest.as_bytes()[..min(self.len(), dest.as_bytes().len())],
+            )
+        }
+    }
+}
+
+#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+pub struct NextInPacket {
+    buf_id: u8,
+    len: u8,
+}
+impl NextInPacket {
+    const NONE: Self = Self {
+        buf_id: 0xff,
+        len: 0xff,
+    };
+}
+
+#[derive(Clone, Copy)]
+pub struct EpIn {
+    pub num: u8,
+    pub buf_pool_size: u32,
+}
+
+#[derive(Clone, Copy)]
+pub struct EpOut {
+    pub num: u8,
+    /// If true, hardware will NAK OUT transfers on this endpoint after the first
+    /// until software re-enables by setting `rxenable_out`
+    pub set_nak: bool,
+}
+
+const NB_EP: usize = 12;
+
+pub struct Usb {
+    mmio: usbdev::Usbdev,
+
+    // buffer pool for SETUP transfers from host, technically common, but only used for EP0.
+    buf_pool_setup: BufPool,
+    // buffer pool for OUT transfers from host, common for all EPs.
+    buf_pool_out: BufPool,
+
+    // buffer pools for IN transfers.
+    buf_pools_in: [BufPool; NB_EP],
+
+    transmit_queues: TransmitQueues,
+}
+
+#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+pub struct UsbConfig {
+    buf_pool_setup: BufPool,
+    buf_pool_out: BufPool,
+    buf_pools_in: [BufPool; NB_EP],
+    in_mask: u32,
+    out_mask: u32,
+    set_nak_mask: u32,
+}
+impl UsbConfig {
+    /// Construct a USB config. This should typically be done within a const
+    /// block so any errors become compile-time panics.
+    ///
+    /// # Panic
+    ///
+    /// This function will panic if the supplied endpoints are invalid.
+    #[inline(always)]
+    pub const fn new(eps_in: &[EpIn], eps_out: &[EpOut]) -> Self {
+        let mut buf_pool_allocator = BuffPoolAllocator::new();
+        let buf_pool_setup = buf_pool_allocator.new_bufpool(4).unwrap();
+        let buf_pool_out = buf_pool_allocator.new_bufpool(12).unwrap();
+
+        let mut buf_pools_in = [BufPool::EMPTY; NB_EP];
+        let mut i = 0;
+        while i < eps_in.len() {
+            let ep = &eps_in[i];
+            if ep.num == 0 || ep.num as usize > NB_EP {
+                panic!("Invalid endpoint number");
+            }
+            let Some(new_pool) = buf_pool_allocator.new_bufpool(ep.buf_pool_size) else {
+                panic!("Bufpool allocation overflow");
+            };
+            buf_pools_in[ep.num as usize] = new_pool;
+            i += 1;
+        }
+        let Some(new_pool) = buf_pool_allocator.remainder_bufpool() else {
+            panic!("Bufpool allocation overflow");
+        };
+        buf_pools_in[0] = new_pool;
+
+        let in_mask: u32 = {
+            let mut v = 1; // always enable EP0
+            let mut i = 0;
+            while i < eps_in.len() {
+                v |= 1 << eps_in[i].num;
+                i += 1;
+            }
+            v
+        };
+
+        let out_mask: u32 = {
+            let mut v = 1; // always enable EP0
+            let mut i = 0;
+            while i < eps_out.len() {
+                v |= 1 << eps_out[i].num;
+                i += 1;
+            }
+            v
+        };
+
+        let set_nak_mask: u32 = {
+            let mut v = 0u32;
+            let mut i = 0;
+            while i < eps_out.len() {
+                if eps_out[i].set_nak {
+                    v |= 1 << eps_out[i].num;
+                }
+                i += 1;
+            }
+
+            // Writes to `rxenable_out` are not atomic - therefore we must
+            // guarantee that `set_nak_out` is only set for up to a single
+            // endpoint (github.com/lowRISC/opentitan/issues/27434)
+            assert!(
+                v.count_ones() <= 1,
+                "set_nak_out can be enabled on at most one endpoint"
+            );
+            v
+        };
+
+        Self {
+            buf_pool_setup,
+            buf_pool_out,
+            buf_pools_in,
+            in_mask,
+            out_mask,
+            set_nak_mask,
+        }
+    }
+}
+
+impl Usb {
+    pub fn new(mmio: usbdev::Usbdev, config: UsbConfig) -> Self {
+        let mut result = Self {
+            mmio,
+            buf_pool_setup: config.buf_pool_setup,
+            buf_pool_out: config.buf_pool_out,
+            buf_pools_in: config.buf_pools_in,
+            transmit_queues: TransmitQueues::new(),
+        };
+        result.init(&config);
+        result
+    }
+    fn init(&mut self, config: &UsbConfig) {
+        self.fill_setup_buffer_fifo();
+        self.fill_out_buffer_fifo();
+
+        let regs = self.mmio.regs_mut();
+
+        regs.ep_in_enable0().write(|_| config.in_mask.into());
+        regs.ep_out_enable0().write(|_| config.out_mask.into());
+        regs.rxenable_out0().write(|_| config.out_mask.into());
+        regs.set_nak_out0().write(|_| config.set_nak_mask.into());
+
+        regs.rxenable_setup0().write(|w| w.setup0(true));
+        regs.intr_enable().write(|w| {
+            w.pkt_received(true)
+                .pkt_sent(true)
+                .disconnected(true)
+                .host_lost(true)
+                .link_reset(true)
+                .link_suspend(true)
+                .link_resume(true)
+                .av_out_empty(true)
+                .rx_full(true)
+                .av_overflow(true)
+                .link_in_err(false)
+                .rx_crc_err(false)
+                .rx_pid_err(false)
+                .rx_bitstuff_err(false)
+                .frame(false)
+                .powered(true)
+                .link_out_err(false)
+                .av_setup_empty(true)
+        });
+        regs.usbctrl().modify(|w| w.enable(true));
+
+        let stat = regs.usbstat().read();
+        traceln!(
+            "Usb out_depth={} setup_depth={}",
+            stat.av_out_depth(),
+            stat.av_setup_depth()
+        );
+    }
+
+    fn reset_in(&mut self) {
+        let regs = self.mmio.regs_mut();
+        for (i, pool) in &mut self.buf_pools_in.iter_mut().enumerate() {
+            pool.reset();
+            let configin = regs.configin().at(i);
+            if configin.read().pend() {
+                // link reset will cancel any pending transactions. Since we're
+                // resetting the pool/queue state there's nothing else to do but
+                // clear the notification.
+                configin.write(|w| w.pend_clear());
+            }
+        }
+        self.transmit_queues.reset();
+    }
+
+    fn fill_setup_buffer_fifo(&mut self) {
+        // Setup buffers for incoming SETUP packets from host.
+        while !self.mmio.regs().usbstat().read().av_setup_full() {
+            let Some(buf_id) = self.buf_pool_setup.take() else {
+                break;
+            };
+            self.mmio
+                .regs_mut()
+                .avsetupbuffer()
+                .write(|w| w.buffer(buf_id.into()));
+        }
+    }
+    fn fill_out_buffer_fifo(&mut self) {
+        // Setup buffers for incoming OUT packets from host.
+        while !self.mmio.regs().usbstat().read().av_out_full() {
+            let Some(buf_id) = self.buf_pool_out.take() else {
+                break;
+            };
+            self.mmio
+                .regs_mut()
+                .avoutbuffer()
+                .write(|w| w.buffer(buf_id.into()));
+        }
+    }
+
+    /// Flush packets bufferred to transmit on `endpoint` starting with `buf_id`.
+    fn clear_ep_tx_queue(&mut self, endpoint: u32, mut buf_id: BufId) {
+        let buf_pool_in = &mut self.buf_pools_in[usize::try_from(endpoint).unwrap()];
+        buf_pool_in.put(buf_id);
+        while let Some(pkt) = self.transmit_queues.deque_next_packet(endpoint, buf_id) {
+            buf_id = BufId(pkt.buf_id.into());
+            buf_pool_in.put(buf_id);
+        }
+    }
+
+    /// Resume accepting OUT transfers on this endpoint.
+    ///
+    /// This should be called after processing an OUT transfer on a given endpoint
+    /// that was configured with `EpOut { set_nak: true }`. The `set_nak` option causes
+    /// the hardware to automatically NAK subsequent OUT transactions until this function
+    /// is called to re-enable reception.
+    pub fn set_rxenable(&mut self, ep_num: u8) {
+        self.mmio
+            .regs_mut()
+            .rxenable_out0()
+            .modify(|w| bit_setval(u32::from(w), ep_num.into(), true).into());
+    }
+}
+
+#[inline(always)]
+fn bit_setval(bits: u32, index: usize, value: bool) -> u32 {
+    let mask = 1 << index;
+    if value { bits | mask } else { bits & !mask }
+}
+
+impl UsbDriver for Usb {
+    const MAX_PACKET_SIZE: usize = 64;
+    type Packet<'a> = PacketHandle<RealMmio<'a>>;
+
+    #[inline(always)]
+    fn stall_in(&mut self, endpoint_idx: u8, stalled: bool) {
+        self.mmio
+            .regs_mut()
+            .in_stall0()
+            .modify(|w| bit_setval(u32::from(w), endpoint_idx.into(), stalled).into());
+    }
+    #[inline(always)]
+    fn stall_out(&mut self, endpoint_idx: u8, stalled: bool) {
+        self.mmio
+            .regs_mut()
+            .out_stall0()
+            .modify(|w| bit_setval(u32::from(w), endpoint_idx.into(), stalled).into());
+    }
+
+    /// Store data in peripheral buffer that will be transferred when the host requests it.
+    #[inline(never)]
+    fn transfer_in(&mut self, endpoint: u8, mut data: &Aligned<A4, [u8]>, zlp: bool) -> usize {
+        let mut bytes_queued = 0;
+        let zlp = zlp && (data.len() % MAX_PACKET_SIZE) == 0;
+        loop {
+            if data.is_empty() && !zlp {
+                break;
+            }
+            let regs = self.mmio.regs_mut();
+            let Some(configin_reg) = regs.configin().get(endpoint.into()) else {
+                // Fault?
+                return 0;
+            };
+
+            let pkt = &data[..cmp::min(MAX_PACKET_SIZE, data.len())];
+            if pkt.len() == MAX_PACKET_SIZE {
+                data = &data[pkt.len()..];
+            } else {
+                data = EMPTY_A4;
+            }
+
+            let buf_pool = self.buf_pools_in.get_mut(usize::from(endpoint)).unwrap();
+
+            // Check to see if we have enough buffers to send both
+            // the last data packet and a ZLP if necessary. If not, leave last
+            // data packet unsent so caller knows to retry transfer
+            if zlp && pkt.len() == MAX_PACKET_SIZE && buf_pool.len() < 2 {
+                traceln!("Couldn't find buf in pool for last IN + ZLP");
+                break;
+            }
+
+            let Some(buf_id) = buf_pool.take() else {
+                traceln!("Couldn't find buf in pool for next IN");
+                break;
+            };
+
+            let Some(buffer) = regs
+                .buffer()
+                .get_sub_array::<BUFFER_SLOT_SIZE_WORDS>(buf_id.offset())
+            else {
+                // Shouldn't fail to get buffer offset
+                unreachable!();
+            };
+            copy_to_reg_array(&buffer, pkt);
+
+            match self.transmit_queues.queue(
+                endpoint.into(),
+                NextInPacket {
+                    buf_id: u32::from(buf_id) as u8,
+                    len: pkt.len() as u8,
+                },
+            ) {
+                TransmitQueueAction::None => {}
+                TransmitQueueAction::SendNow => {
+                    if configin_reg.read().rdy() {
+                        traceln!("WARN: Packet already queued in hardware");
+                    }
+                    configin_reg.write(|w| {
+                        w.buffer(buf_id.into())
+                            .rdy(true)
+                            .size(u32::try_from(pkt.len()).unwrap())
+                    });
+                }
+            }
+            bytes_queued += pkt.len();
+
+            if pkt.is_empty() {
+                break;
+            }
+        }
+        bytes_queued
+    }
+    fn set_address(&mut self, address: u8) {
+        self.mmio
+            .regs_mut()
+            .usbctrl()
+            .modify(|w| w.device_address(address.into()));
+    }
+
+    #[inline(never)]
+    fn poll(&mut self) -> Option<UsbEvent<PacketHandle<RealMmio<'_>>>> {
+        let intr = self.mmio.regs_mut().intr_state().read();
+
+        // TODO: use count_leading_zeros() to iterate over the pending interrupts
+        if intr.pkt_received() {
+            let fifo_entry = self.mmio.regs_mut().rxfifo().read();
+
+            if fifo_entry.setup() {
+                self.fill_setup_buffer_fifo();
+
+                if let Some(configin_reg) = self
+                    .mmio
+                    .regs_mut()
+                    .configin()
+                    .get(fifo_entry.ep() as usize)
+                {
+                    let configin = configin_reg.read();
+                    if configin.pend() {
+                        // Previous transmission was cancelled by an incoming setup packet
+                        configin_reg.write(|w| w.pend_clear());
+                        self.clear_ep_tx_queue(fifo_entry.ep(), BufId(configin.buffer()));
+                    }
+                }
+            } else {
+                self.fill_out_buffer_fifo();
+            }
+
+            let offset = usize::try_from(fifo_entry.buffer()).unwrap() * BUFFER_SLOT_SIZE_WORDS;
+            let Some(pkt_buffer) = self
+                .mmio
+                .regs()
+                .into_buffer()
+                .get_sub_array::<BUFFER_SLOT_SIZE_WORDS>(offset)
+            else {
+                return Some(UsbEvent::ErrorUnexpectedBufId);
+            };
+
+            if fifo_entry.setup() {
+                let buf_id = BufId(fifo_entry.buffer());
+
+                // Return the buffer back to the pool, but don't call
+                // self.fill_setup_buffer_fifo() yet, as the caller to poll()
+                // may look at this data from the returned event, and we don't want
+                // the peripheral to change it while they're reading the data
+                // (because the returned Event is exclusively holding self, it won't be possible
+                // to call fill_setup_buffer_fifo() until after they lose the event).
+                self.buf_pool_setup.put(buf_id);
+
+                let ep = u8::try_from(fifo_entry.ep()).unwrap();
+                let pkt_handle = PacketHandle {
+                    data: pkt_buffer,
+                    // These unwraps will optimize out
+                    ep,
+                    packet_len: u16::try_from(fifo_entry.size()).unwrap(),
+                };
+                let mut pkt_words = [0_u32; 2];
+                pkt_handle.copy_to(&mut pkt_words);
+                return Some(UsbEvent::SetupPacket {
+                    endpoint: ep,
+                    pkt: SetupPacket::new(pkt_words),
+                });
+            } else {
+                let buf_id = BufId(fifo_entry.buffer());
+                self.buf_pool_out.put(buf_id);
+                return Some(UsbEvent::DataOutPacket(PacketHandle {
+                    data: pkt_buffer,
+                    // These unwraps will optimize out
+                    ep: u8::try_from(fifo_entry.ep()).unwrap(),
+                    packet_len: u16::try_from(fifo_entry.size()).unwrap(),
+                }));
+            }
+        }
+        if intr.pkt_sent() {
+            let regs = self.mmio.regs_mut();
+            loop {
+                let endpoint_bits: u32 = regs.in_sent0().read().into();
+                if endpoint_bits == 0 {
+                    break;
+                }
+                let endpoint_id = endpoint_bits.trailing_zeros();
+
+                // Ensure we don't get interrupted about this packet again (w1c)
+                regs.in_sent0().write(|_| (1 << endpoint_id).into());
+
+                let Some(configin_reg) = regs.configin().get(usize::try_from(endpoint_id).unwrap())
+                else {
+                    // TODO: Log weird hardware behavior?
+                    continue;
+                };
+                let configin = configin_reg.read();
+
+                if configin.rdy() {
+                    // TODO: Log weird hardware behavior...
+                    continue;
+                }
+
+                let buf_pool = self
+                    .buf_pools_in
+                    .get_mut(usize::try_from(endpoint_id).unwrap())
+                    .unwrap();
+                let sent_buf_id = BufId(configin.buffer());
+                buf_pool.put(sent_buf_id);
+
+                if let Some(next_pkt) = self
+                    .transmit_queues
+                    .deque_next_packet(endpoint_id, sent_buf_id)
+                {
+                    // We have more packets for this endpoint already in the
+                    // peripheral SRAM; let's tell the hardware to prep the next
+                    // one for sending.
+                    configin_reg.write(|w| {
+                        w.buffer(next_pkt.buf_id.into())
+                            .size(next_pkt.len.into())
+                            .rdy(true)
+                    });
+                }
+                return Some(UsbEvent::PacketSent {
+                    endpoint: endpoint_id,
+                });
+            }
+        }
+        if intr.host_lost() {
+            self.mmio
+                .regs_mut()
+                .intr_state()
+                .write(|w| w.host_lost_clear());
+            return Some(UsbEvent::LinkDown);
+        }
+        if intr.powered() {
+            self.mmio
+                .regs_mut()
+                .intr_state()
+                .write(|w| w.powered_clear());
+            return Some(UsbEvent::VBus);
+        }
+        if intr.disconnected() {
+            self.mmio
+                .regs_mut()
+                .intr_state()
+                .write(|w| w.disconnected_clear());
+            return Some(UsbEvent::VBusLost);
+        }
+        if intr.link_reset() {
+            self.reset_in();
+            self.mmio
+                .regs_mut()
+                .intr_state()
+                .write(|w| w.link_reset_clear());
+            return Some(UsbEvent::UsbReset);
+        }
+        if intr.av_overflow() {
+            self.mmio
+                .regs_mut()
+                .intr_state()
+                .write(|w| w.av_overflow_clear());
+            traceln!("av_overflow");
+        }
+        if intr.link_suspend() {
+            self.mmio
+                .regs_mut()
+                .intr_state()
+                .write(|w| w.link_suspend_clear());
+        }
+        if intr.link_resume() {
+            self.mmio
+                .regs_mut()
+                .intr_state()
+                .write(|w| w.link_resume_clear());
+        }
+        if intr.av_out_empty() {
+            traceln!("av_out_empty");
+            self.fill_out_buffer_fifo();
+        }
+        if intr.av_setup_empty() {
+            traceln!("av_setup_empty");
+            self.fill_setup_buffer_fifo();
+        }
+        if intr.rx_full() {
+            traceln!("rx_full");
+        }
+
+        None
+    }
+}
+
+#[derive(Eq, PartialEq, Debug)]
+pub enum TransmitQueueAction {
+    None,
+    SendNow,
+}
+
+pub mod transmit_queue {
+    use super::*;
+
+    pub struct TransmitQueues {
+        slots: [NextInPacket; BUFFER_SLOT_COUNT],
+
+        /// Indexed by endpoint num, this is the slot index of the last packet
+        /// queued for transmission on that endpoint.
+        last_pkt_idx: [Option<u8>; NB_EP],
+    }
+    impl TransmitQueues {
+        pub const fn new() -> Self {
+            Self {
+                slots: [NextInPacket::NONE; BUFFER_SLOT_COUNT],
+                last_pkt_idx: [None; NB_EP],
+            }
+        }
+        pub fn reset(&mut self) {
+            *self = Self::new()
+        }
+
+        #[must_use]
+        #[inline(always)]
+        pub fn queue(&mut self, ep_id: u32, pkt: NextInPacket) -> TransmitQueueAction {
+            let ep_id = usize::try_from(ep_id).unwrap();
+            let last_pkt_idx = &mut self.last_pkt_idx[ep_id];
+            let result = if let Some(last_pkt_idx) = *last_pkt_idx
+                && let Some(entry) = self.slots.get_mut(usize::from(last_pkt_idx))
+            {
+                *entry = pkt;
+                TransmitQueueAction::None
+            } else {
+                if let Some(entry) = self.slots.get_mut(usize::from(pkt.buf_id)) {
+                    *entry = NextInPacket::NONE;
+                }
+                TransmitQueueAction::SendNow
+            };
+            *last_pkt_idx = Some(pkt.buf_id);
+            result
+        }
+
+        #[inline(always)]
+        pub fn deque_next_packet(
+            &mut self,
+            ep_id: u32,
+            sent_buf_id: BufId,
+        ) -> Option<NextInPacket> {
+            let ep_id = usize::try_from(ep_id).unwrap();
+            let sent_buf_id = usize::from(sent_buf_id);
+            let next_pkt = &mut self.slots[sent_buf_id];
+            if usize::from(next_pkt.buf_id) >= BUFFER_SLOT_COUNT {
+                self.last_pkt_idx[ep_id] = None;
+                return None;
+            }
+            Some(core::mem::replace(next_pkt, NextInPacket::NONE))
+        }
+    }
+    impl Default for TransmitQueues {
+        fn default() -> Self {
+            Self::new()
+        }
+    }
+
+    #[cfg(test)]
+    mod test {
+        use super::*;
+
+        #[test]
+        fn test_transmit_queues() {
+            let mut queues = TransmitQueues::new();
+            assert_eq!(
+                queues.queue(0, NextInPacket { buf_id: 4, len: 64 }),
+                TransmitQueueAction::SendNow
+            );
+            assert_eq!(
+                queues.queue(0, NextInPacket { buf_id: 5, len: 64 }),
+                TransmitQueueAction::None
+            );
+            assert_eq!(
+                queues.queue(
+                    1,
+                    NextInPacket {
+                        buf_id: 10,
+                        len: 64
+                    }
+                ),
+                TransmitQueueAction::SendNow
+            );
+            assert_eq!(
+                queues.queue(
+                    1,
+                    NextInPacket {
+                        buf_id: 11,
+                        len: 64
+                    }
+                ),
+                TransmitQueueAction::None
+            );
+            assert_eq!(
+                queues.queue(0, NextInPacket { buf_id: 6, len: 0 }),
+                TransmitQueueAction::None
+            );
+            assert_eq!(
+                queues.queue(1, NextInPacket { buf_id: 12, len: 3 }),
+                TransmitQueueAction::None
+            );
+
+            assert_eq!(
+                queues.deque_next_packet(1, BufId(10)),
+                Some(NextInPacket {
+                    buf_id: 11,
+                    len: 64
+                })
+            );
+            assert_eq!(
+                queues.deque_next_packet(0, BufId(4)),
+                Some(NextInPacket { buf_id: 5, len: 64 })
+            );
+            assert_eq!(
+                queues.deque_next_packet(0, BufId(5)),
+                Some(NextInPacket { buf_id: 6, len: 0 })
+            );
+            assert_eq!(queues.deque_next_packet(0, BufId(6)), None);
+
+            assert_eq!(
+                queues.queue(
+                    1,
+                    NextInPacket {
+                        buf_id: 10,
+                        len: 33
+                    }
+                ),
+                TransmitQueueAction::None
+            );
+            assert_eq!(
+                queues.queue(0, NextInPacket { buf_id: 4, len: 64 }),
+                TransmitQueueAction::SendNow
+            );
+            assert_eq!(
+                queues.queue(0, NextInPacket { buf_id: 5, len: 9 }),
+                TransmitQueueAction::None
+            );
+
+            assert_eq!(
+                queues.deque_next_packet(1, BufId(11)),
+                Some(NextInPacket { buf_id: 12, len: 3 })
+            );
+            assert_eq!(
+                queues.deque_next_packet(1, BufId(12)),
+                Some(NextInPacket {
+                    buf_id: 10,
+                    len: 33
+                })
+            );
+            assert_eq!(
+                queues.deque_next_packet(0, BufId(4)),
+                Some(NextInPacket { buf_id: 5, len: 9 })
+            );
+            assert_eq!(queues.deque_next_packet(0, BufId(5)), None);
+            assert_eq!(queues.deque_next_packet(1, BufId(10)), None);
+
+            // Make sure we cleaned up after ourselves...
+            assert!(queues.slots.iter().all(|s| *s == NextInPacket::NONE));
+            assert!(queues.last_pkt_idx.iter().all(|i| i.is_none()));
+        }
+    }
+}
+
+pub mod buf_pool {
+    use super::*;
+
+    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
+    #[repr(transparent)]
+    pub struct BufId(pub u32);
+    impl BufId {
+        pub const fn offset(&self) -> usize {
+            self.0 as usize * BUFFER_SLOT_SIZE_WORDS
+        }
+    }
+    impl From<BufId> for u32 {
+        fn from(value: BufId) -> Self {
+            value.0
+        }
+    }
+    impl From<BufId> for usize {
+        fn from(value: BufId) -> Self {
+            usize::try_from(value.0).unwrap()
+        }
+    }
+    impl From<u32> for BufId {
+        fn from(value: u32) -> Self {
+            Self(value)
+        }
+    }
+
+    pub struct BuffPoolAllocator {
+        allocated_buf_ids: u32,
+    }
+    impl Default for BuffPoolAllocator {
+        fn default() -> Self {
+            Self::new()
+        }
+    }
+    impl BuffPoolAllocator {
+        pub const fn new() -> Self {
+            Self {
+                allocated_buf_ids: 0,
+            }
+        }
+        pub const fn new_bufpool(&mut self, len: u32) -> Option<BufPool> {
+            let start_id = self.allocated_buf_ids.trailing_ones();
+            if len == 0 || start_id + len > 32 {
+                return None;
+            }
+            let mask = (((1_u64 << len) - 1) << start_id) as u32;
+            self.allocated_buf_ids |= mask;
+            Some(BufPool {
+                init_value: mask,
+                available_bufs: mask,
+            })
+        }
+        pub const fn remainder_bufpool(mut self) -> Option<BufPool> {
+            let left = self.allocated_buf_ids.leading_zeros();
+            self.new_bufpool(left)
+        }
+    }
+
+    #[cfg(test)]
+    mod test_buff_pool_allocator {
+        use super::*;
+
+        #[test]
+        fn test_next() {
+            let mut allocator = BuffPoolAllocator::new();
+            assert_eq!(
+                allocator.new_bufpool(1),
+                Some(BufPool {
+                    available_bufs: 0b01,
+                    init_value: 0b01
+                })
+            );
+            assert_eq!(
+                allocator.new_bufpool(1),
+                Some(BufPool {
+                    available_bufs: 0b10,
+                    init_value: 0b10,
+                })
+            );
+            assert_eq!(
+                allocator.new_bufpool(2),
+                Some(BufPool {
+                    available_bufs: 0b1100,
+                    init_value: 0b1100,
+                })
+            );
+            assert_eq!(allocator.new_bufpool(0), None);
+            assert_eq!(allocator.new_bufpool(30), None);
+            assert_eq!(
+                allocator.new_bufpool(28),
+                Some(BufPool {
+                    available_bufs: (0xffff_ffffu64 << 4) as u32,
+                    init_value: (0xffff_ffffu64 << 4) as u32,
+                })
+            );
+            assert_eq!(allocator.new_bufpool(1), None);
+        }
+        #[test]
+        fn test_remainder() {
+            let mut allocator = BuffPoolAllocator::new();
+            assert_eq!(
+                allocator.new_bufpool(1),
+                Some(BufPool {
+                    available_bufs: 0b01,
+                    init_value: 0b01,
+                })
+            );
+            assert_eq!(
+                allocator.new_bufpool(1),
+                Some(BufPool {
+                    available_bufs: 0b10,
+                    init_value: 0b10,
+                })
+            );
+            assert_eq!(
+                allocator.new_bufpool(2),
+                Some(BufPool {
+                    available_bufs: 0b1100,
+                    init_value: 0b1100,
+                })
+            );
+            assert_eq!(
+                allocator.remainder_bufpool(),
+                Some(BufPool {
+                    available_bufs: (0xffff_ffffu64 << 4) as u32,
+                    init_value: (0xffff_ffffu64 << 4) as u32,
+                })
+            );
+        }
+    }
+
+    #[derive(PartialEq, Eq, Debug, Clone, Copy)]
+    pub struct BufPool {
+        // bitset of bufs that are currently available for taking with take().
+        available_bufs: u32,
+        init_value: u32,
+    }
+    impl BufPool {
+        pub const EMPTY: Self = Self {
+            available_bufs: 0,
+            init_value: 0,
+        };
+
+        #[cfg(test)]
+        pub const fn new(start_id: usize, len: usize) -> Self {
+            assert!(start_id < 32);
+            assert!(len > 0);
+            assert!(start_id + len <= 32);
+            let available_bufs = (((1_u64 << len) - 1) << start_id) as u32;
+            Self {
+                available_bufs,
+                init_value: available_bufs,
+            }
+        }
+        pub fn reset(&mut self) {
+            self.available_bufs = self.init_value;
+        }
+        pub fn take(&mut self) -> Option<BufId> {
+            if self.is_empty() {
+                return None;
+            }
+            let buf_id = self.available_bufs.trailing_zeros();
+            let mask = 1 << buf_id;
+            debug_assert!((self.available_bufs & mask) != 0);
+            self.available_bufs &= !mask;
+            Some(BufId(buf_id))
+        }
+        pub fn put(&mut self, buf_id: BufId) {
+            let mask = 1 << u32::from(buf_id);
+            debug_assert!((self.available_bufs & mask) == 0);
+            self.available_bufs |= mask;
+        }
+
+        pub fn len(&self) -> usize {
+            usize::try_from(self.available_bufs.count_ones()).unwrap()
+        }
+
+        pub fn is_empty(&self) -> bool {
+            self.available_bufs == 0
+        }
+    }
+
+    #[cfg(test)]
+    mod test {
+        use super::*;
+
+        #[test]
+        fn test_full_size() {
+            let mut pool = BufPool::new(0, 32);
+            assert_eq!(pool.available_bufs, 0xffff_ffff);
+            for i in 0..32 {
+                assert_eq!(Some(BufId::from(i)), pool.take());
+            }
+            assert_eq!(None, pool.take());
+            pool.put(5.into());
+            pool.put(7.into());
+            pool.put(3.into());
+            assert_eq!(Some(3.into()), pool.take());
+            assert_eq!(Some(5.into()), pool.take());
+            assert_eq!(Some(7.into()), pool.take());
+            assert_eq!(None, pool.take());
+            assert_eq!(None, pool.take());
+        }
+
+        #[test]
+        fn test_5_bits() {
+            let mut pool = BufPool::new(4, 5);
+            assert_eq!(pool.available_bufs, 0x0000_01f0);
+            assert_eq!(Some(BufId::from(4)), pool.take());
+            assert_eq!(Some(BufId::from(5)), pool.take());
+            assert_eq!(Some(BufId::from(6)), pool.take());
+            assert_eq!(Some(BufId::from(7)), pool.take());
+            assert_eq!(Some(BufId::from(8)), pool.take());
+            assert_eq!(None, pool.take());
+
+            pool.put(5.into());
+            pool.put(6.into());
+            assert_eq!(Some(5.into()), pool.take());
+            assert_eq!(Some(6.into()), pool.take());
+            assert_eq!(None, pool.take());
+        }
+
+        #[test]
+        fn test_config() {
+            assert_eq!(
+                UsbConfig::new(
+                    &[
+                        EpIn {
+                            num: 1,
+                            buf_pool_size: 3,
+                        },
+                        EpIn {
+                            num: 3,
+                            buf_pool_size: 5,
+                        },
+                    ],
+                    &[
+                        EpOut {
+                            num: 2,
+                            set_nak: true
+                        },
+                        EpOut {
+                            num: 4,
+                            set_nak: false
+                        },
+                    ]
+                ),
+                UsbConfig {
+                    buf_pool_setup: BufPool::new(0, 4),
+                    buf_pool_out: BufPool::new(4, 12),
+                    buf_pools_in: [
+                        BufPool::new(24, 8),
+                        BufPool::new(16, 3),
+                        BufPool::EMPTY,
+                        BufPool::new(19, 5),
+                        BufPool::EMPTY,
+                        BufPool::EMPTY,
+                        BufPool::EMPTY,
+                        BufPool::EMPTY,
+                        BufPool::EMPTY,
+                        BufPool::EMPTY,
+                        BufPool::EMPTY,
+                        BufPool::EMPTY,
+                    ],
+                    in_mask: 0b01011,
+                    out_mask: 0b10101,
+                    set_nak_mask: 0b100,
+                },
+            );
+        }
+
+        #[test]
+        #[should_panic]
+        fn test_config_too_many_set_nak() {
+            UsbConfig::new(
+                &[EpIn {
+                    num: 1,
+                    buf_pool_size: 3,
+                }],
+                &[
+                    EpOut {
+                        num: 2,
+                        set_nak: true,
+                    },
+                    EpOut {
+                        num: 4,
+                        set_nak: true,
+                    },
+                ],
+            );
+        }
+    }
+}
diff --git a/target/earlgrey/registers/BUILD.bazel b/target/earlgrey/registers/BUILD.bazel
index 3b309eed..b760f2d6 100644
--- a/target/earlgrey/registers/BUILD.bazel
+++ b/target/earlgrey/registers/BUILD.bazel
@@ -381,3 +381,10 @@ rust_library(
     visibility = ["//visibility:public"],
     deps = ["@ureg"],
 )
+
+rust_library(
+    name = "top_earlgrey",
+    srcs = ["top_earlgrey.rs"],
+    edition = "2024",
+    visibility = ["//visibility:public"],
+)
diff --git a/target/earlgrey/registers/top_earlgrey.rs b/target/earlgrey/registers/top_earlgrey.rs
new file mode 100644
index 00000000..60c28608
--- /dev/null
+++ b/target/earlgrey/registers/top_earlgrey.rs
@@ -0,0 +1,3257 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This file was generated automatically.
+// Please do not modify content of this file directly.
+// File generated by using template: "toplevel.rs.tpl"
+// To regenerate this file follow OpenTitan topgen documentations.
+
+#![no_std]
+#![allow(dead_code)]
+
+//! This file contains enums and consts for use within the Rust codebase.
+//!
+//! These definitions are for information that depends on the top-specific chip
+//! configuration, which includes:
+//! - Device Memory Information (for Peripherals and Memory)
+//! - PLIC Interrupt ID Names and Source Mappings
+//! - Alert ID Names and Source Mappings
+//! - Pinmux Pin/Select Names
+//! - Power Manager Wakeups
+
+use core::convert::TryFrom;
+
+/// Peripheral base address for uart0 in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const UART0_BASE_ADDR: usize = 0x40000000;
+
+/// Peripheral size for uart0 in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #UART0_BASE_ADDR and
+/// `UART0_BASE_ADDR + UART0_SIZE_BYTES`.
+pub const UART0_SIZE_BYTES: usize = 0x40;
+
+/// Peripheral base address for uart1 in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const UART1_BASE_ADDR: usize = 0x40010000;
+
+/// Peripheral size for uart1 in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #UART1_BASE_ADDR and
+/// `UART1_BASE_ADDR + UART1_SIZE_BYTES`.
+pub const UART1_SIZE_BYTES: usize = 0x40;
+
+/// Peripheral base address for uart2 in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const UART2_BASE_ADDR: usize = 0x40020000;
+
+/// Peripheral size for uart2 in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #UART2_BASE_ADDR and
+/// `UART2_BASE_ADDR + UART2_SIZE_BYTES`.
+pub const UART2_SIZE_BYTES: usize = 0x40;
+
+/// Peripheral base address for uart3 in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const UART3_BASE_ADDR: usize = 0x40030000;
+
+/// Peripheral size for uart3 in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #UART3_BASE_ADDR and
+/// `UART3_BASE_ADDR + UART3_SIZE_BYTES`.
+pub const UART3_SIZE_BYTES: usize = 0x40;
+
+/// Peripheral base address for gpio in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const GPIO_BASE_ADDR: usize = 0x40040000;
+
+/// Peripheral size for gpio in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #GPIO_BASE_ADDR and
+/// `GPIO_BASE_ADDR + GPIO_SIZE_BYTES`.
+pub const GPIO_SIZE_BYTES: usize = 0x40;
+
+/// Peripheral base address for spi_device in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const SPI_DEVICE_BASE_ADDR: usize = 0x40050000;
+
+/// Peripheral size for spi_device in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #SPI_DEVICE_BASE_ADDR and
+/// `SPI_DEVICE_BASE_ADDR + SPI_DEVICE_SIZE_BYTES`.
+pub const SPI_DEVICE_SIZE_BYTES: usize = 0x2000;
+
+/// Peripheral base address for i2c0 in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const I2C0_BASE_ADDR: usize = 0x40080000;
+
+/// Peripheral size for i2c0 in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #I2C0_BASE_ADDR and
+/// `I2C0_BASE_ADDR + I2C0_SIZE_BYTES`.
+pub const I2C0_SIZE_BYTES: usize = 0x80;
+
+/// Peripheral base address for i2c1 in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const I2C1_BASE_ADDR: usize = 0x40090000;
+
+/// Peripheral size for i2c1 in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #I2C1_BASE_ADDR and
+/// `I2C1_BASE_ADDR + I2C1_SIZE_BYTES`.
+pub const I2C1_SIZE_BYTES: usize = 0x80;
+
+/// Peripheral base address for i2c2 in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const I2C2_BASE_ADDR: usize = 0x400A0000;
+
+/// Peripheral size for i2c2 in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #I2C2_BASE_ADDR and
+/// `I2C2_BASE_ADDR + I2C2_SIZE_BYTES`.
+pub const I2C2_SIZE_BYTES: usize = 0x80;
+
+/// Peripheral base address for pattgen in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const PATTGEN_BASE_ADDR: usize = 0x400E0000;
+
+/// Peripheral size for pattgen in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #PATTGEN_BASE_ADDR and
+/// `PATTGEN_BASE_ADDR + PATTGEN_SIZE_BYTES`.
+pub const PATTGEN_SIZE_BYTES: usize = 0x40;
+
+/// Peripheral base address for rv_timer in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const RV_TIMER_BASE_ADDR: usize = 0x40100000;
+
+/// Peripheral size for rv_timer in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #RV_TIMER_BASE_ADDR and
+/// `RV_TIMER_BASE_ADDR + RV_TIMER_SIZE_BYTES`.
+pub const RV_TIMER_SIZE_BYTES: usize = 0x200;
+
+/// Peripheral base address for core device on otp_ctrl in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const OTP_CTRL_CORE_BASE_ADDR: usize = 0x40130000;
+
+/// Peripheral size for core device on otp_ctrl in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #OTP_CTRL_CORE_BASE_ADDR and
+/// `OTP_CTRL_CORE_BASE_ADDR + OTP_CTRL_CORE_SIZE_BYTES`.
+pub const OTP_CTRL_CORE_SIZE_BYTES: usize = 0x1000;
+
+/// Peripheral base address for prim device on otp_ctrl in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const OTP_CTRL_PRIM_BASE_ADDR: usize = 0x40138000;
+
+/// Peripheral size for prim device on otp_ctrl in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #OTP_CTRL_PRIM_BASE_ADDR and
+/// `OTP_CTRL_PRIM_BASE_ADDR + OTP_CTRL_PRIM_SIZE_BYTES`.
+pub const OTP_CTRL_PRIM_SIZE_BYTES: usize = 0x20;
+
+/// Peripheral base address for lc_ctrl in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const LC_CTRL_BASE_ADDR: usize = 0x40140000;
+
+/// Peripheral size for lc_ctrl in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #LC_CTRL_BASE_ADDR and
+/// `LC_CTRL_BASE_ADDR + LC_CTRL_SIZE_BYTES`.
+pub const LC_CTRL_SIZE_BYTES: usize = 0x100;
+
+/// Peripheral base address for alert_handler in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const ALERT_HANDLER_BASE_ADDR: usize = 0x40150000;
+
+/// Peripheral size for alert_handler in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #ALERT_HANDLER_BASE_ADDR and
+/// `ALERT_HANDLER_BASE_ADDR + ALERT_HANDLER_SIZE_BYTES`.
+pub const ALERT_HANDLER_SIZE_BYTES: usize = 0x800;
+
+/// Peripheral base address for spi_host0 in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const SPI_HOST0_BASE_ADDR: usize = 0x40300000;
+
+/// Peripheral size for spi_host0 in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #SPI_HOST0_BASE_ADDR and
+/// `SPI_HOST0_BASE_ADDR + SPI_HOST0_SIZE_BYTES`.
+pub const SPI_HOST0_SIZE_BYTES: usize = 0x40;
+
+/// Peripheral base address for spi_host1 in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const SPI_HOST1_BASE_ADDR: usize = 0x40310000;
+
+/// Peripheral size for spi_host1 in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #SPI_HOST1_BASE_ADDR and
+/// `SPI_HOST1_BASE_ADDR + SPI_HOST1_SIZE_BYTES`.
+pub const SPI_HOST1_SIZE_BYTES: usize = 0x40;
+
+/// Peripheral base address for usbdev in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const USBDEV_BASE_ADDR: usize = 0x40320000;
+
+/// Peripheral size for usbdev in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #USBDEV_BASE_ADDR and
+/// `USBDEV_BASE_ADDR + USBDEV_SIZE_BYTES`.
+pub const USBDEV_SIZE_BYTES: usize = 0x1000;
+
+/// Peripheral base address for pwrmgr_aon in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const PWRMGR_AON_BASE_ADDR: usize = 0x40400000;
+
+/// Peripheral size for pwrmgr_aon in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #PWRMGR_AON_BASE_ADDR and
+/// `PWRMGR_AON_BASE_ADDR + PWRMGR_AON_SIZE_BYTES`.
+pub const PWRMGR_AON_SIZE_BYTES: usize = 0x80;
+
+/// Peripheral base address for rstmgr_aon in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const RSTMGR_AON_BASE_ADDR: usize = 0x40410000;
+
+/// Peripheral size for rstmgr_aon in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #RSTMGR_AON_BASE_ADDR and
+/// `RSTMGR_AON_BASE_ADDR + RSTMGR_AON_SIZE_BYTES`.
+pub const RSTMGR_AON_SIZE_BYTES: usize = 0x80;
+
+/// Peripheral base address for clkmgr_aon in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const CLKMGR_AON_BASE_ADDR: usize = 0x40420000;
+
+/// Peripheral size for clkmgr_aon in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #CLKMGR_AON_BASE_ADDR and
+/// `CLKMGR_AON_BASE_ADDR + CLKMGR_AON_SIZE_BYTES`.
+pub const CLKMGR_AON_SIZE_BYTES: usize = 0x80;
+
+/// Peripheral base address for sysrst_ctrl_aon in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const SYSRST_CTRL_AON_BASE_ADDR: usize = 0x40430000;
+
+/// Peripheral size for sysrst_ctrl_aon in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #SYSRST_CTRL_AON_BASE_ADDR and
+/// `SYSRST_CTRL_AON_BASE_ADDR + SYSRST_CTRL_AON_SIZE_BYTES`.
+pub const SYSRST_CTRL_AON_SIZE_BYTES: usize = 0x100;
+
+/// Peripheral base address for adc_ctrl_aon in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const ADC_CTRL_AON_BASE_ADDR: usize = 0x40440000;
+
+/// Peripheral size for adc_ctrl_aon in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #ADC_CTRL_AON_BASE_ADDR and
+/// `ADC_CTRL_AON_BASE_ADDR + ADC_CTRL_AON_SIZE_BYTES`.
+pub const ADC_CTRL_AON_SIZE_BYTES: usize = 0x80;
+
+/// Peripheral base address for pwm_aon in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const PWM_AON_BASE_ADDR: usize = 0x40450000;
+
+/// Peripheral size for pwm_aon in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #PWM_AON_BASE_ADDR and
+/// `PWM_AON_BASE_ADDR + PWM_AON_SIZE_BYTES`.
+pub const PWM_AON_SIZE_BYTES: usize = 0x80;
+
+/// Peripheral base address for pinmux_aon in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const PINMUX_AON_BASE_ADDR: usize = 0x40460000;
+
+/// Peripheral size for pinmux_aon in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #PINMUX_AON_BASE_ADDR and
+/// `PINMUX_AON_BASE_ADDR + PINMUX_AON_SIZE_BYTES`.
+pub const PINMUX_AON_SIZE_BYTES: usize = 0x1000;
+
+/// Peripheral base address for aon_timer_aon in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const AON_TIMER_AON_BASE_ADDR: usize = 0x40470000;
+
+/// Peripheral size for aon_timer_aon in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #AON_TIMER_AON_BASE_ADDR and
+/// `AON_TIMER_AON_BASE_ADDR + AON_TIMER_AON_SIZE_BYTES`.
+pub const AON_TIMER_AON_SIZE_BYTES: usize = 0x40;
+
+/// Peripheral base address for ast in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const AST_BASE_ADDR: usize = 0x40480000;
+
+/// Peripheral size for ast in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #AST_BASE_ADDR and
+/// `AST_BASE_ADDR + AST_SIZE_BYTES`.
+pub const AST_SIZE_BYTES: usize = 0x400;
+
+/// Peripheral base address for sensor_ctrl_aon in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const SENSOR_CTRL_AON_BASE_ADDR: usize = 0x40490000;
+
+/// Peripheral size for sensor_ctrl_aon in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #SENSOR_CTRL_AON_BASE_ADDR and
+/// `SENSOR_CTRL_AON_BASE_ADDR + SENSOR_CTRL_AON_SIZE_BYTES`.
+pub const SENSOR_CTRL_AON_SIZE_BYTES: usize = 0x80;
+
+/// Peripheral base address for regs device on sram_ctrl_ret_aon in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const SRAM_CTRL_RET_AON_REGS_BASE_ADDR: usize = 0x40500000;
+
+/// Peripheral size for regs device on sram_ctrl_ret_aon in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #SRAM_CTRL_RET_AON_REGS_BASE_ADDR and
+/// `SRAM_CTRL_RET_AON_REGS_BASE_ADDR + SRAM_CTRL_RET_AON_REGS_SIZE_BYTES`.
+pub const SRAM_CTRL_RET_AON_REGS_SIZE_BYTES: usize = 0x40;
+
+/// Peripheral base address for ram device on sram_ctrl_ret_aon in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const SRAM_CTRL_RET_AON_RAM_BASE_ADDR: usize = 0x40600000;
+
+/// Peripheral size for ram device on sram_ctrl_ret_aon in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #SRAM_CTRL_RET_AON_RAM_BASE_ADDR and
+/// `SRAM_CTRL_RET_AON_RAM_BASE_ADDR + SRAM_CTRL_RET_AON_RAM_SIZE_BYTES`.
+pub const SRAM_CTRL_RET_AON_RAM_SIZE_BYTES: usize = 0x1000;
+
+/// Peripheral base address for core device on flash_ctrl in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const FLASH_CTRL_CORE_BASE_ADDR: usize = 0x41000000;
+
+/// Peripheral size for core device on flash_ctrl in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #FLASH_CTRL_CORE_BASE_ADDR and
+/// `FLASH_CTRL_CORE_BASE_ADDR + FLASH_CTRL_CORE_SIZE_BYTES`.
+pub const FLASH_CTRL_CORE_SIZE_BYTES: usize = 0x200;
+
+/// Peripheral base address for prim device on flash_ctrl in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const FLASH_CTRL_PRIM_BASE_ADDR: usize = 0x41008000;
+
+/// Peripheral size for prim device on flash_ctrl in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #FLASH_CTRL_PRIM_BASE_ADDR and
+/// `FLASH_CTRL_PRIM_BASE_ADDR + FLASH_CTRL_PRIM_SIZE_BYTES`.
+pub const FLASH_CTRL_PRIM_SIZE_BYTES: usize = 0x80;
+
+/// Peripheral base address for mem device on flash_ctrl in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const FLASH_CTRL_MEM_BASE_ADDR: usize = 0x20000000;
+
+/// Peripheral size for mem device on flash_ctrl in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #FLASH_CTRL_MEM_BASE_ADDR and
+/// `FLASH_CTRL_MEM_BASE_ADDR + FLASH_CTRL_MEM_SIZE_BYTES`.
+pub const FLASH_CTRL_MEM_SIZE_BYTES: usize = 0x100000;
+
+/// Peripheral base address for regs device on rv_dm in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const RV_DM_REGS_BASE_ADDR: usize = 0x41200000;
+
+/// Peripheral size for regs device on rv_dm in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #RV_DM_REGS_BASE_ADDR and
+/// `RV_DM_REGS_BASE_ADDR + RV_DM_REGS_SIZE_BYTES`.
+pub const RV_DM_REGS_SIZE_BYTES: usize = 0x10;
+
+/// Peripheral base address for mem device on rv_dm in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const RV_DM_MEM_BASE_ADDR: usize = 0x10000;
+
+/// Peripheral size for mem device on rv_dm in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #RV_DM_MEM_BASE_ADDR and
+/// `RV_DM_MEM_BASE_ADDR + RV_DM_MEM_SIZE_BYTES`.
+pub const RV_DM_MEM_SIZE_BYTES: usize = 0x1000;
+
+/// Peripheral base address for rv_plic in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const RV_PLIC_BASE_ADDR: usize = 0x48000000;
+
+/// Peripheral size for rv_plic in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #RV_PLIC_BASE_ADDR and
+/// `RV_PLIC_BASE_ADDR + RV_PLIC_SIZE_BYTES`.
+pub const RV_PLIC_SIZE_BYTES: usize = 0x8000000;
+
+/// Peripheral base address for aes in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const AES_BASE_ADDR: usize = 0x41100000;
+
+/// Peripheral size for aes in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #AES_BASE_ADDR and
+/// `AES_BASE_ADDR + AES_SIZE_BYTES`.
+pub const AES_SIZE_BYTES: usize = 0x100;
+
+/// Peripheral base address for hmac in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const HMAC_BASE_ADDR: usize = 0x41110000;
+
+/// Peripheral size for hmac in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #HMAC_BASE_ADDR and
+/// `HMAC_BASE_ADDR + HMAC_SIZE_BYTES`.
+pub const HMAC_SIZE_BYTES: usize = 0x2000;
+
+/// Peripheral base address for kmac in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const KMAC_BASE_ADDR: usize = 0x41120000;
+
+/// Peripheral size for kmac in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #KMAC_BASE_ADDR and
+/// `KMAC_BASE_ADDR + KMAC_SIZE_BYTES`.
+pub const KMAC_SIZE_BYTES: usize = 0x1000;
+
+/// Peripheral base address for otbn in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const OTBN_BASE_ADDR: usize = 0x41130000;
+
+/// Peripheral size for otbn in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #OTBN_BASE_ADDR and
+/// `OTBN_BASE_ADDR + OTBN_SIZE_BYTES`.
+pub const OTBN_SIZE_BYTES: usize = 0x10000;
+
+/// Peripheral base address for keymgr in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const KEYMGR_BASE_ADDR: usize = 0x41140000;
+
+/// Peripheral size for keymgr in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #KEYMGR_BASE_ADDR and
+/// `KEYMGR_BASE_ADDR + KEYMGR_SIZE_BYTES`.
+pub const KEYMGR_SIZE_BYTES: usize = 0x100;
+
+/// Peripheral base address for csrng in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const CSRNG_BASE_ADDR: usize = 0x41150000;
+
+/// Peripheral size for csrng in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #CSRNG_BASE_ADDR and
+/// `CSRNG_BASE_ADDR + CSRNG_SIZE_BYTES`.
+pub const CSRNG_SIZE_BYTES: usize = 0x80;
+
+/// Peripheral base address for entropy_src in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const ENTROPY_SRC_BASE_ADDR: usize = 0x41160000;
+
+/// Peripheral size for entropy_src in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #ENTROPY_SRC_BASE_ADDR and
+/// `ENTROPY_SRC_BASE_ADDR + ENTROPY_SRC_SIZE_BYTES`.
+pub const ENTROPY_SRC_SIZE_BYTES: usize = 0x100;
+
+/// Peripheral base address for edn0 in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const EDN0_BASE_ADDR: usize = 0x41170000;
+
+/// Peripheral size for edn0 in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #EDN0_BASE_ADDR and
+/// `EDN0_BASE_ADDR + EDN0_SIZE_BYTES`.
+pub const EDN0_SIZE_BYTES: usize = 0x80;
+
+/// Peripheral base address for edn1 in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const EDN1_BASE_ADDR: usize = 0x41180000;
+
+/// Peripheral size for edn1 in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #EDN1_BASE_ADDR and
+/// `EDN1_BASE_ADDR + EDN1_SIZE_BYTES`.
+pub const EDN1_SIZE_BYTES: usize = 0x80;
+
+/// Peripheral base address for regs device on sram_ctrl_main in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const SRAM_CTRL_MAIN_REGS_BASE_ADDR: usize = 0x411C0000;
+
+/// Peripheral size for regs device on sram_ctrl_main in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #SRAM_CTRL_MAIN_REGS_BASE_ADDR and
+/// `SRAM_CTRL_MAIN_REGS_BASE_ADDR + SRAM_CTRL_MAIN_REGS_SIZE_BYTES`.
+pub const SRAM_CTRL_MAIN_REGS_SIZE_BYTES: usize = 0x40;
+
+/// Peripheral base address for ram device on sram_ctrl_main in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const SRAM_CTRL_MAIN_RAM_BASE_ADDR: usize = 0x10000000;
+
+/// Peripheral size for ram device on sram_ctrl_main in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #SRAM_CTRL_MAIN_RAM_BASE_ADDR and
+/// `SRAM_CTRL_MAIN_RAM_BASE_ADDR + SRAM_CTRL_MAIN_RAM_SIZE_BYTES`.
+pub const SRAM_CTRL_MAIN_RAM_SIZE_BYTES: usize = 0x20000;
+
+/// Peripheral base address for regs device on rom_ctrl in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const ROM_CTRL_REGS_BASE_ADDR: usize = 0x411E0000;
+
+/// Peripheral size for regs device on rom_ctrl in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #ROM_CTRL_REGS_BASE_ADDR and
+/// `ROM_CTRL_REGS_BASE_ADDR + ROM_CTRL_REGS_SIZE_BYTES`.
+pub const ROM_CTRL_REGS_SIZE_BYTES: usize = 0x80;
+
+/// Peripheral base address for rom device on rom_ctrl in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const ROM_CTRL_ROM_BASE_ADDR: usize = 0x8000;
+
+/// Peripheral size for rom device on rom_ctrl in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #ROM_CTRL_ROM_BASE_ADDR and
+/// `ROM_CTRL_ROM_BASE_ADDR + ROM_CTRL_ROM_SIZE_BYTES`.
+pub const ROM_CTRL_ROM_SIZE_BYTES: usize = 0x8000;
+
+/// Peripheral base address for cfg device on rv_core_ibex in top earlgrey.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const RV_CORE_IBEX_CFG_BASE_ADDR: usize = 0x411F0000;
+
+/// Peripheral size for cfg device on rv_core_ibex in top earlgrey.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #RV_CORE_IBEX_CFG_BASE_ADDR and
+/// `RV_CORE_IBEX_CFG_BASE_ADDR + RV_CORE_IBEX_CFG_SIZE_BYTES`.
+pub const RV_CORE_IBEX_CFG_SIZE_BYTES: usize = 0x100;
+
+/// Memory base address for ram_ret_aon in top earlgrey.
+pub const RAM_RET_AON_BASE_ADDR: usize = 0x40600000;
+
+/// Memory size for ram_ret_aon in top earlgrey.
+pub const RAM_RET_AON_SIZE_BYTES: usize = 0x1000;
+
+/// Memory base address for eflash in top earlgrey.
+pub const EFLASH_BASE_ADDR: usize = 0x20000000;
+
+/// Memory size for eflash in top earlgrey.
+pub const EFLASH_SIZE_BYTES: usize = 0x100000;
+
+/// Memory base address for ram_main in top earlgrey.
+pub const RAM_MAIN_BASE_ADDR: usize = 0x10000000;
+
+/// Memory size for ram_main in top earlgrey.
+pub const RAM_MAIN_SIZE_BYTES: usize = 0x20000;
+
+/// Memory base address for rom in top earlgrey.
+pub const ROM_BASE_ADDR: usize = 0x8000;
+
+/// Memory size for rom in top earlgrey.
+pub const ROM_SIZE_BYTES: usize = 0x8000;
+
+/// PLIC Interrupt Source Peripheral.
+///
+/// Enumeration used to determine which peripheral asserted the corresponding
+/// interrupt.
+#[derive(Copy, Clone, PartialEq, Eq)]
+#[repr(u32)]
+pub enum PlicPeripheral {
+    /// Unknown Peripheral
+    Unknown = 0,
+    /// uart0
+    Uart0 = 1,
+    /// uart1
+    Uart1 = 2,
+    /// uart2
+    Uart2 = 3,
+    /// uart3
+    Uart3 = 4,
+    /// gpio
+    Gpio = 5,
+    /// spi_device
+    SpiDevice = 6,
+    /// i2c0
+    I2c0 = 7,
+    /// i2c1
+    I2c1 = 8,
+    /// i2c2
+    I2c2 = 9,
+    /// pattgen
+    Pattgen = 10,
+    /// rv_timer
+    RvTimer = 11,
+    /// otp_ctrl
+    OtpCtrl = 12,
+    /// alert_handler
+    AlertHandler = 13,
+    /// spi_host0
+    SpiHost0 = 14,
+    /// spi_host1
+    SpiHost1 = 15,
+    /// usbdev
+    Usbdev = 16,
+    /// pwrmgr_aon
+    PwrmgrAon = 17,
+    /// sysrst_ctrl_aon
+    SysrstCtrlAon = 18,
+    /// adc_ctrl_aon
+    AdcCtrlAon = 19,
+    /// aon_timer_aon
+    AonTimerAon = 20,
+    /// sensor_ctrl_aon
+    SensorCtrlAon = 21,
+    /// flash_ctrl
+    FlashCtrl = 22,
+    /// hmac
+    Hmac = 23,
+    /// kmac
+    Kmac = 24,
+    /// otbn
+    Otbn = 25,
+    /// keymgr
+    Keymgr = 26,
+    /// csrng
+    Csrng = 27,
+    /// entropy_src
+    EntropySrc = 28,
+    /// edn0
+    Edn0 = 29,
+    /// edn1
+    Edn1 = 30,
+}
+
+impl TryFrom<u32> for PlicPeripheral {
+    type Error = u32;
+    fn try_from(val: u32) -> Result<Self, Self::Error> {
+        match val {
+            0 => Ok(Self::Unknown),
+            1 => Ok(Self::Uart0),
+            2 => Ok(Self::Uart1),
+            3 => Ok(Self::Uart2),
+            4 => Ok(Self::Uart3),
+            5 => Ok(Self::Gpio),
+            6 => Ok(Self::SpiDevice),
+            7 => Ok(Self::I2c0),
+            8 => Ok(Self::I2c1),
+            9 => Ok(Self::I2c2),
+            10 => Ok(Self::Pattgen),
+            11 => Ok(Self::RvTimer),
+            12 => Ok(Self::OtpCtrl),
+            13 => Ok(Self::AlertHandler),
+            14 => Ok(Self::SpiHost0),
+            15 => Ok(Self::SpiHost1),
+            16 => Ok(Self::Usbdev),
+            17 => Ok(Self::PwrmgrAon),
+            18 => Ok(Self::SysrstCtrlAon),
+            19 => Ok(Self::AdcCtrlAon),
+            20 => Ok(Self::AonTimerAon),
+            21 => Ok(Self::SensorCtrlAon),
+            22 => Ok(Self::FlashCtrl),
+            23 => Ok(Self::Hmac),
+            24 => Ok(Self::Kmac),
+            25 => Ok(Self::Otbn),
+            26 => Ok(Self::Keymgr),
+            27 => Ok(Self::Csrng),
+            28 => Ok(Self::EntropySrc),
+            29 => Ok(Self::Edn0),
+            30 => Ok(Self::Edn1),
+            _ => Err(val),
+        }
+    }
+}
+
+/// PLIC Interrupt Source.
+///
+/// Enumeration of all PLIC interrupt sources. The interrupt sources belonging to
+/// the same peripheral are guaranteed to be consecutive.
+#[derive(Copy, Clone, PartialEq, Eq)]
+#[repr(u32)]
+pub enum PlicIrqId {
+    /// No Interrupt
+    None = 0,
+    /// uart0_tx_watermark
+    Uart0TxWatermark = 1,
+    /// uart0_rx_watermark
+    Uart0RxWatermark = 2,
+    /// uart0_tx_done
+    Uart0TxDone = 3,
+    /// uart0_rx_overflow
+    Uart0RxOverflow = 4,
+    /// uart0_rx_frame_err
+    Uart0RxFrameErr = 5,
+    /// uart0_rx_break_err
+    Uart0RxBreakErr = 6,
+    /// uart0_rx_timeout
+    Uart0RxTimeout = 7,
+    /// uart0_rx_parity_err
+    Uart0RxParityErr = 8,
+    /// uart0_tx_empty
+    Uart0TxEmpty = 9,
+    /// uart1_tx_watermark
+    Uart1TxWatermark = 10,
+    /// uart1_rx_watermark
+    Uart1RxWatermark = 11,
+    /// uart1_tx_done
+    Uart1TxDone = 12,
+    /// uart1_rx_overflow
+    Uart1RxOverflow = 13,
+    /// uart1_rx_frame_err
+    Uart1RxFrameErr = 14,
+    /// uart1_rx_break_err
+    Uart1RxBreakErr = 15,
+    /// uart1_rx_timeout
+    Uart1RxTimeout = 16,
+    /// uart1_rx_parity_err
+    Uart1RxParityErr = 17,
+    /// uart1_tx_empty
+    Uart1TxEmpty = 18,
+    /// uart2_tx_watermark
+    Uart2TxWatermark = 19,
+    /// uart2_rx_watermark
+    Uart2RxWatermark = 20,
+    /// uart2_tx_done
+    Uart2TxDone = 21,
+    /// uart2_rx_overflow
+    Uart2RxOverflow = 22,
+    /// uart2_rx_frame_err
+    Uart2RxFrameErr = 23,
+    /// uart2_rx_break_err
+    Uart2RxBreakErr = 24,
+    /// uart2_rx_timeout
+    Uart2RxTimeout = 25,
+    /// uart2_rx_parity_err
+    Uart2RxParityErr = 26,
+    /// uart2_tx_empty
+    Uart2TxEmpty = 27,
+    /// uart3_tx_watermark
+    Uart3TxWatermark = 28,
+    /// uart3_rx_watermark
+    Uart3RxWatermark = 29,
+    /// uart3_tx_done
+    Uart3TxDone = 30,
+    /// uart3_rx_overflow
+    Uart3RxOverflow = 31,
+    /// uart3_rx_frame_err
+    Uart3RxFrameErr = 32,
+    /// uart3_rx_break_err
+    Uart3RxBreakErr = 33,
+    /// uart3_rx_timeout
+    Uart3RxTimeout = 34,
+    /// uart3_rx_parity_err
+    Uart3RxParityErr = 35,
+    /// uart3_tx_empty
+    Uart3TxEmpty = 36,
+    /// gpio_gpio 0
+    GpioGpio0 = 37,
+    /// gpio_gpio 1
+    GpioGpio1 = 38,
+    /// gpio_gpio 2
+    GpioGpio2 = 39,
+    /// gpio_gpio 3
+    GpioGpio3 = 40,
+    /// gpio_gpio 4
+    GpioGpio4 = 41,
+    /// gpio_gpio 5
+    GpioGpio5 = 42,
+    /// gpio_gpio 6
+    GpioGpio6 = 43,
+    /// gpio_gpio 7
+    GpioGpio7 = 44,
+    /// gpio_gpio 8
+    GpioGpio8 = 45,
+    /// gpio_gpio 9
+    GpioGpio9 = 46,
+    /// gpio_gpio 10
+    GpioGpio10 = 47,
+    /// gpio_gpio 11
+    GpioGpio11 = 48,
+    /// gpio_gpio 12
+    GpioGpio12 = 49,
+    /// gpio_gpio 13
+    GpioGpio13 = 50,
+    /// gpio_gpio 14
+    GpioGpio14 = 51,
+    /// gpio_gpio 15
+    GpioGpio15 = 52,
+    /// gpio_gpio 16
+    GpioGpio16 = 53,
+    /// gpio_gpio 17
+    GpioGpio17 = 54,
+    /// gpio_gpio 18
+    GpioGpio18 = 55,
+    /// gpio_gpio 19
+    GpioGpio19 = 56,
+    /// gpio_gpio 20
+    GpioGpio20 = 57,
+    /// gpio_gpio 21
+    GpioGpio21 = 58,
+    /// gpio_gpio 22
+    GpioGpio22 = 59,
+    /// gpio_gpio 23
+    GpioGpio23 = 60,
+    /// gpio_gpio 24
+    GpioGpio24 = 61,
+    /// gpio_gpio 25
+    GpioGpio25 = 62,
+    /// gpio_gpio 26
+    GpioGpio26 = 63,
+    /// gpio_gpio 27
+    GpioGpio27 = 64,
+    /// gpio_gpio 28
+    GpioGpio28 = 65,
+    /// gpio_gpio 29
+    GpioGpio29 = 66,
+    /// gpio_gpio 30
+    GpioGpio30 = 67,
+    /// gpio_gpio 31
+    GpioGpio31 = 68,
+    /// spi_device_upload_cmdfifo_not_empty
+    SpiDeviceUploadCmdfifoNotEmpty = 69,
+    /// spi_device_upload_payload_not_empty
+    SpiDeviceUploadPayloadNotEmpty = 70,
+    /// spi_device_upload_payload_overflow
+    SpiDeviceUploadPayloadOverflow = 71,
+    /// spi_device_readbuf_watermark
+    SpiDeviceReadbufWatermark = 72,
+    /// spi_device_readbuf_flip
+    SpiDeviceReadbufFlip = 73,
+    /// spi_device_tpm_header_not_empty
+    SpiDeviceTpmHeaderNotEmpty = 74,
+    /// spi_device_tpm_rdfifo_cmd_end
+    SpiDeviceTpmRdfifoCmdEnd = 75,
+    /// spi_device_tpm_rdfifo_drop
+    SpiDeviceTpmRdfifoDrop = 76,
+    /// i2c0_fmt_threshold
+    I2c0FmtThreshold = 77,
+    /// i2c0_rx_threshold
+    I2c0RxThreshold = 78,
+    /// i2c0_acq_threshold
+    I2c0AcqThreshold = 79,
+    /// i2c0_rx_overflow
+    I2c0RxOverflow = 80,
+    /// i2c0_controller_halt
+    I2c0ControllerHalt = 81,
+    /// i2c0_scl_interference
+    I2c0SclInterference = 82,
+    /// i2c0_sda_interference
+    I2c0SdaInterference = 83,
+    /// i2c0_stretch_timeout
+    I2c0StretchTimeout = 84,
+    /// i2c0_sda_unstable
+    I2c0SdaUnstable = 85,
+    /// i2c0_cmd_complete
+    I2c0CmdComplete = 86,
+    /// i2c0_tx_stretch
+    I2c0TxStretch = 87,
+    /// i2c0_tx_threshold
+    I2c0TxThreshold = 88,
+    /// i2c0_acq_stretch
+    I2c0AcqStretch = 89,
+    /// i2c0_unexp_stop
+    I2c0UnexpStop = 90,
+    /// i2c0_host_timeout
+    I2c0HostTimeout = 91,
+    /// i2c1_fmt_threshold
+    I2c1FmtThreshold = 92,
+    /// i2c1_rx_threshold
+    I2c1RxThreshold = 93,
+    /// i2c1_acq_threshold
+    I2c1AcqThreshold = 94,
+    /// i2c1_rx_overflow
+    I2c1RxOverflow = 95,
+    /// i2c1_controller_halt
+    I2c1ControllerHalt = 96,
+    /// i2c1_scl_interference
+    I2c1SclInterference = 97,
+    /// i2c1_sda_interference
+    I2c1SdaInterference = 98,
+    /// i2c1_stretch_timeout
+    I2c1StretchTimeout = 99,
+    /// i2c1_sda_unstable
+    I2c1SdaUnstable = 100,
+    /// i2c1_cmd_complete
+    I2c1CmdComplete = 101,
+    /// i2c1_tx_stretch
+    I2c1TxStretch = 102,
+    /// i2c1_tx_threshold
+    I2c1TxThreshold = 103,
+    /// i2c1_acq_stretch
+    I2c1AcqStretch = 104,
+    /// i2c1_unexp_stop
+    I2c1UnexpStop = 105,
+    /// i2c1_host_timeout
+    I2c1HostTimeout = 106,
+    /// i2c2_fmt_threshold
+    I2c2FmtThreshold = 107,
+    /// i2c2_rx_threshold
+    I2c2RxThreshold = 108,
+    /// i2c2_acq_threshold
+    I2c2AcqThreshold = 109,
+    /// i2c2_rx_overflow
+    I2c2RxOverflow = 110,
+    /// i2c2_controller_halt
+    I2c2ControllerHalt = 111,
+    /// i2c2_scl_interference
+    I2c2SclInterference = 112,
+    /// i2c2_sda_interference
+    I2c2SdaInterference = 113,
+    /// i2c2_stretch_timeout
+    I2c2StretchTimeout = 114,
+    /// i2c2_sda_unstable
+    I2c2SdaUnstable = 115,
+    /// i2c2_cmd_complete
+    I2c2CmdComplete = 116,
+    /// i2c2_tx_stretch
+    I2c2TxStretch = 117,
+    /// i2c2_tx_threshold
+    I2c2TxThreshold = 118,
+    /// i2c2_acq_stretch
+    I2c2AcqStretch = 119,
+    /// i2c2_unexp_stop
+    I2c2UnexpStop = 120,
+    /// i2c2_host_timeout
+    I2c2HostTimeout = 121,
+    /// pattgen_done_ch0
+    PattgenDoneCh0 = 122,
+    /// pattgen_done_ch1
+    PattgenDoneCh1 = 123,
+    /// rv_timer_timer_expired_hart0_timer0
+    RvTimerTimerExpiredHart0Timer0 = 124,
+    /// otp_ctrl_otp_operation_done
+    OtpCtrlOtpOperationDone = 125,
+    /// otp_ctrl_otp_error
+    OtpCtrlOtpError = 126,
+    /// alert_handler_classa
+    AlertHandlerClassa = 127,
+    /// alert_handler_classb
+    AlertHandlerClassb = 128,
+    /// alert_handler_classc
+    AlertHandlerClassc = 129,
+    /// alert_handler_classd
+    AlertHandlerClassd = 130,
+    /// spi_host0_error
+    SpiHost0Error = 131,
+    /// spi_host0_spi_event
+    SpiHost0SpiEvent = 132,
+    /// spi_host1_error
+    SpiHost1Error = 133,
+    /// spi_host1_spi_event
+    SpiHost1SpiEvent = 134,
+    /// usbdev_pkt_received
+    UsbdevPktReceived = 135,
+    /// usbdev_pkt_sent
+    UsbdevPktSent = 136,
+    /// usbdev_disconnected
+    UsbdevDisconnected = 137,
+    /// usbdev_host_lost
+    UsbdevHostLost = 138,
+    /// usbdev_link_reset
+    UsbdevLinkReset = 139,
+    /// usbdev_link_suspend
+    UsbdevLinkSuspend = 140,
+    /// usbdev_link_resume
+    UsbdevLinkResume = 141,
+    /// usbdev_av_out_empty
+    UsbdevAvOutEmpty = 142,
+    /// usbdev_rx_full
+    UsbdevRxFull = 143,
+    /// usbdev_av_overflow
+    UsbdevAvOverflow = 144,
+    /// usbdev_link_in_err
+    UsbdevLinkInErr = 145,
+    /// usbdev_rx_crc_err
+    UsbdevRxCrcErr = 146,
+    /// usbdev_rx_pid_err
+    UsbdevRxPidErr = 147,
+    /// usbdev_rx_bitstuff_err
+    UsbdevRxBitstuffErr = 148,
+    /// usbdev_frame
+    UsbdevFrame = 149,
+    /// usbdev_powered
+    UsbdevPowered = 150,
+    /// usbdev_link_out_err
+    UsbdevLinkOutErr = 151,
+    /// usbdev_av_setup_empty
+    UsbdevAvSetupEmpty = 152,
+    /// pwrmgr_aon_wakeup
+    PwrmgrAonWakeup = 153,
+    /// sysrst_ctrl_aon_event_detected
+    SysrstCtrlAonEventDetected = 154,
+    /// adc_ctrl_aon_match_pending
+    AdcCtrlAonMatchPending = 155,
+    /// aon_timer_aon_wkup_timer_expired
+    AonTimerAonWkupTimerExpired = 156,
+    /// aon_timer_aon_wdog_timer_bark
+    AonTimerAonWdogTimerBark = 157,
+    /// sensor_ctrl_aon_io_status_change
+    SensorCtrlAonIoStatusChange = 158,
+    /// sensor_ctrl_aon_init_status_change
+    SensorCtrlAonInitStatusChange = 159,
+    /// flash_ctrl_prog_empty
+    FlashCtrlProgEmpty = 160,
+    /// flash_ctrl_prog_lvl
+    FlashCtrlProgLvl = 161,
+    /// flash_ctrl_rd_full
+    FlashCtrlRdFull = 162,
+    /// flash_ctrl_rd_lvl
+    FlashCtrlRdLvl = 163,
+    /// flash_ctrl_op_done
+    FlashCtrlOpDone = 164,
+    /// flash_ctrl_corr_err
+    FlashCtrlCorrErr = 165,
+    /// hmac_hmac_done
+    HmacHmacDone = 166,
+    /// hmac_fifo_empty
+    HmacFifoEmpty = 167,
+    /// hmac_hmac_err
+    HmacHmacErr = 168,
+    /// kmac_kmac_done
+    KmacKmacDone = 169,
+    /// kmac_fifo_empty
+    KmacFifoEmpty = 170,
+    /// kmac_kmac_err
+    KmacKmacErr = 171,
+    /// otbn_done
+    OtbnDone = 172,
+    /// keymgr_op_done
+    KeymgrOpDone = 173,
+    /// csrng_cs_cmd_req_done
+    CsrngCsCmdReqDone = 174,
+    /// csrng_cs_entropy_req
+    CsrngCsEntropyReq = 175,
+    /// csrng_cs_hw_inst_exc
+    CsrngCsHwInstExc = 176,
+    /// csrng_cs_fatal_err
+    CsrngCsFatalErr = 177,
+    /// entropy_src_es_entropy_valid
+    EntropySrcEsEntropyValid = 178,
+    /// entropy_src_es_health_test_failed
+    EntropySrcEsHealthTestFailed = 179,
+    /// entropy_src_es_observe_fifo_ready
+    EntropySrcEsObserveFifoReady = 180,
+    /// entropy_src_es_fatal_err
+    EntropySrcEsFatalErr = 181,
+    /// edn0_edn_cmd_req_done
+    Edn0EdnCmdReqDone = 182,
+    /// edn0_edn_fatal_err
+    Edn0EdnFatalErr = 183,
+    /// edn1_edn_cmd_req_done
+    Edn1EdnCmdReqDone = 184,
+    /// edn1_edn_fatal_err
+    Edn1EdnFatalErr = 185,
+}
+
+impl TryFrom<u32> for PlicIrqId {
+    type Error = u32;
+    fn try_from(val: u32) -> Result<Self, Self::Error> {
+        match val {
+            0 => Ok(Self::None),
+            1 => Ok(Self::Uart0TxWatermark),
+            2 => Ok(Self::Uart0RxWatermark),
+            3 => Ok(Self::Uart0TxDone),
+            4 => Ok(Self::Uart0RxOverflow),
+            5 => Ok(Self::Uart0RxFrameErr),
+            6 => Ok(Self::Uart0RxBreakErr),
+            7 => Ok(Self::Uart0RxTimeout),
+            8 => Ok(Self::Uart0RxParityErr),
+            9 => Ok(Self::Uart0TxEmpty),
+            10 => Ok(Self::Uart1TxWatermark),
+            11 => Ok(Self::Uart1RxWatermark),
+            12 => Ok(Self::Uart1TxDone),
+            13 => Ok(Self::Uart1RxOverflow),
+            14 => Ok(Self::Uart1RxFrameErr),
+            15 => Ok(Self::Uart1RxBreakErr),
+            16 => Ok(Self::Uart1RxTimeout),
+            17 => Ok(Self::Uart1RxParityErr),
+            18 => Ok(Self::Uart1TxEmpty),
+            19 => Ok(Self::Uart2TxWatermark),
+            20 => Ok(Self::Uart2RxWatermark),
+            21 => Ok(Self::Uart2TxDone),
+            22 => Ok(Self::Uart2RxOverflow),
+            23 => Ok(Self::Uart2RxFrameErr),
+            24 => Ok(Self::Uart2RxBreakErr),
+            25 => Ok(Self::Uart2RxTimeout),
+            26 => Ok(Self::Uart2RxParityErr),
+            27 => Ok(Self::Uart2TxEmpty),
+            28 => Ok(Self::Uart3TxWatermark),
+            29 => Ok(Self::Uart3RxWatermark),
+            30 => Ok(Self::Uart3TxDone),
+            31 => Ok(Self::Uart3RxOverflow),
+            32 => Ok(Self::Uart3RxFrameErr),
+            33 => Ok(Self::Uart3RxBreakErr),
+            34 => Ok(Self::Uart3RxTimeout),
+            35 => Ok(Self::Uart3RxParityErr),
+            36 => Ok(Self::Uart3TxEmpty),
+            37 => Ok(Self::GpioGpio0),
+            38 => Ok(Self::GpioGpio1),
+            39 => Ok(Self::GpioGpio2),
+            40 => Ok(Self::GpioGpio3),
+            41 => Ok(Self::GpioGpio4),
+            42 => Ok(Self::GpioGpio5),
+            43 => Ok(Self::GpioGpio6),
+            44 => Ok(Self::GpioGpio7),
+            45 => Ok(Self::GpioGpio8),
+            46 => Ok(Self::GpioGpio9),
+            47 => Ok(Self::GpioGpio10),
+            48 => Ok(Self::GpioGpio11),
+            49 => Ok(Self::GpioGpio12),
+            50 => Ok(Self::GpioGpio13),
+            51 => Ok(Self::GpioGpio14),
+            52 => Ok(Self::GpioGpio15),
+            53 => Ok(Self::GpioGpio16),
+            54 => Ok(Self::GpioGpio17),
+            55 => Ok(Self::GpioGpio18),
+            56 => Ok(Self::GpioGpio19),
+            57 => Ok(Self::GpioGpio20),
+            58 => Ok(Self::GpioGpio21),
+            59 => Ok(Self::GpioGpio22),
+            60 => Ok(Self::GpioGpio23),
+            61 => Ok(Self::GpioGpio24),
+            62 => Ok(Self::GpioGpio25),
+            63 => Ok(Self::GpioGpio26),
+            64 => Ok(Self::GpioGpio27),
+            65 => Ok(Self::GpioGpio28),
+            66 => Ok(Self::GpioGpio29),
+            67 => Ok(Self::GpioGpio30),
+            68 => Ok(Self::GpioGpio31),
+            69 => Ok(Self::SpiDeviceUploadCmdfifoNotEmpty),
+            70 => Ok(Self::SpiDeviceUploadPayloadNotEmpty),
+            71 => Ok(Self::SpiDeviceUploadPayloadOverflow),
+            72 => Ok(Self::SpiDeviceReadbufWatermark),
+            73 => Ok(Self::SpiDeviceReadbufFlip),
+            74 => Ok(Self::SpiDeviceTpmHeaderNotEmpty),
+            75 => Ok(Self::SpiDeviceTpmRdfifoCmdEnd),
+            76 => Ok(Self::SpiDeviceTpmRdfifoDrop),
+            77 => Ok(Self::I2c0FmtThreshold),
+            78 => Ok(Self::I2c0RxThreshold),
+            79 => Ok(Self::I2c0AcqThreshold),
+            80 => Ok(Self::I2c0RxOverflow),
+            81 => Ok(Self::I2c0ControllerHalt),
+            82 => Ok(Self::I2c0SclInterference),
+            83 => Ok(Self::I2c0SdaInterference),
+            84 => Ok(Self::I2c0StretchTimeout),
+            85 => Ok(Self::I2c0SdaUnstable),
+            86 => Ok(Self::I2c0CmdComplete),
+            87 => Ok(Self::I2c0TxStretch),
+            88 => Ok(Self::I2c0TxThreshold),
+            89 => Ok(Self::I2c0AcqStretch),
+            90 => Ok(Self::I2c0UnexpStop),
+            91 => Ok(Self::I2c0HostTimeout),
+            92 => Ok(Self::I2c1FmtThreshold),
+            93 => Ok(Self::I2c1RxThreshold),
+            94 => Ok(Self::I2c1AcqThreshold),
+            95 => Ok(Self::I2c1RxOverflow),
+            96 => Ok(Self::I2c1ControllerHalt),
+            97 => Ok(Self::I2c1SclInterference),
+            98 => Ok(Self::I2c1SdaInterference),
+            99 => Ok(Self::I2c1StretchTimeout),
+            100 => Ok(Self::I2c1SdaUnstable),
+            101 => Ok(Self::I2c1CmdComplete),
+            102 => Ok(Self::I2c1TxStretch),
+            103 => Ok(Self::I2c1TxThreshold),
+            104 => Ok(Self::I2c1AcqStretch),
+            105 => Ok(Self::I2c1UnexpStop),
+            106 => Ok(Self::I2c1HostTimeout),
+            107 => Ok(Self::I2c2FmtThreshold),
+            108 => Ok(Self::I2c2RxThreshold),
+            109 => Ok(Self::I2c2AcqThreshold),
+            110 => Ok(Self::I2c2RxOverflow),
+            111 => Ok(Self::I2c2ControllerHalt),
+            112 => Ok(Self::I2c2SclInterference),
+            113 => Ok(Self::I2c2SdaInterference),
+            114 => Ok(Self::I2c2StretchTimeout),
+            115 => Ok(Self::I2c2SdaUnstable),
+            116 => Ok(Self::I2c2CmdComplete),
+            117 => Ok(Self::I2c2TxStretch),
+            118 => Ok(Self::I2c2TxThreshold),
+            119 => Ok(Self::I2c2AcqStretch),
+            120 => Ok(Self::I2c2UnexpStop),
+            121 => Ok(Self::I2c2HostTimeout),
+            122 => Ok(Self::PattgenDoneCh0),
+            123 => Ok(Self::PattgenDoneCh1),
+            124 => Ok(Self::RvTimerTimerExpiredHart0Timer0),
+            125 => Ok(Self::OtpCtrlOtpOperationDone),
+            126 => Ok(Self::OtpCtrlOtpError),
+            127 => Ok(Self::AlertHandlerClassa),
+            128 => Ok(Self::AlertHandlerClassb),
+            129 => Ok(Self::AlertHandlerClassc),
+            130 => Ok(Self::AlertHandlerClassd),
+            131 => Ok(Self::SpiHost0Error),
+            132 => Ok(Self::SpiHost0SpiEvent),
+            133 => Ok(Self::SpiHost1Error),
+            134 => Ok(Self::SpiHost1SpiEvent),
+            135 => Ok(Self::UsbdevPktReceived),
+            136 => Ok(Self::UsbdevPktSent),
+            137 => Ok(Self::UsbdevDisconnected),
+            138 => Ok(Self::UsbdevHostLost),
+            139 => Ok(Self::UsbdevLinkReset),
+            140 => Ok(Self::UsbdevLinkSuspend),
+            141 => Ok(Self::UsbdevLinkResume),
+            142 => Ok(Self::UsbdevAvOutEmpty),
+            143 => Ok(Self::UsbdevRxFull),
+            144 => Ok(Self::UsbdevAvOverflow),
+            145 => Ok(Self::UsbdevLinkInErr),
+            146 => Ok(Self::UsbdevRxCrcErr),
+            147 => Ok(Self::UsbdevRxPidErr),
+            148 => Ok(Self::UsbdevRxBitstuffErr),
+            149 => Ok(Self::UsbdevFrame),
+            150 => Ok(Self::UsbdevPowered),
+            151 => Ok(Self::UsbdevLinkOutErr),
+            152 => Ok(Self::UsbdevAvSetupEmpty),
+            153 => Ok(Self::PwrmgrAonWakeup),
+            154 => Ok(Self::SysrstCtrlAonEventDetected),
+            155 => Ok(Self::AdcCtrlAonMatchPending),
+            156 => Ok(Self::AonTimerAonWkupTimerExpired),
+            157 => Ok(Self::AonTimerAonWdogTimerBark),
+            158 => Ok(Self::SensorCtrlAonIoStatusChange),
+            159 => Ok(Self::SensorCtrlAonInitStatusChange),
+            160 => Ok(Self::FlashCtrlProgEmpty),
+            161 => Ok(Self::FlashCtrlProgLvl),
+            162 => Ok(Self::FlashCtrlRdFull),
+            163 => Ok(Self::FlashCtrlRdLvl),
+            164 => Ok(Self::FlashCtrlOpDone),
+            165 => Ok(Self::FlashCtrlCorrErr),
+            166 => Ok(Self::HmacHmacDone),
+            167 => Ok(Self::HmacFifoEmpty),
+            168 => Ok(Self::HmacHmacErr),
+            169 => Ok(Self::KmacKmacDone),
+            170 => Ok(Self::KmacFifoEmpty),
+            171 => Ok(Self::KmacKmacErr),
+            172 => Ok(Self::OtbnDone),
+            173 => Ok(Self::KeymgrOpDone),
+            174 => Ok(Self::CsrngCsCmdReqDone),
+            175 => Ok(Self::CsrngCsEntropyReq),
+            176 => Ok(Self::CsrngCsHwInstExc),
+            177 => Ok(Self::CsrngCsFatalErr),
+            178 => Ok(Self::EntropySrcEsEntropyValid),
+            179 => Ok(Self::EntropySrcEsHealthTestFailed),
+            180 => Ok(Self::EntropySrcEsObserveFifoReady),
+            181 => Ok(Self::EntropySrcEsFatalErr),
+            182 => Ok(Self::Edn0EdnCmdReqDone),
+            183 => Ok(Self::Edn0EdnFatalErr),
+            184 => Ok(Self::Edn1EdnCmdReqDone),
+            185 => Ok(Self::Edn1EdnFatalErr),
+            _ => Err(val),
+        }
+    }
+}
+
+/// PLIC Interrupt Target.
+///
+/// Enumeration used to determine which set of IE, CC, threshold registers to
+/// access for a given interrupt target.
+#[derive(Copy, Clone, PartialEq, Eq)]
+#[repr(u32)]
+pub enum PlicTarget {
+    /// Ibex Core 0
+    Ibex0 = 0,
+}
+
+/// Alert Handler Source Peripheral.
+///
+/// Enumeration used to determine which peripheral asserted the corresponding
+/// alert.
+#[derive(Copy, Clone, PartialEq, Eq)]
+#[repr(u32)]
+pub enum AlertPeripheral {
+    /// uart0
+    Uart0 = 0,
+    /// uart1
+    Uart1 = 1,
+    /// uart2
+    Uart2 = 2,
+    /// uart3
+    Uart3 = 3,
+    /// gpio
+    Gpio = 4,
+    /// spi_device
+    SpiDevice = 5,
+    /// i2c0
+    I2c0 = 6,
+    /// i2c1
+    I2c1 = 7,
+    /// i2c2
+    I2c2 = 8,
+    /// pattgen
+    Pattgen = 9,
+    /// rv_timer
+    RvTimer = 10,
+    /// otp_ctrl
+    OtpCtrl = 11,
+    /// lc_ctrl
+    LcCtrl = 12,
+    /// spi_host0
+    SpiHost0 = 13,
+    /// spi_host1
+    SpiHost1 = 14,
+    /// usbdev
+    Usbdev = 15,
+    /// pwrmgr_aon
+    PwrmgrAon = 16,
+    /// rstmgr_aon
+    RstmgrAon = 17,
+    /// clkmgr_aon
+    ClkmgrAon = 18,
+    /// sysrst_ctrl_aon
+    SysrstCtrlAon = 19,
+    /// adc_ctrl_aon
+    AdcCtrlAon = 20,
+    /// pwm_aon
+    PwmAon = 21,
+    /// pinmux_aon
+    PinmuxAon = 22,
+    /// aon_timer_aon
+    AonTimerAon = 23,
+    /// sensor_ctrl_aon
+    SensorCtrlAon = 24,
+    /// sram_ctrl_ret_aon
+    SramCtrlRetAon = 25,
+    /// flash_ctrl
+    FlashCtrl = 26,
+    /// rv_dm
+    RvDm = 27,
+    /// rv_plic
+    RvPlic = 28,
+    /// aes
+    Aes = 29,
+    /// hmac
+    Hmac = 30,
+    /// kmac
+    Kmac = 31,
+    /// otbn
+    Otbn = 32,
+    /// keymgr
+    Keymgr = 33,
+    /// csrng
+    Csrng = 34,
+    /// entropy_src
+    EntropySrc = 35,
+    /// edn0
+    Edn0 = 36,
+    /// edn1
+    Edn1 = 37,
+    /// sram_ctrl_main
+    SramCtrlMain = 38,
+    /// rom_ctrl
+    RomCtrl = 39,
+    /// rv_core_ibex
+    RvCoreIbex = 40,
+}
+
+/// Alert Handler Alert Source.
+///
+/// Enumeration of all Alert Handler Alert Sources. The alert sources belonging to
+/// the same peripheral are guaranteed to be consecutive.
+#[derive(Copy, Clone, PartialEq, Eq)]
+#[repr(u32)]
+pub enum AlertId {
+    /// uart0_fatal_fault
+    Uart0FatalFault = 0,
+    /// uart1_fatal_fault
+    Uart1FatalFault = 1,
+    /// uart2_fatal_fault
+    Uart2FatalFault = 2,
+    /// uart3_fatal_fault
+    Uart3FatalFault = 3,
+    /// gpio_fatal_fault
+    GpioFatalFault = 4,
+    /// spi_device_fatal_fault
+    SpiDeviceFatalFault = 5,
+    /// i2c0_fatal_fault
+    I2c0FatalFault = 6,
+    /// i2c1_fatal_fault
+    I2c1FatalFault = 7,
+    /// i2c2_fatal_fault
+    I2c2FatalFault = 8,
+    /// pattgen_fatal_fault
+    PattgenFatalFault = 9,
+    /// rv_timer_fatal_fault
+    RvTimerFatalFault = 10,
+    /// otp_ctrl_fatal_macro_error
+    OtpCtrlFatalMacroError = 11,
+    /// otp_ctrl_fatal_check_error
+    OtpCtrlFatalCheckError = 12,
+    /// otp_ctrl_fatal_bus_integ_error
+    OtpCtrlFatalBusIntegError = 13,
+    /// otp_ctrl_fatal_prim_otp_alert
+    OtpCtrlFatalPrimOtpAlert = 14,
+    /// otp_ctrl_recov_prim_otp_alert
+    OtpCtrlRecovPrimOtpAlert = 15,
+    /// lc_ctrl_fatal_prog_error
+    LcCtrlFatalProgError = 16,
+    /// lc_ctrl_fatal_state_error
+    LcCtrlFatalStateError = 17,
+    /// lc_ctrl_fatal_bus_integ_error
+    LcCtrlFatalBusIntegError = 18,
+    /// spi_host0_fatal_fault
+    SpiHost0FatalFault = 19,
+    /// spi_host1_fatal_fault
+    SpiHost1FatalFault = 20,
+    /// usbdev_fatal_fault
+    UsbdevFatalFault = 21,
+    /// pwrmgr_aon_fatal_fault
+    PwrmgrAonFatalFault = 22,
+    /// rstmgr_aon_fatal_fault
+    RstmgrAonFatalFault = 23,
+    /// rstmgr_aon_fatal_cnsty_fault
+    RstmgrAonFatalCnstyFault = 24,
+    /// clkmgr_aon_recov_fault
+    ClkmgrAonRecovFault = 25,
+    /// clkmgr_aon_fatal_fault
+    ClkmgrAonFatalFault = 26,
+    /// sysrst_ctrl_aon_fatal_fault
+    SysrstCtrlAonFatalFault = 27,
+    /// adc_ctrl_aon_fatal_fault
+    AdcCtrlAonFatalFault = 28,
+    /// pwm_aon_fatal_fault
+    PwmAonFatalFault = 29,
+    /// pinmux_aon_fatal_fault
+    PinmuxAonFatalFault = 30,
+    /// aon_timer_aon_fatal_fault
+    AonTimerAonFatalFault = 31,
+    /// sensor_ctrl_aon_recov_alert
+    SensorCtrlAonRecovAlert = 32,
+    /// sensor_ctrl_aon_fatal_alert
+    SensorCtrlAonFatalAlert = 33,
+    /// sram_ctrl_ret_aon_fatal_error
+    SramCtrlRetAonFatalError = 34,
+    /// flash_ctrl_recov_err
+    FlashCtrlRecovErr = 35,
+    /// flash_ctrl_fatal_std_err
+    FlashCtrlFatalStdErr = 36,
+    /// flash_ctrl_fatal_err
+    FlashCtrlFatalErr = 37,
+    /// flash_ctrl_fatal_prim_flash_alert
+    FlashCtrlFatalPrimFlashAlert = 38,
+    /// flash_ctrl_recov_prim_flash_alert
+    FlashCtrlRecovPrimFlashAlert = 39,
+    /// rv_dm_fatal_fault
+    RvDmFatalFault = 40,
+    /// rv_plic_fatal_fault
+    RvPlicFatalFault = 41,
+    /// aes_recov_ctrl_update_err
+    AesRecovCtrlUpdateErr = 42,
+    /// aes_fatal_fault
+    AesFatalFault = 43,
+    /// hmac_fatal_fault
+    HmacFatalFault = 44,
+    /// kmac_recov_operation_err
+    KmacRecovOperationErr = 45,
+    /// kmac_fatal_fault_err
+    KmacFatalFaultErr = 46,
+    /// otbn_fatal
+    OtbnFatal = 47,
+    /// otbn_recov
+    OtbnRecov = 48,
+    /// keymgr_recov_operation_err
+    KeymgrRecovOperationErr = 49,
+    /// keymgr_fatal_fault_err
+    KeymgrFatalFaultErr = 50,
+    /// csrng_recov_alert
+    CsrngRecovAlert = 51,
+    /// csrng_fatal_alert
+    CsrngFatalAlert = 52,
+    /// entropy_src_recov_alert
+    EntropySrcRecovAlert = 53,
+    /// entropy_src_fatal_alert
+    EntropySrcFatalAlert = 54,
+    /// edn0_recov_alert
+    Edn0RecovAlert = 55,
+    /// edn0_fatal_alert
+    Edn0FatalAlert = 56,
+    /// edn1_recov_alert
+    Edn1RecovAlert = 57,
+    /// edn1_fatal_alert
+    Edn1FatalAlert = 58,
+    /// sram_ctrl_main_fatal_error
+    SramCtrlMainFatalError = 59,
+    /// rom_ctrl_fatal
+    RomCtrlFatal = 60,
+    /// rv_core_ibex_fatal_sw_err
+    RvCoreIbexFatalSwErr = 61,
+    /// rv_core_ibex_recov_sw_err
+    RvCoreIbexRecovSwErr = 62,
+    /// rv_core_ibex_fatal_hw_err
+    RvCoreIbexFatalHwErr = 63,
+    /// rv_core_ibex_recov_hw_err
+    RvCoreIbexRecovHwErr = 64,
+}
+
+impl TryFrom<u32> for AlertId {
+    type Error = u32;
+    fn try_from(val: u32) -> Result<Self, Self::Error> {
+        match val {
+            0 => Ok(Self::Uart0FatalFault),
+            1 => Ok(Self::Uart1FatalFault),
+            2 => Ok(Self::Uart2FatalFault),
+            3 => Ok(Self::Uart3FatalFault),
+            4 => Ok(Self::GpioFatalFault),
+            5 => Ok(Self::SpiDeviceFatalFault),
+            6 => Ok(Self::I2c0FatalFault),
+            7 => Ok(Self::I2c1FatalFault),
+            8 => Ok(Self::I2c2FatalFault),
+            9 => Ok(Self::PattgenFatalFault),
+            10 => Ok(Self::RvTimerFatalFault),
+            11 => Ok(Self::OtpCtrlFatalMacroError),
+            12 => Ok(Self::OtpCtrlFatalCheckError),
+            13 => Ok(Self::OtpCtrlFatalBusIntegError),
+            14 => Ok(Self::OtpCtrlFatalPrimOtpAlert),
+            15 => Ok(Self::OtpCtrlRecovPrimOtpAlert),
+            16 => Ok(Self::LcCtrlFatalProgError),
+            17 => Ok(Self::LcCtrlFatalStateError),
+            18 => Ok(Self::LcCtrlFatalBusIntegError),
+            19 => Ok(Self::SpiHost0FatalFault),
+            20 => Ok(Self::SpiHost1FatalFault),
+            21 => Ok(Self::UsbdevFatalFault),
+            22 => Ok(Self::PwrmgrAonFatalFault),
+            23 => Ok(Self::RstmgrAonFatalFault),
+            24 => Ok(Self::RstmgrAonFatalCnstyFault),
+            25 => Ok(Self::ClkmgrAonRecovFault),
+            26 => Ok(Self::ClkmgrAonFatalFault),
+            27 => Ok(Self::SysrstCtrlAonFatalFault),
+            28 => Ok(Self::AdcCtrlAonFatalFault),
+            29 => Ok(Self::PwmAonFatalFault),
+            30 => Ok(Self::PinmuxAonFatalFault),
+            31 => Ok(Self::AonTimerAonFatalFault),
+            32 => Ok(Self::SensorCtrlAonRecovAlert),
+            33 => Ok(Self::SensorCtrlAonFatalAlert),
+            34 => Ok(Self::SramCtrlRetAonFatalError),
+            35 => Ok(Self::FlashCtrlRecovErr),
+            36 => Ok(Self::FlashCtrlFatalStdErr),
+            37 => Ok(Self::FlashCtrlFatalErr),
+            38 => Ok(Self::FlashCtrlFatalPrimFlashAlert),
+            39 => Ok(Self::FlashCtrlRecovPrimFlashAlert),
+            40 => Ok(Self::RvDmFatalFault),
+            41 => Ok(Self::RvPlicFatalFault),
+            42 => Ok(Self::AesRecovCtrlUpdateErr),
+            43 => Ok(Self::AesFatalFault),
+            44 => Ok(Self::HmacFatalFault),
+            45 => Ok(Self::KmacRecovOperationErr),
+            46 => Ok(Self::KmacFatalFaultErr),
+            47 => Ok(Self::OtbnFatal),
+            48 => Ok(Self::OtbnRecov),
+            49 => Ok(Self::KeymgrRecovOperationErr),
+            50 => Ok(Self::KeymgrFatalFaultErr),
+            51 => Ok(Self::CsrngRecovAlert),
+            52 => Ok(Self::CsrngFatalAlert),
+            53 => Ok(Self::EntropySrcRecovAlert),
+            54 => Ok(Self::EntropySrcFatalAlert),
+            55 => Ok(Self::Edn0RecovAlert),
+            56 => Ok(Self::Edn0FatalAlert),
+            57 => Ok(Self::Edn1RecovAlert),
+            58 => Ok(Self::Edn1FatalAlert),
+            59 => Ok(Self::SramCtrlMainFatalError),
+            60 => Ok(Self::RomCtrlFatal),
+            61 => Ok(Self::RvCoreIbexFatalSwErr),
+            62 => Ok(Self::RvCoreIbexRecovSwErr),
+            63 => Ok(Self::RvCoreIbexFatalHwErr),
+            64 => Ok(Self::RvCoreIbexRecovHwErr),
+            _ => Err(val),
+        }
+    }
+}
+
+/// PLIC Interrupt Source to Peripheral Map
+///
+/// This array is a mapping from `PlicIrqId` to
+/// `PlicPeripheral`.
+pub const PLIC_INTERRUPT_FOR_PERIPHERAL: [PlicPeripheral; 186] = [
+    // None -> PlicPeripheral::Unknown
+    PlicPeripheral::Unknown,
+    // Uart0TxWatermark -> PlicPeripheral::Uart0
+    PlicPeripheral::Uart0,
+    // Uart0RxWatermark -> PlicPeripheral::Uart0
+    PlicPeripheral::Uart0,
+    // Uart0TxDone -> PlicPeripheral::Uart0
+    PlicPeripheral::Uart0,
+    // Uart0RxOverflow -> PlicPeripheral::Uart0
+    PlicPeripheral::Uart0,
+    // Uart0RxFrameErr -> PlicPeripheral::Uart0
+    PlicPeripheral::Uart0,
+    // Uart0RxBreakErr -> PlicPeripheral::Uart0
+    PlicPeripheral::Uart0,
+    // Uart0RxTimeout -> PlicPeripheral::Uart0
+    PlicPeripheral::Uart0,
+    // Uart0RxParityErr -> PlicPeripheral::Uart0
+    PlicPeripheral::Uart0,
+    // Uart0TxEmpty -> PlicPeripheral::Uart0
+    PlicPeripheral::Uart0,
+    // Uart1TxWatermark -> PlicPeripheral::Uart1
+    PlicPeripheral::Uart1,
+    // Uart1RxWatermark -> PlicPeripheral::Uart1
+    PlicPeripheral::Uart1,
+    // Uart1TxDone -> PlicPeripheral::Uart1
+    PlicPeripheral::Uart1,
+    // Uart1RxOverflow -> PlicPeripheral::Uart1
+    PlicPeripheral::Uart1,
+    // Uart1RxFrameErr -> PlicPeripheral::Uart1
+    PlicPeripheral::Uart1,
+    // Uart1RxBreakErr -> PlicPeripheral::Uart1
+    PlicPeripheral::Uart1,
+    // Uart1RxTimeout -> PlicPeripheral::Uart1
+    PlicPeripheral::Uart1,
+    // Uart1RxParityErr -> PlicPeripheral::Uart1
+    PlicPeripheral::Uart1,
+    // Uart1TxEmpty -> PlicPeripheral::Uart1
+    PlicPeripheral::Uart1,
+    // Uart2TxWatermark -> PlicPeripheral::Uart2
+    PlicPeripheral::Uart2,
+    // Uart2RxWatermark -> PlicPeripheral::Uart2
+    PlicPeripheral::Uart2,
+    // Uart2TxDone -> PlicPeripheral::Uart2
+    PlicPeripheral::Uart2,
+    // Uart2RxOverflow -> PlicPeripheral::Uart2
+    PlicPeripheral::Uart2,
+    // Uart2RxFrameErr -> PlicPeripheral::Uart2
+    PlicPeripheral::Uart2,
+    // Uart2RxBreakErr -> PlicPeripheral::Uart2
+    PlicPeripheral::Uart2,
+    // Uart2RxTimeout -> PlicPeripheral::Uart2
+    PlicPeripheral::Uart2,
+    // Uart2RxParityErr -> PlicPeripheral::Uart2
+    PlicPeripheral::Uart2,
+    // Uart2TxEmpty -> PlicPeripheral::Uart2
+    PlicPeripheral::Uart2,
+    // Uart3TxWatermark -> PlicPeripheral::Uart3
+    PlicPeripheral::Uart3,
+    // Uart3RxWatermark -> PlicPeripheral::Uart3
+    PlicPeripheral::Uart3,
+    // Uart3TxDone -> PlicPeripheral::Uart3
+    PlicPeripheral::Uart3,
+    // Uart3RxOverflow -> PlicPeripheral::Uart3
+    PlicPeripheral::Uart3,
+    // Uart3RxFrameErr -> PlicPeripheral::Uart3
+    PlicPeripheral::Uart3,
+    // Uart3RxBreakErr -> PlicPeripheral::Uart3
+    PlicPeripheral::Uart3,
+    // Uart3RxTimeout -> PlicPeripheral::Uart3
+    PlicPeripheral::Uart3,
+    // Uart3RxParityErr -> PlicPeripheral::Uart3
+    PlicPeripheral::Uart3,
+    // Uart3TxEmpty -> PlicPeripheral::Uart3
+    PlicPeripheral::Uart3,
+    // GpioGpio0 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio1 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio2 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio3 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio4 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio5 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio6 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio7 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio8 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio9 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio10 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio11 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio12 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio13 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio14 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio15 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio16 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio17 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio18 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio19 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio20 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio21 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio22 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio23 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio24 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio25 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio26 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio27 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio28 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio29 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio30 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // GpioGpio31 -> PlicPeripheral::Gpio
+    PlicPeripheral::Gpio,
+    // SpiDeviceUploadCmdfifoNotEmpty -> PlicPeripheral::SpiDevice
+    PlicPeripheral::SpiDevice,
+    // SpiDeviceUploadPayloadNotEmpty -> PlicPeripheral::SpiDevice
+    PlicPeripheral::SpiDevice,
+    // SpiDeviceUploadPayloadOverflow -> PlicPeripheral::SpiDevice
+    PlicPeripheral::SpiDevice,
+    // SpiDeviceReadbufWatermark -> PlicPeripheral::SpiDevice
+    PlicPeripheral::SpiDevice,
+    // SpiDeviceReadbufFlip -> PlicPeripheral::SpiDevice
+    PlicPeripheral::SpiDevice,
+    // SpiDeviceTpmHeaderNotEmpty -> PlicPeripheral::SpiDevice
+    PlicPeripheral::SpiDevice,
+    // SpiDeviceTpmRdfifoCmdEnd -> PlicPeripheral::SpiDevice
+    PlicPeripheral::SpiDevice,
+    // SpiDeviceTpmRdfifoDrop -> PlicPeripheral::SpiDevice
+    PlicPeripheral::SpiDevice,
+    // I2c0FmtThreshold -> PlicPeripheral::I2c0
+    PlicPeripheral::I2c0,
+    // I2c0RxThreshold -> PlicPeripheral::I2c0
+    PlicPeripheral::I2c0,
+    // I2c0AcqThreshold -> PlicPeripheral::I2c0
+    PlicPeripheral::I2c0,
+    // I2c0RxOverflow -> PlicPeripheral::I2c0
+    PlicPeripheral::I2c0,
+    // I2c0ControllerHalt -> PlicPeripheral::I2c0
+    PlicPeripheral::I2c0,
+    // I2c0SclInterference -> PlicPeripheral::I2c0
+    PlicPeripheral::I2c0,
+    // I2c0SdaInterference -> PlicPeripheral::I2c0
+    PlicPeripheral::I2c0,
+    // I2c0StretchTimeout -> PlicPeripheral::I2c0
+    PlicPeripheral::I2c0,
+    // I2c0SdaUnstable -> PlicPeripheral::I2c0
+    PlicPeripheral::I2c0,
+    // I2c0CmdComplete -> PlicPeripheral::I2c0
+    PlicPeripheral::I2c0,
+    // I2c0TxStretch -> PlicPeripheral::I2c0
+    PlicPeripheral::I2c0,
+    // I2c0TxThreshold -> PlicPeripheral::I2c0
+    PlicPeripheral::I2c0,
+    // I2c0AcqStretch -> PlicPeripheral::I2c0
+    PlicPeripheral::I2c0,
+    // I2c0UnexpStop -> PlicPeripheral::I2c0
+    PlicPeripheral::I2c0,
+    // I2c0HostTimeout -> PlicPeripheral::I2c0
+    PlicPeripheral::I2c0,
+    // I2c1FmtThreshold -> PlicPeripheral::I2c1
+    PlicPeripheral::I2c1,
+    // I2c1RxThreshold -> PlicPeripheral::I2c1
+    PlicPeripheral::I2c1,
+    // I2c1AcqThreshold -> PlicPeripheral::I2c1
+    PlicPeripheral::I2c1,
+    // I2c1RxOverflow -> PlicPeripheral::I2c1
+    PlicPeripheral::I2c1,
+    // I2c1ControllerHalt -> PlicPeripheral::I2c1
+    PlicPeripheral::I2c1,
+    // I2c1SclInterference -> PlicPeripheral::I2c1
+    PlicPeripheral::I2c1,
+    // I2c1SdaInterference -> PlicPeripheral::I2c1
+    PlicPeripheral::I2c1,
+    // I2c1StretchTimeout -> PlicPeripheral::I2c1
+    PlicPeripheral::I2c1,
+    // I2c1SdaUnstable -> PlicPeripheral::I2c1
+    PlicPeripheral::I2c1,
+    // I2c1CmdComplete -> PlicPeripheral::I2c1
+    PlicPeripheral::I2c1,
+    // I2c1TxStretch -> PlicPeripheral::I2c1
+    PlicPeripheral::I2c1,
+    // I2c1TxThreshold -> PlicPeripheral::I2c1
+    PlicPeripheral::I2c1,
+    // I2c1AcqStretch -> PlicPeripheral::I2c1
+    PlicPeripheral::I2c1,
+    // I2c1UnexpStop -> PlicPeripheral::I2c1
+    PlicPeripheral::I2c1,
+    // I2c1HostTimeout -> PlicPeripheral::I2c1
+    PlicPeripheral::I2c1,
+    // I2c2FmtThreshold -> PlicPeripheral::I2c2
+    PlicPeripheral::I2c2,
+    // I2c2RxThreshold -> PlicPeripheral::I2c2
+    PlicPeripheral::I2c2,
+    // I2c2AcqThreshold -> PlicPeripheral::I2c2
+    PlicPeripheral::I2c2,
+    // I2c2RxOverflow -> PlicPeripheral::I2c2
+    PlicPeripheral::I2c2,
+    // I2c2ControllerHalt -> PlicPeripheral::I2c2
+    PlicPeripheral::I2c2,
+    // I2c2SclInterference -> PlicPeripheral::I2c2
+    PlicPeripheral::I2c2,
+    // I2c2SdaInterference -> PlicPeripheral::I2c2
+    PlicPeripheral::I2c2,
+    // I2c2StretchTimeout -> PlicPeripheral::I2c2
+    PlicPeripheral::I2c2,
+    // I2c2SdaUnstable -> PlicPeripheral::I2c2
+    PlicPeripheral::I2c2,
+    // I2c2CmdComplete -> PlicPeripheral::I2c2
+    PlicPeripheral::I2c2,
+    // I2c2TxStretch -> PlicPeripheral::I2c2
+    PlicPeripheral::I2c2,
+    // I2c2TxThreshold -> PlicPeripheral::I2c2
+    PlicPeripheral::I2c2,
+    // I2c2AcqStretch -> PlicPeripheral::I2c2
+    PlicPeripheral::I2c2,
+    // I2c2UnexpStop -> PlicPeripheral::I2c2
+    PlicPeripheral::I2c2,
+    // I2c2HostTimeout -> PlicPeripheral::I2c2
+    PlicPeripheral::I2c2,
+    // PattgenDoneCh0 -> PlicPeripheral::Pattgen
+    PlicPeripheral::Pattgen,
+    // PattgenDoneCh1 -> PlicPeripheral::Pattgen
+    PlicPeripheral::Pattgen,
+    // RvTimerTimerExpiredHart0Timer0 -> PlicPeripheral::RvTimer
+    PlicPeripheral::RvTimer,
+    // OtpCtrlOtpOperationDone -> PlicPeripheral::OtpCtrl
+    PlicPeripheral::OtpCtrl,
+    // OtpCtrlOtpError -> PlicPeripheral::OtpCtrl
+    PlicPeripheral::OtpCtrl,
+    // AlertHandlerClassa -> PlicPeripheral::AlertHandler
+    PlicPeripheral::AlertHandler,
+    // AlertHandlerClassb -> PlicPeripheral::AlertHandler
+    PlicPeripheral::AlertHandler,
+    // AlertHandlerClassc -> PlicPeripheral::AlertHandler
+    PlicPeripheral::AlertHandler,
+    // AlertHandlerClassd -> PlicPeripheral::AlertHandler
+    PlicPeripheral::AlertHandler,
+    // SpiHost0Error -> PlicPeripheral::SpiHost0
+    PlicPeripheral::SpiHost0,
+    // SpiHost0SpiEvent -> PlicPeripheral::SpiHost0
+    PlicPeripheral::SpiHost0,
+    // SpiHost1Error -> PlicPeripheral::SpiHost1
+    PlicPeripheral::SpiHost1,
+    // SpiHost1SpiEvent -> PlicPeripheral::SpiHost1
+    PlicPeripheral::SpiHost1,
+    // UsbdevPktReceived -> PlicPeripheral::Usbdev
+    PlicPeripheral::Usbdev,
+    // UsbdevPktSent -> PlicPeripheral::Usbdev
+    PlicPeripheral::Usbdev,
+    // UsbdevDisconnected -> PlicPeripheral::Usbdev
+    PlicPeripheral::Usbdev,
+    // UsbdevHostLost -> PlicPeripheral::Usbdev
+    PlicPeripheral::Usbdev,
+    // UsbdevLinkReset -> PlicPeripheral::Usbdev
+    PlicPeripheral::Usbdev,
+    // UsbdevLinkSuspend -> PlicPeripheral::Usbdev
+    PlicPeripheral::Usbdev,
+    // UsbdevLinkResume -> PlicPeripheral::Usbdev
+    PlicPeripheral::Usbdev,
+    // UsbdevAvOutEmpty -> PlicPeripheral::Usbdev
+    PlicPeripheral::Usbdev,
+    // UsbdevRxFull -> PlicPeripheral::Usbdev
+    PlicPeripheral::Usbdev,
+    // UsbdevAvOverflow -> PlicPeripheral::Usbdev
+    PlicPeripheral::Usbdev,
+    // UsbdevLinkInErr -> PlicPeripheral::Usbdev
+    PlicPeripheral::Usbdev,
+    // UsbdevRxCrcErr -> PlicPeripheral::Usbdev
+    PlicPeripheral::Usbdev,
+    // UsbdevRxPidErr -> PlicPeripheral::Usbdev
+    PlicPeripheral::Usbdev,
+    // UsbdevRxBitstuffErr -> PlicPeripheral::Usbdev
+    PlicPeripheral::Usbdev,
+    // UsbdevFrame -> PlicPeripheral::Usbdev
+    PlicPeripheral::Usbdev,
+    // UsbdevPowered -> PlicPeripheral::Usbdev
+    PlicPeripheral::Usbdev,
+    // UsbdevLinkOutErr -> PlicPeripheral::Usbdev
+    PlicPeripheral::Usbdev,
+    // UsbdevAvSetupEmpty -> PlicPeripheral::Usbdev
+    PlicPeripheral::Usbdev,
+    // PwrmgrAonWakeup -> PlicPeripheral::PwrmgrAon
+    PlicPeripheral::PwrmgrAon,
+    // SysrstCtrlAonEventDetected -> PlicPeripheral::SysrstCtrlAon
+    PlicPeripheral::SysrstCtrlAon,
+    // AdcCtrlAonMatchPending -> PlicPeripheral::AdcCtrlAon
+    PlicPeripheral::AdcCtrlAon,
+    // AonTimerAonWkupTimerExpired -> PlicPeripheral::AonTimerAon
+    PlicPeripheral::AonTimerAon,
+    // AonTimerAonWdogTimerBark -> PlicPeripheral::AonTimerAon
+    PlicPeripheral::AonTimerAon,
+    // SensorCtrlAonIoStatusChange -> PlicPeripheral::SensorCtrlAon
+    PlicPeripheral::SensorCtrlAon,
+    // SensorCtrlAonInitStatusChange -> PlicPeripheral::SensorCtrlAon
+    PlicPeripheral::SensorCtrlAon,
+    // FlashCtrlProgEmpty -> PlicPeripheral::FlashCtrl
+    PlicPeripheral::FlashCtrl,
+    // FlashCtrlProgLvl -> PlicPeripheral::FlashCtrl
+    PlicPeripheral::FlashCtrl,
+    // FlashCtrlRdFull -> PlicPeripheral::FlashCtrl
+    PlicPeripheral::FlashCtrl,
+    // FlashCtrlRdLvl -> PlicPeripheral::FlashCtrl
+    PlicPeripheral::FlashCtrl,
+    // FlashCtrlOpDone -> PlicPeripheral::FlashCtrl
+    PlicPeripheral::FlashCtrl,
+    // FlashCtrlCorrErr -> PlicPeripheral::FlashCtrl
+    PlicPeripheral::FlashCtrl,
+    // HmacHmacDone -> PlicPeripheral::Hmac
+    PlicPeripheral::Hmac,
+    // HmacFifoEmpty -> PlicPeripheral::Hmac
+    PlicPeripheral::Hmac,
+    // HmacHmacErr -> PlicPeripheral::Hmac
+    PlicPeripheral::Hmac,
+    // KmacKmacDone -> PlicPeripheral::Kmac
+    PlicPeripheral::Kmac,
+    // KmacFifoEmpty -> PlicPeripheral::Kmac
+    PlicPeripheral::Kmac,
+    // KmacKmacErr -> PlicPeripheral::Kmac
+    PlicPeripheral::Kmac,
+    // OtbnDone -> PlicPeripheral::Otbn
+    PlicPeripheral::Otbn,
+    // KeymgrOpDone -> PlicPeripheral::Keymgr
+    PlicPeripheral::Keymgr,
+    // CsrngCsCmdReqDone -> PlicPeripheral::Csrng
+    PlicPeripheral::Csrng,
+    // CsrngCsEntropyReq -> PlicPeripheral::Csrng
+    PlicPeripheral::Csrng,
+    // CsrngCsHwInstExc -> PlicPeripheral::Csrng
+    PlicPeripheral::Csrng,
+    // CsrngCsFatalErr -> PlicPeripheral::Csrng
+    PlicPeripheral::Csrng,
+    // EntropySrcEsEntropyValid -> PlicPeripheral::EntropySrc
+    PlicPeripheral::EntropySrc,
+    // EntropySrcEsHealthTestFailed -> PlicPeripheral::EntropySrc
+    PlicPeripheral::EntropySrc,
+    // EntropySrcEsObserveFifoReady -> PlicPeripheral::EntropySrc
+    PlicPeripheral::EntropySrc,
+    // EntropySrcEsFatalErr -> PlicPeripheral::EntropySrc
+    PlicPeripheral::EntropySrc,
+    // Edn0EdnCmdReqDone -> PlicPeripheral::Edn0
+    PlicPeripheral::Edn0,
+    // Edn0EdnFatalErr -> PlicPeripheral::Edn0
+    PlicPeripheral::Edn0,
+    // Edn1EdnCmdReqDone -> PlicPeripheral::Edn1
+    PlicPeripheral::Edn1,
+    // Edn1EdnFatalErr -> PlicPeripheral::Edn1
+    PlicPeripheral::Edn1,
+];
+
+/// Alert Handler Alert Source to Peripheral Map
+///
+/// This array is a mapping from `AlertId` to
+/// `AlertPeripheral`.
+pub const ALERT_FOR_PERIPHERAL: [AlertPeripheral; 65] = [
+    // Uart0FatalFault -> AlertPeripheral::Uart0
+    AlertPeripheral::Uart0,
+    // Uart1FatalFault -> AlertPeripheral::Uart1
+    AlertPeripheral::Uart1,
+    // Uart2FatalFault -> AlertPeripheral::Uart2
+    AlertPeripheral::Uart2,
+    // Uart3FatalFault -> AlertPeripheral::Uart3
+    AlertPeripheral::Uart3,
+    // GpioFatalFault -> AlertPeripheral::Gpio
+    AlertPeripheral::Gpio,
+    // SpiDeviceFatalFault -> AlertPeripheral::SpiDevice
+    AlertPeripheral::SpiDevice,
+    // I2c0FatalFault -> AlertPeripheral::I2c0
+    AlertPeripheral::I2c0,
+    // I2c1FatalFault -> AlertPeripheral::I2c1
+    AlertPeripheral::I2c1,
+    // I2c2FatalFault -> AlertPeripheral::I2c2
+    AlertPeripheral::I2c2,
+    // PattgenFatalFault -> AlertPeripheral::Pattgen
+    AlertPeripheral::Pattgen,
+    // RvTimerFatalFault -> AlertPeripheral::RvTimer
+    AlertPeripheral::RvTimer,
+    // OtpCtrlFatalMacroError -> AlertPeripheral::OtpCtrl
+    AlertPeripheral::OtpCtrl,
+    // OtpCtrlFatalCheckError -> AlertPeripheral::OtpCtrl
+    AlertPeripheral::OtpCtrl,
+    // OtpCtrlFatalBusIntegError -> AlertPeripheral::OtpCtrl
+    AlertPeripheral::OtpCtrl,
+    // OtpCtrlFatalPrimOtpAlert -> AlertPeripheral::OtpCtrl
+    AlertPeripheral::OtpCtrl,
+    // OtpCtrlRecovPrimOtpAlert -> AlertPeripheral::OtpCtrl
+    AlertPeripheral::OtpCtrl,
+    // LcCtrlFatalProgError -> AlertPeripheral::LcCtrl
+    AlertPeripheral::LcCtrl,
+    // LcCtrlFatalStateError -> AlertPeripheral::LcCtrl
+    AlertPeripheral::LcCtrl,
+    // LcCtrlFatalBusIntegError -> AlertPeripheral::LcCtrl
+    AlertPeripheral::LcCtrl,
+    // SpiHost0FatalFault -> AlertPeripheral::SpiHost0
+    AlertPeripheral::SpiHost0,
+    // SpiHost1FatalFault -> AlertPeripheral::SpiHost1
+    AlertPeripheral::SpiHost1,
+    // UsbdevFatalFault -> AlertPeripheral::Usbdev
+    AlertPeripheral::Usbdev,
+    // PwrmgrAonFatalFault -> AlertPeripheral::PwrmgrAon
+    AlertPeripheral::PwrmgrAon,
+    // RstmgrAonFatalFault -> AlertPeripheral::RstmgrAon
+    AlertPeripheral::RstmgrAon,
+    // RstmgrAonFatalCnstyFault -> AlertPeripheral::RstmgrAon
+    AlertPeripheral::RstmgrAon,
+    // ClkmgrAonRecovFault -> AlertPeripheral::ClkmgrAon
+    AlertPeripheral::ClkmgrAon,
+    // ClkmgrAonFatalFault -> AlertPeripheral::ClkmgrAon
+    AlertPeripheral::ClkmgrAon,
+    // SysrstCtrlAonFatalFault -> AlertPeripheral::SysrstCtrlAon
+    AlertPeripheral::SysrstCtrlAon,
+    // AdcCtrlAonFatalFault -> AlertPeripheral::AdcCtrlAon
+    AlertPeripheral::AdcCtrlAon,
+    // PwmAonFatalFault -> AlertPeripheral::PwmAon
+    AlertPeripheral::PwmAon,
+    // PinmuxAonFatalFault -> AlertPeripheral::PinmuxAon
+    AlertPeripheral::PinmuxAon,
+    // AonTimerAonFatalFault -> AlertPeripheral::AonTimerAon
+    AlertPeripheral::AonTimerAon,
+    // SensorCtrlAonRecovAlert -> AlertPeripheral::SensorCtrlAon
+    AlertPeripheral::SensorCtrlAon,
+    // SensorCtrlAonFatalAlert -> AlertPeripheral::SensorCtrlAon
+    AlertPeripheral::SensorCtrlAon,
+    // SramCtrlRetAonFatalError -> AlertPeripheral::SramCtrlRetAon
+    AlertPeripheral::SramCtrlRetAon,
+    // FlashCtrlRecovErr -> AlertPeripheral::FlashCtrl
+    AlertPeripheral::FlashCtrl,
+    // FlashCtrlFatalStdErr -> AlertPeripheral::FlashCtrl
+    AlertPeripheral::FlashCtrl,
+    // FlashCtrlFatalErr -> AlertPeripheral::FlashCtrl
+    AlertPeripheral::FlashCtrl,
+    // FlashCtrlFatalPrimFlashAlert -> AlertPeripheral::FlashCtrl
+    AlertPeripheral::FlashCtrl,
+    // FlashCtrlRecovPrimFlashAlert -> AlertPeripheral::FlashCtrl
+    AlertPeripheral::FlashCtrl,
+    // RvDmFatalFault -> AlertPeripheral::RvDm
+    AlertPeripheral::RvDm,
+    // RvPlicFatalFault -> AlertPeripheral::RvPlic
+    AlertPeripheral::RvPlic,
+    // AesRecovCtrlUpdateErr -> AlertPeripheral::Aes
+    AlertPeripheral::Aes,
+    // AesFatalFault -> AlertPeripheral::Aes
+    AlertPeripheral::Aes,
+    // HmacFatalFault -> AlertPeripheral::Hmac
+    AlertPeripheral::Hmac,
+    // KmacRecovOperationErr -> AlertPeripheral::Kmac
+    AlertPeripheral::Kmac,
+    // KmacFatalFaultErr -> AlertPeripheral::Kmac
+    AlertPeripheral::Kmac,
+    // OtbnFatal -> AlertPeripheral::Otbn
+    AlertPeripheral::Otbn,
+    // OtbnRecov -> AlertPeripheral::Otbn
+    AlertPeripheral::Otbn,
+    // KeymgrRecovOperationErr -> AlertPeripheral::Keymgr
+    AlertPeripheral::Keymgr,
+    // KeymgrFatalFaultErr -> AlertPeripheral::Keymgr
+    AlertPeripheral::Keymgr,
+    // CsrngRecovAlert -> AlertPeripheral::Csrng
+    AlertPeripheral::Csrng,
+    // CsrngFatalAlert -> AlertPeripheral::Csrng
+    AlertPeripheral::Csrng,
+    // EntropySrcRecovAlert -> AlertPeripheral::EntropySrc
+    AlertPeripheral::EntropySrc,
+    // EntropySrcFatalAlert -> AlertPeripheral::EntropySrc
+    AlertPeripheral::EntropySrc,
+    // Edn0RecovAlert -> AlertPeripheral::Edn0
+    AlertPeripheral::Edn0,
+    // Edn0FatalAlert -> AlertPeripheral::Edn0
+    AlertPeripheral::Edn0,
+    // Edn1RecovAlert -> AlertPeripheral::Edn1
+    AlertPeripheral::Edn1,
+    // Edn1FatalAlert -> AlertPeripheral::Edn1
+    AlertPeripheral::Edn1,
+    // SramCtrlMainFatalError -> AlertPeripheral::SramCtrlMain
+    AlertPeripheral::SramCtrlMain,
+    // RomCtrlFatal -> AlertPeripheral::RomCtrl
+    AlertPeripheral::RomCtrl,
+    // RvCoreIbexFatalSwErr -> AlertPeripheral::RvCoreIbex
+    AlertPeripheral::RvCoreIbex,
+    // RvCoreIbexRecovSwErr -> AlertPeripheral::RvCoreIbex
+    AlertPeripheral::RvCoreIbex,
+    // RvCoreIbexFatalHwErr -> AlertPeripheral::RvCoreIbex
+    AlertPeripheral::RvCoreIbex,
+    // RvCoreIbexRecovHwErr -> AlertPeripheral::RvCoreIbex
+    AlertPeripheral::RvCoreIbex,
+];
+
+// PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1}
+//  0 and 1 are tied to value 0 and 1
+pub const NUM_MIO_PADS: usize = 47;
+pub const NUM_DIO_PADS: usize = 16;
+
+pub const PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET: usize = 2;
+pub const PINMUX_PERIPH_OUTSEL_IDX_OFFSET: usize = 3;
+
+/// Pinmux Peripheral Input.
+#[derive(Copy, Clone, PartialEq, Eq)]
+#[repr(u32)]
+pub enum PinmuxPeripheralIn {
+    /// Peripheral Input 0
+    GpioGpio0 = 0,
+    /// Peripheral Input 1
+    GpioGpio1 = 1,
+    /// Peripheral Input 2
+    GpioGpio2 = 2,
+    /// Peripheral Input 3
+    GpioGpio3 = 3,
+    /// Peripheral Input 4
+    GpioGpio4 = 4,
+    /// Peripheral Input 5
+    GpioGpio5 = 5,
+    /// Peripheral Input 6
+    GpioGpio6 = 6,
+    /// Peripheral Input 7
+    GpioGpio7 = 7,
+    /// Peripheral Input 8
+    GpioGpio8 = 8,
+    /// Peripheral Input 9
+    GpioGpio9 = 9,
+    /// Peripheral Input 10
+    GpioGpio10 = 10,
+    /// Peripheral Input 11
+    GpioGpio11 = 11,
+    /// Peripheral Input 12
+    GpioGpio12 = 12,
+    /// Peripheral Input 13
+    GpioGpio13 = 13,
+    /// Peripheral Input 14
+    GpioGpio14 = 14,
+    /// Peripheral Input 15
+    GpioGpio15 = 15,
+    /// Peripheral Input 16
+    GpioGpio16 = 16,
+    /// Peripheral Input 17
+    GpioGpio17 = 17,
+    /// Peripheral Input 18
+    GpioGpio18 = 18,
+    /// Peripheral Input 19
+    GpioGpio19 = 19,
+    /// Peripheral Input 20
+    GpioGpio20 = 20,
+    /// Peripheral Input 21
+    GpioGpio21 = 21,
+    /// Peripheral Input 22
+    GpioGpio22 = 22,
+    /// Peripheral Input 23
+    GpioGpio23 = 23,
+    /// Peripheral Input 24
+    GpioGpio24 = 24,
+    /// Peripheral Input 25
+    GpioGpio25 = 25,
+    /// Peripheral Input 26
+    GpioGpio26 = 26,
+    /// Peripheral Input 27
+    GpioGpio27 = 27,
+    /// Peripheral Input 28
+    GpioGpio28 = 28,
+    /// Peripheral Input 29
+    GpioGpio29 = 29,
+    /// Peripheral Input 30
+    GpioGpio30 = 30,
+    /// Peripheral Input 31
+    GpioGpio31 = 31,
+    /// Peripheral Input 32
+    I2c0Sda = 32,
+    /// Peripheral Input 33
+    I2c0Scl = 33,
+    /// Peripheral Input 34
+    I2c1Sda = 34,
+    /// Peripheral Input 35
+    I2c1Scl = 35,
+    /// Peripheral Input 36
+    I2c2Sda = 36,
+    /// Peripheral Input 37
+    I2c2Scl = 37,
+    /// Peripheral Input 38
+    SpiHost1Sd0 = 38,
+    /// Peripheral Input 39
+    SpiHost1Sd1 = 39,
+    /// Peripheral Input 40
+    SpiHost1Sd2 = 40,
+    /// Peripheral Input 41
+    SpiHost1Sd3 = 41,
+    /// Peripheral Input 42
+    Uart0Rx = 42,
+    /// Peripheral Input 43
+    Uart1Rx = 43,
+    /// Peripheral Input 44
+    Uart2Rx = 44,
+    /// Peripheral Input 45
+    Uart3Rx = 45,
+    /// Peripheral Input 46
+    SpiDeviceTpmCsb = 46,
+    /// Peripheral Input 47
+    FlashCtrlTck = 47,
+    /// Peripheral Input 48
+    FlashCtrlTms = 48,
+    /// Peripheral Input 49
+    FlashCtrlTdi = 49,
+    /// Peripheral Input 50
+    SysrstCtrlAonAcPresent = 50,
+    /// Peripheral Input 51
+    SysrstCtrlAonKey0In = 51,
+    /// Peripheral Input 52
+    SysrstCtrlAonKey1In = 52,
+    /// Peripheral Input 53
+    SysrstCtrlAonKey2In = 53,
+    /// Peripheral Input 54
+    SysrstCtrlAonPwrbIn = 54,
+    /// Peripheral Input 55
+    SysrstCtrlAonLidOpen = 55,
+    /// Peripheral Input 56
+    UsbdevSense = 56,
+}
+
+impl TryFrom<u32> for PinmuxPeripheralIn {
+    type Error = u32;
+    fn try_from(val: u32) -> Result<Self, Self::Error> {
+        match val {
+            0 => Ok(Self::GpioGpio0),
+            1 => Ok(Self::GpioGpio1),
+            2 => Ok(Self::GpioGpio2),
+            3 => Ok(Self::GpioGpio3),
+            4 => Ok(Self::GpioGpio4),
+            5 => Ok(Self::GpioGpio5),
+            6 => Ok(Self::GpioGpio6),
+            7 => Ok(Self::GpioGpio7),
+            8 => Ok(Self::GpioGpio8),
+            9 => Ok(Self::GpioGpio9),
+            10 => Ok(Self::GpioGpio10),
+            11 => Ok(Self::GpioGpio11),
+            12 => Ok(Self::GpioGpio12),
+            13 => Ok(Self::GpioGpio13),
+            14 => Ok(Self::GpioGpio14),
+            15 => Ok(Self::GpioGpio15),
+            16 => Ok(Self::GpioGpio16),
+            17 => Ok(Self::GpioGpio17),
+            18 => Ok(Self::GpioGpio18),
+            19 => Ok(Self::GpioGpio19),
+            20 => Ok(Self::GpioGpio20),
+            21 => Ok(Self::GpioGpio21),
+            22 => Ok(Self::GpioGpio22),
+            23 => Ok(Self::GpioGpio23),
+            24 => Ok(Self::GpioGpio24),
+            25 => Ok(Self::GpioGpio25),
+            26 => Ok(Self::GpioGpio26),
+            27 => Ok(Self::GpioGpio27),
+            28 => Ok(Self::GpioGpio28),
+            29 => Ok(Self::GpioGpio29),
+            30 => Ok(Self::GpioGpio30),
+            31 => Ok(Self::GpioGpio31),
+            32 => Ok(Self::I2c0Sda),
+            33 => Ok(Self::I2c0Scl),
+            34 => Ok(Self::I2c1Sda),
+            35 => Ok(Self::I2c1Scl),
+            36 => Ok(Self::I2c2Sda),
+            37 => Ok(Self::I2c2Scl),
+            38 => Ok(Self::SpiHost1Sd0),
+            39 => Ok(Self::SpiHost1Sd1),
+            40 => Ok(Self::SpiHost1Sd2),
+            41 => Ok(Self::SpiHost1Sd3),
+            42 => Ok(Self::Uart0Rx),
+            43 => Ok(Self::Uart1Rx),
+            44 => Ok(Self::Uart2Rx),
+            45 => Ok(Self::Uart3Rx),
+            46 => Ok(Self::SpiDeviceTpmCsb),
+            47 => Ok(Self::FlashCtrlTck),
+            48 => Ok(Self::FlashCtrlTms),
+            49 => Ok(Self::FlashCtrlTdi),
+            50 => Ok(Self::SysrstCtrlAonAcPresent),
+            51 => Ok(Self::SysrstCtrlAonKey0In),
+            52 => Ok(Self::SysrstCtrlAonKey1In),
+            53 => Ok(Self::SysrstCtrlAonKey2In),
+            54 => Ok(Self::SysrstCtrlAonPwrbIn),
+            55 => Ok(Self::SysrstCtrlAonLidOpen),
+            56 => Ok(Self::UsbdevSense),
+            _ => Err(val),
+        }
+    }
+}
+
+/// Pinmux MIO Input Selector.
+#[derive(Copy, Clone, PartialEq, Eq)]
+#[repr(u32)]
+pub enum PinmuxInsel {
+    /// Tie constantly to zero
+    ConstantZero = 0,
+    /// Tie constantly to one
+    ConstantOne = 1,
+    /// MIO Pad 0
+    Ioa0 = 2,
+    /// MIO Pad 1
+    Ioa1 = 3,
+    /// MIO Pad 2
+    Ioa2 = 4,
+    /// MIO Pad 3
+    Ioa3 = 5,
+    /// MIO Pad 4
+    Ioa4 = 6,
+    /// MIO Pad 5
+    Ioa5 = 7,
+    /// MIO Pad 6
+    Ioa6 = 8,
+    /// MIO Pad 7
+    Ioa7 = 9,
+    /// MIO Pad 8
+    Ioa8 = 10,
+    /// MIO Pad 9
+    Iob0 = 11,
+    /// MIO Pad 10
+    Iob1 = 12,
+    /// MIO Pad 11
+    Iob2 = 13,
+    /// MIO Pad 12
+    Iob3 = 14,
+    /// MIO Pad 13
+    Iob4 = 15,
+    /// MIO Pad 14
+    Iob5 = 16,
+    /// MIO Pad 15
+    Iob6 = 17,
+    /// MIO Pad 16
+    Iob7 = 18,
+    /// MIO Pad 17
+    Iob8 = 19,
+    /// MIO Pad 18
+    Iob9 = 20,
+    /// MIO Pad 19
+    Iob10 = 21,
+    /// MIO Pad 20
+    Iob11 = 22,
+    /// MIO Pad 21
+    Iob12 = 23,
+    /// MIO Pad 22
+    Ioc0 = 24,
+    /// MIO Pad 23
+    Ioc1 = 25,
+    /// MIO Pad 24
+    Ioc2 = 26,
+    /// MIO Pad 25
+    Ioc3 = 27,
+    /// MIO Pad 26
+    Ioc4 = 28,
+    /// MIO Pad 27
+    Ioc5 = 29,
+    /// MIO Pad 28
+    Ioc6 = 30,
+    /// MIO Pad 29
+    Ioc7 = 31,
+    /// MIO Pad 30
+    Ioc8 = 32,
+    /// MIO Pad 31
+    Ioc9 = 33,
+    /// MIO Pad 32
+    Ioc10 = 34,
+    /// MIO Pad 33
+    Ioc11 = 35,
+    /// MIO Pad 34
+    Ioc12 = 36,
+    /// MIO Pad 35
+    Ior0 = 37,
+    /// MIO Pad 36
+    Ior1 = 38,
+    /// MIO Pad 37
+    Ior2 = 39,
+    /// MIO Pad 38
+    Ior3 = 40,
+    /// MIO Pad 39
+    Ior4 = 41,
+    /// MIO Pad 40
+    Ior5 = 42,
+    /// MIO Pad 41
+    Ior6 = 43,
+    /// MIO Pad 42
+    Ior7 = 44,
+    /// MIO Pad 43
+    Ior10 = 45,
+    /// MIO Pad 44
+    Ior11 = 46,
+    /// MIO Pad 45
+    Ior12 = 47,
+    /// MIO Pad 46
+    Ior13 = 48,
+}
+
+impl TryFrom<u32> for PinmuxInsel {
+    type Error = u32;
+    fn try_from(val: u32) -> Result<Self, Self::Error> {
+        match val {
+            0 => Ok(Self::ConstantZero),
+            1 => Ok(Self::ConstantOne),
+            2 => Ok(Self::Ioa0),
+            3 => Ok(Self::Ioa1),
+            4 => Ok(Self::Ioa2),
+            5 => Ok(Self::Ioa3),
+            6 => Ok(Self::Ioa4),
+            7 => Ok(Self::Ioa5),
+            8 => Ok(Self::Ioa6),
+            9 => Ok(Self::Ioa7),
+            10 => Ok(Self::Ioa8),
+            11 => Ok(Self::Iob0),
+            12 => Ok(Self::Iob1),
+            13 => Ok(Self::Iob2),
+            14 => Ok(Self::Iob3),
+            15 => Ok(Self::Iob4),
+            16 => Ok(Self::Iob5),
+            17 => Ok(Self::Iob6),
+            18 => Ok(Self::Iob7),
+            19 => Ok(Self::Iob8),
+            20 => Ok(Self::Iob9),
+            21 => Ok(Self::Iob10),
+            22 => Ok(Self::Iob11),
+            23 => Ok(Self::Iob12),
+            24 => Ok(Self::Ioc0),
+            25 => Ok(Self::Ioc1),
+            26 => Ok(Self::Ioc2),
+            27 => Ok(Self::Ioc3),
+            28 => Ok(Self::Ioc4),
+            29 => Ok(Self::Ioc5),
+            30 => Ok(Self::Ioc6),
+            31 => Ok(Self::Ioc7),
+            32 => Ok(Self::Ioc8),
+            33 => Ok(Self::Ioc9),
+            34 => Ok(Self::Ioc10),
+            35 => Ok(Self::Ioc11),
+            36 => Ok(Self::Ioc12),
+            37 => Ok(Self::Ior0),
+            38 => Ok(Self::Ior1),
+            39 => Ok(Self::Ior2),
+            40 => Ok(Self::Ior3),
+            41 => Ok(Self::Ior4),
+            42 => Ok(Self::Ior5),
+            43 => Ok(Self::Ior6),
+            44 => Ok(Self::Ior7),
+            45 => Ok(Self::Ior10),
+            46 => Ok(Self::Ior11),
+            47 => Ok(Self::Ior12),
+            48 => Ok(Self::Ior13),
+            _ => Err(val),
+        }
+    }
+}
+
+/// Pinmux MIO Output.
+#[derive(Copy, Clone, PartialEq, Eq)]
+#[repr(u32)]
+pub enum PinmuxMioOut {
+    /// MIO Pad 0
+    Ioa0 = 0,
+    /// MIO Pad 1
+    Ioa1 = 1,
+    /// MIO Pad 2
+    Ioa2 = 2,
+    /// MIO Pad 3
+    Ioa3 = 3,
+    /// MIO Pad 4
+    Ioa4 = 4,
+    /// MIO Pad 5
+    Ioa5 = 5,
+    /// MIO Pad 6
+    Ioa6 = 6,
+    /// MIO Pad 7
+    Ioa7 = 7,
+    /// MIO Pad 8
+    Ioa8 = 8,
+    /// MIO Pad 9
+    Iob0 = 9,
+    /// MIO Pad 10
+    Iob1 = 10,
+    /// MIO Pad 11
+    Iob2 = 11,
+    /// MIO Pad 12
+    Iob3 = 12,
+    /// MIO Pad 13
+    Iob4 = 13,
+    /// MIO Pad 14
+    Iob5 = 14,
+    /// MIO Pad 15
+    Iob6 = 15,
+    /// MIO Pad 16
+    Iob7 = 16,
+    /// MIO Pad 17
+    Iob8 = 17,
+    /// MIO Pad 18
+    Iob9 = 18,
+    /// MIO Pad 19
+    Iob10 = 19,
+    /// MIO Pad 20
+    Iob11 = 20,
+    /// MIO Pad 21
+    Iob12 = 21,
+    /// MIO Pad 22
+    Ioc0 = 22,
+    /// MIO Pad 23
+    Ioc1 = 23,
+    /// MIO Pad 24
+    Ioc2 = 24,
+    /// MIO Pad 25
+    Ioc3 = 25,
+    /// MIO Pad 26
+    Ioc4 = 26,
+    /// MIO Pad 27
+    Ioc5 = 27,
+    /// MIO Pad 28
+    Ioc6 = 28,
+    /// MIO Pad 29
+    Ioc7 = 29,
+    /// MIO Pad 30
+    Ioc8 = 30,
+    /// MIO Pad 31
+    Ioc9 = 31,
+    /// MIO Pad 32
+    Ioc10 = 32,
+    /// MIO Pad 33
+    Ioc11 = 33,
+    /// MIO Pad 34
+    Ioc12 = 34,
+    /// MIO Pad 35
+    Ior0 = 35,
+    /// MIO Pad 36
+    Ior1 = 36,
+    /// MIO Pad 37
+    Ior2 = 37,
+    /// MIO Pad 38
+    Ior3 = 38,
+    /// MIO Pad 39
+    Ior4 = 39,
+    /// MIO Pad 40
+    Ior5 = 40,
+    /// MIO Pad 41
+    Ior6 = 41,
+    /// MIO Pad 42
+    Ior7 = 42,
+    /// MIO Pad 43
+    Ior10 = 43,
+    /// MIO Pad 44
+    Ior11 = 44,
+    /// MIO Pad 45
+    Ior12 = 45,
+    /// MIO Pad 46
+    Ior13 = 46,
+}
+
+impl TryFrom<u32> for PinmuxMioOut {
+    type Error = u32;
+    fn try_from(val: u32) -> Result<Self, Self::Error> {
+        match val {
+            0 => Ok(Self::Ioa0),
+            1 => Ok(Self::Ioa1),
+            2 => Ok(Self::Ioa2),
+            3 => Ok(Self::Ioa3),
+            4 => Ok(Self::Ioa4),
+            5 => Ok(Self::Ioa5),
+            6 => Ok(Self::Ioa6),
+            7 => Ok(Self::Ioa7),
+            8 => Ok(Self::Ioa8),
+            9 => Ok(Self::Iob0),
+            10 => Ok(Self::Iob1),
+            11 => Ok(Self::Iob2),
+            12 => Ok(Self::Iob3),
+            13 => Ok(Self::Iob4),
+            14 => Ok(Self::Iob5),
+            15 => Ok(Self::Iob6),
+            16 => Ok(Self::Iob7),
+            17 => Ok(Self::Iob8),
+            18 => Ok(Self::Iob9),
+            19 => Ok(Self::Iob10),
+            20 => Ok(Self::Iob11),
+            21 => Ok(Self::Iob12),
+            22 => Ok(Self::Ioc0),
+            23 => Ok(Self::Ioc1),
+            24 => Ok(Self::Ioc2),
+            25 => Ok(Self::Ioc3),
+            26 => Ok(Self::Ioc4),
+            27 => Ok(Self::Ioc5),
+            28 => Ok(Self::Ioc6),
+            29 => Ok(Self::Ioc7),
+            30 => Ok(Self::Ioc8),
+            31 => Ok(Self::Ioc9),
+            32 => Ok(Self::Ioc10),
+            33 => Ok(Self::Ioc11),
+            34 => Ok(Self::Ioc12),
+            35 => Ok(Self::Ior0),
+            36 => Ok(Self::Ior1),
+            37 => Ok(Self::Ior2),
+            38 => Ok(Self::Ior3),
+            39 => Ok(Self::Ior4),
+            40 => Ok(Self::Ior5),
+            41 => Ok(Self::Ior6),
+            42 => Ok(Self::Ior7),
+            43 => Ok(Self::Ior10),
+            44 => Ok(Self::Ior11),
+            45 => Ok(Self::Ior12),
+            46 => Ok(Self::Ior13),
+            _ => Err(val),
+        }
+    }
+}
+
+/// Pinmux Peripheral Output Selector.
+#[derive(Copy, Clone, PartialEq, Eq)]
+#[repr(u32)]
+pub enum PinmuxOutsel {
+    /// Tie constantly to zero
+    ConstantZero = 0,
+    /// Tie constantly to one
+    ConstantOne = 1,
+    /// Tie constantly to high-Z
+    ConstantHighZ = 2,
+    /// Peripheral Output 0
+    GpioGpio0 = 3,
+    /// Peripheral Output 1
+    GpioGpio1 = 4,
+    /// Peripheral Output 2
+    GpioGpio2 = 5,
+    /// Peripheral Output 3
+    GpioGpio3 = 6,
+    /// Peripheral Output 4
+    GpioGpio4 = 7,
+    /// Peripheral Output 5
+    GpioGpio5 = 8,
+    /// Peripheral Output 6
+    GpioGpio6 = 9,
+    /// Peripheral Output 7
+    GpioGpio7 = 10,
+    /// Peripheral Output 8
+    GpioGpio8 = 11,
+    /// Peripheral Output 9
+    GpioGpio9 = 12,
+    /// Peripheral Output 10
+    GpioGpio10 = 13,
+    /// Peripheral Output 11
+    GpioGpio11 = 14,
+    /// Peripheral Output 12
+    GpioGpio12 = 15,
+    /// Peripheral Output 13
+    GpioGpio13 = 16,
+    /// Peripheral Output 14
+    GpioGpio14 = 17,
+    /// Peripheral Output 15
+    GpioGpio15 = 18,
+    /// Peripheral Output 16
+    GpioGpio16 = 19,
+    /// Peripheral Output 17
+    GpioGpio17 = 20,
+    /// Peripheral Output 18
+    GpioGpio18 = 21,
+    /// Peripheral Output 19
+    GpioGpio19 = 22,
+    /// Peripheral Output 20
+    GpioGpio20 = 23,
+    /// Peripheral Output 21
+    GpioGpio21 = 24,
+    /// Peripheral Output 22
+    GpioGpio22 = 25,
+    /// Peripheral Output 23
+    GpioGpio23 = 26,
+    /// Peripheral Output 24
+    GpioGpio24 = 27,
+    /// Peripheral Output 25
+    GpioGpio25 = 28,
+    /// Peripheral Output 26
+    GpioGpio26 = 29,
+    /// Peripheral Output 27
+    GpioGpio27 = 30,
+    /// Peripheral Output 28
+    GpioGpio28 = 31,
+    /// Peripheral Output 29
+    GpioGpio29 = 32,
+    /// Peripheral Output 30
+    GpioGpio30 = 33,
+    /// Peripheral Output 31
+    GpioGpio31 = 34,
+    /// Peripheral Output 32
+    I2c0Sda = 35,
+    /// Peripheral Output 33
+    I2c0Scl = 36,
+    /// Peripheral Output 34
+    I2c1Sda = 37,
+    /// Peripheral Output 35
+    I2c1Scl = 38,
+    /// Peripheral Output 36
+    I2c2Sda = 39,
+    /// Peripheral Output 37
+    I2c2Scl = 40,
+    /// Peripheral Output 38
+    SpiHost1Sd0 = 41,
+    /// Peripheral Output 39
+    SpiHost1Sd1 = 42,
+    /// Peripheral Output 40
+    SpiHost1Sd2 = 43,
+    /// Peripheral Output 41
+    SpiHost1Sd3 = 44,
+    /// Peripheral Output 42
+    Uart0Tx = 45,
+    /// Peripheral Output 43
+    Uart1Tx = 46,
+    /// Peripheral Output 44
+    Uart2Tx = 47,
+    /// Peripheral Output 45
+    Uart3Tx = 48,
+    /// Peripheral Output 46
+    PattgenPda0Tx = 49,
+    /// Peripheral Output 47
+    PattgenPcl0Tx = 50,
+    /// Peripheral Output 48
+    PattgenPda1Tx = 51,
+    /// Peripheral Output 49
+    PattgenPcl1Tx = 52,
+    /// Peripheral Output 50
+    SpiHost1Sck = 53,
+    /// Peripheral Output 51
+    SpiHost1Csb = 54,
+    /// Peripheral Output 52
+    FlashCtrlTdo = 55,
+    /// Peripheral Output 53
+    SensorCtrlAonAstDebugOut0 = 56,
+    /// Peripheral Output 54
+    SensorCtrlAonAstDebugOut1 = 57,
+    /// Peripheral Output 55
+    SensorCtrlAonAstDebugOut2 = 58,
+    /// Peripheral Output 56
+    SensorCtrlAonAstDebugOut3 = 59,
+    /// Peripheral Output 57
+    SensorCtrlAonAstDebugOut4 = 60,
+    /// Peripheral Output 58
+    SensorCtrlAonAstDebugOut5 = 61,
+    /// Peripheral Output 59
+    SensorCtrlAonAstDebugOut6 = 62,
+    /// Peripheral Output 60
+    SensorCtrlAonAstDebugOut7 = 63,
+    /// Peripheral Output 61
+    SensorCtrlAonAstDebugOut8 = 64,
+    /// Peripheral Output 62
+    PwmAonPwm0 = 65,
+    /// Peripheral Output 63
+    PwmAonPwm1 = 66,
+    /// Peripheral Output 64
+    PwmAonPwm2 = 67,
+    /// Peripheral Output 65
+    PwmAonPwm3 = 68,
+    /// Peripheral Output 66
+    PwmAonPwm4 = 69,
+    /// Peripheral Output 67
+    PwmAonPwm5 = 70,
+    /// Peripheral Output 68
+    OtpCtrlTest0 = 71,
+    /// Peripheral Output 69
+    SysrstCtrlAonBatDisable = 72,
+    /// Peripheral Output 70
+    SysrstCtrlAonKey0Out = 73,
+    /// Peripheral Output 71
+    SysrstCtrlAonKey1Out = 74,
+    /// Peripheral Output 72
+    SysrstCtrlAonKey2Out = 75,
+    /// Peripheral Output 73
+    SysrstCtrlAonPwrbOut = 76,
+    /// Peripheral Output 74
+    SysrstCtrlAonZ3Wakeup = 77,
+}
+
+impl TryFrom<u32> for PinmuxOutsel {
+    type Error = u32;
+    fn try_from(val: u32) -> Result<Self, Self::Error> {
+        match val {
+            0 => Ok(Self::ConstantZero),
+            1 => Ok(Self::ConstantOne),
+            2 => Ok(Self::ConstantHighZ),
+            3 => Ok(Self::GpioGpio0),
+            4 => Ok(Self::GpioGpio1),
+            5 => Ok(Self::GpioGpio2),
+            6 => Ok(Self::GpioGpio3),
+            7 => Ok(Self::GpioGpio4),
+            8 => Ok(Self::GpioGpio5),
+            9 => Ok(Self::GpioGpio6),
+            10 => Ok(Self::GpioGpio7),
+            11 => Ok(Self::GpioGpio8),
+            12 => Ok(Self::GpioGpio9),
+            13 => Ok(Self::GpioGpio10),
+            14 => Ok(Self::GpioGpio11),
+            15 => Ok(Self::GpioGpio12),
+            16 => Ok(Self::GpioGpio13),
+            17 => Ok(Self::GpioGpio14),
+            18 => Ok(Self::GpioGpio15),
+            19 => Ok(Self::GpioGpio16),
+            20 => Ok(Self::GpioGpio17),
+            21 => Ok(Self::GpioGpio18),
+            22 => Ok(Self::GpioGpio19),
+            23 => Ok(Self::GpioGpio20),
+            24 => Ok(Self::GpioGpio21),
+            25 => Ok(Self::GpioGpio22),
+            26 => Ok(Self::GpioGpio23),
+            27 => Ok(Self::GpioGpio24),
+            28 => Ok(Self::GpioGpio25),
+            29 => Ok(Self::GpioGpio26),
+            30 => Ok(Self::GpioGpio27),
+            31 => Ok(Self::GpioGpio28),
+            32 => Ok(Self::GpioGpio29),
+            33 => Ok(Self::GpioGpio30),
+            34 => Ok(Self::GpioGpio31),
+            35 => Ok(Self::I2c0Sda),
+            36 => Ok(Self::I2c0Scl),
+            37 => Ok(Self::I2c1Sda),
+            38 => Ok(Self::I2c1Scl),
+            39 => Ok(Self::I2c2Sda),
+            40 => Ok(Self::I2c2Scl),
+            41 => Ok(Self::SpiHost1Sd0),
+            42 => Ok(Self::SpiHost1Sd1),
+            43 => Ok(Self::SpiHost1Sd2),
+            44 => Ok(Self::SpiHost1Sd3),
+            45 => Ok(Self::Uart0Tx),
+            46 => Ok(Self::Uart1Tx),
+            47 => Ok(Self::Uart2Tx),
+            48 => Ok(Self::Uart3Tx),
+            49 => Ok(Self::PattgenPda0Tx),
+            50 => Ok(Self::PattgenPcl0Tx),
+            51 => Ok(Self::PattgenPda1Tx),
+            52 => Ok(Self::PattgenPcl1Tx),
+            53 => Ok(Self::SpiHost1Sck),
+            54 => Ok(Self::SpiHost1Csb),
+            55 => Ok(Self::FlashCtrlTdo),
+            56 => Ok(Self::SensorCtrlAonAstDebugOut0),
+            57 => Ok(Self::SensorCtrlAonAstDebugOut1),
+            58 => Ok(Self::SensorCtrlAonAstDebugOut2),
+            59 => Ok(Self::SensorCtrlAonAstDebugOut3),
+            60 => Ok(Self::SensorCtrlAonAstDebugOut4),
+            61 => Ok(Self::SensorCtrlAonAstDebugOut5),
+            62 => Ok(Self::SensorCtrlAonAstDebugOut6),
+            63 => Ok(Self::SensorCtrlAonAstDebugOut7),
+            64 => Ok(Self::SensorCtrlAonAstDebugOut8),
+            65 => Ok(Self::PwmAonPwm0),
+            66 => Ok(Self::PwmAonPwm1),
+            67 => Ok(Self::PwmAonPwm2),
+            68 => Ok(Self::PwmAonPwm3),
+            69 => Ok(Self::PwmAonPwm4),
+            70 => Ok(Self::PwmAonPwm5),
+            71 => Ok(Self::OtpCtrlTest0),
+            72 => Ok(Self::SysrstCtrlAonBatDisable),
+            73 => Ok(Self::SysrstCtrlAonKey0Out),
+            74 => Ok(Self::SysrstCtrlAonKey1Out),
+            75 => Ok(Self::SysrstCtrlAonKey2Out),
+            76 => Ok(Self::SysrstCtrlAonPwrbOut),
+            77 => Ok(Self::SysrstCtrlAonZ3Wakeup),
+            _ => Err(val),
+        }
+    }
+}
+
+/// Dedicated Pad Selects
+#[derive(Copy, Clone, PartialEq, Eq)]
+#[repr(u32)]
+pub enum DirectPads {
+    UsbdevUsbDp = 0,
+    UsbdevUsbDn = 1,
+    SpiHost0Sd0 = 2,
+    SpiHost0Sd1 = 3,
+    SpiHost0Sd2 = 4,
+    SpiHost0Sd3 = 5,
+    SpiDeviceSd0 = 6,
+    SpiDeviceSd1 = 7,
+    SpiDeviceSd2 = 8,
+    SpiDeviceSd3 = 9,
+    SysrstCtrlAonEcRstL = 10,
+    SysrstCtrlAonFlashWpL = 11,
+    SpiDeviceSck = 12,
+    SpiDeviceCsb = 13,
+    SpiHost0Sck = 14,
+    SpiHost0Csb = 15,
+}
+
+impl TryFrom<u32> for DirectPads {
+    type Error = u32;
+    fn try_from(val: u32) -> Result<Self, Self::Error> {
+        match val {
+            0 => Ok(Self::UsbdevUsbDp),
+            1 => Ok(Self::UsbdevUsbDn),
+            2 => Ok(Self::SpiHost0Sd0),
+            3 => Ok(Self::SpiHost0Sd1),
+            4 => Ok(Self::SpiHost0Sd2),
+            5 => Ok(Self::SpiHost0Sd3),
+            6 => Ok(Self::SpiDeviceSd0),
+            7 => Ok(Self::SpiDeviceSd1),
+            8 => Ok(Self::SpiDeviceSd2),
+            9 => Ok(Self::SpiDeviceSd3),
+            10 => Ok(Self::SysrstCtrlAonEcRstL),
+            11 => Ok(Self::SysrstCtrlAonFlashWpL),
+            12 => Ok(Self::SpiDeviceSck),
+            13 => Ok(Self::SpiDeviceCsb),
+            14 => Ok(Self::SpiHost0Sck),
+            15 => Ok(Self::SpiHost0Csb),
+            _ => Err(val),
+        }
+    }
+}
+
+/// Muxed Pad Selects
+#[derive(Copy, Clone, PartialEq, Eq)]
+#[repr(u32)]
+pub enum MuxedPads {
+    Ioa0 = 0,
+    Ioa1 = 1,
+    Ioa2 = 2,
+    Ioa3 = 3,
+    Ioa4 = 4,
+    Ioa5 = 5,
+    Ioa6 = 6,
+    Ioa7 = 7,
+    Ioa8 = 8,
+    Iob0 = 9,
+    Iob1 = 10,
+    Iob2 = 11,
+    Iob3 = 12,
+    Iob4 = 13,
+    Iob5 = 14,
+    Iob6 = 15,
+    Iob7 = 16,
+    Iob8 = 17,
+    Iob9 = 18,
+    Iob10 = 19,
+    Iob11 = 20,
+    Iob12 = 21,
+    Ioc0 = 22,
+    Ioc1 = 23,
+    Ioc2 = 24,
+    Ioc3 = 25,
+    Ioc4 = 26,
+    Ioc5 = 27,
+    Ioc6 = 28,
+    Ioc7 = 29,
+    Ioc8 = 30,
+    Ioc9 = 31,
+    Ioc10 = 32,
+    Ioc11 = 33,
+    Ioc12 = 34,
+    Ior0 = 35,
+    Ior1 = 36,
+    Ior2 = 37,
+    Ior3 = 38,
+    Ior4 = 39,
+    Ior5 = 40,
+    Ior6 = 41,
+    Ior7 = 42,
+    Ior10 = 43,
+    Ior11 = 44,
+    Ior12 = 45,
+    Ior13 = 46,
+}
+
+impl TryFrom<u32> for MuxedPads {
+    type Error = u32;
+    fn try_from(val: u32) -> Result<Self, Self::Error> {
+        match val {
+            0 => Ok(Self::Ioa0),
+            1 => Ok(Self::Ioa1),
+            2 => Ok(Self::Ioa2),
+            3 => Ok(Self::Ioa3),
+            4 => Ok(Self::Ioa4),
+            5 => Ok(Self::Ioa5),
+            6 => Ok(Self::Ioa6),
+            7 => Ok(Self::Ioa7),
+            8 => Ok(Self::Ioa8),
+            9 => Ok(Self::Iob0),
+            10 => Ok(Self::Iob1),
+            11 => Ok(Self::Iob2),
+            12 => Ok(Self::Iob3),
+            13 => Ok(Self::Iob4),
+            14 => Ok(Self::Iob5),
+            15 => Ok(Self::Iob6),
+            16 => Ok(Self::Iob7),
+            17 => Ok(Self::Iob8),
+            18 => Ok(Self::Iob9),
+            19 => Ok(Self::Iob10),
+            20 => Ok(Self::Iob11),
+            21 => Ok(Self::Iob12),
+            22 => Ok(Self::Ioc0),
+            23 => Ok(Self::Ioc1),
+            24 => Ok(Self::Ioc2),
+            25 => Ok(Self::Ioc3),
+            26 => Ok(Self::Ioc4),
+            27 => Ok(Self::Ioc5),
+            28 => Ok(Self::Ioc6),
+            29 => Ok(Self::Ioc7),
+            30 => Ok(Self::Ioc8),
+            31 => Ok(Self::Ioc9),
+            32 => Ok(Self::Ioc10),
+            33 => Ok(Self::Ioc11),
+            34 => Ok(Self::Ioc12),
+            35 => Ok(Self::Ior0),
+            36 => Ok(Self::Ior1),
+            37 => Ok(Self::Ior2),
+            38 => Ok(Self::Ior3),
+            39 => Ok(Self::Ior4),
+            40 => Ok(Self::Ior5),
+            41 => Ok(Self::Ior6),
+            42 => Ok(Self::Ior7),
+            43 => Ok(Self::Ior10),
+            44 => Ok(Self::Ior11),
+            45 => Ok(Self::Ior12),
+            46 => Ok(Self::Ior13),
+            _ => Err(val),
+        }
+    }
+}
+
+/// Power Manager Wakeup Signals
+#[derive(Copy, Clone, PartialEq, Eq)]
+#[repr(u32)]
+pub enum PowerManagerWakeUps {
+    SysrstCtrlAonWkupReq = 0,
+    AdcCtrlAonWkupReq = 1,
+    PinmuxAonPinWkupReq = 2,
+    PinmuxAonUsbWkupReq = 3,
+    AonTimerAonWkupReq = 4,
+    SensorCtrlAonWkupReq = 5,
+}
+
+/// Reset Manager Software Controlled Resets
+#[derive(Copy, Clone, PartialEq, Eq)]
+#[repr(u32)]
+pub enum ResetManagerSwResets {
+    SpiDevice = 0,
+    SpiHost0 = 1,
+    SpiHost1 = 2,
+    Usb = 3,
+    UsbAon = 4,
+    I2c0 = 5,
+    I2c1 = 6,
+    I2c2 = 7,
+}
+
+/// Power Manager Reset Request Signals
+#[derive(Copy, Clone, PartialEq, Eq)]
+#[repr(u32)]
+pub enum PowerManagerResetRequests {
+    SysrstCtrlAonRstReq = 0,
+    AonTimerAonAonTimerRstReq = 1,
+}
+
+/// Clock Manager Software-Controlled ("Gated") Clocks.
+///
+/// The Software has full control over these clocks.
+#[derive(Copy, Clone, PartialEq, Eq)]
+#[repr(u32)]
+pub enum GateableClocks {
+    /// Clock clk_io_div4_peri in group peri
+    IoDiv4Peri = 0,
+    /// Clock clk_io_div2_peri in group peri
+    IoDiv2Peri = 1,
+    /// Clock clk_io_peri in group peri
+    IoPeri = 2,
+    /// Clock clk_usb_peri in group peri
+    UsbPeri = 3,
+}
+
+/// Clock Manager Software-Hinted Clocks.
+///
+/// The Software has partial control over these clocks. It can ask them to stop,
+/// but the clock manager is in control of whether the clock actually is stopped.
+#[derive(Copy, Clone, PartialEq, Eq)]
+#[repr(u32)]
+pub enum HintableClocks {
+    /// Clock clk_main_aes in group trans
+    MainAes = 0,
+    /// Clock clk_main_hmac in group trans
+    MainHmac = 1,
+    /// Clock clk_main_kmac in group trans
+    MainKmac = 2,
+    /// Clock clk_main_otbn in group trans
+    MainOtbn = 3,
+}
+
+/// MMIO Region
+///
+/// MMIO region excludes any memory that is separate from the module
+/// configuration space, i.e. ROM, main SRAM, and flash are excluded but
+/// retention SRAM, spi_device memory, or usbdev memory are included.
+pub const MMIO_BASE_ADDR: usize = 0x40000000;
+pub const MMIO_SIZE_BYTES: usize = 0x10000000;
diff --git a/target/earlgrey/registers/usbdev.rs b/target/earlgrey/registers/usbdev.rs
index 1a3c8e10..ca1388cd 100644
--- a/target/earlgrey/registers/usbdev.rs
+++ b/target/earlgrey/registers/usbdev.rs
@@ -40,6 +40,42 @@ impl Usbdev {
         }
     }
 }
+#[doc = r" A zero-sized type that represents ownership of this"]
+#[doc = r" peripheral, used to get access to a Register lock. Most"]
+#[doc = r" programs create one of these in unsafe code near the top of"]
+#[doc = r" main(), and pass it to the driver responsible for managing"]
+#[doc = r" all access to the hardware."]
+#[doc = r" "]
+#[doc = r" Unlike the non-IntMut instance, this instance allows registers"]
+#[doc = r" to be mutated with only a `&self` reference, which is"]
+#[doc = r" useful when constructing a driver that needs to be"]
+#[doc = r" shared. The driver is responsible for ensuring that shared"]
+#[doc = r" access to these registers is done in a compatible way. "]
+pub struct UsbdevIntMut {
+    _priv: (),
+}
+impl UsbdevIntMut {
+    pub const PTR: *mut u32 = 0x40320000 as *mut u32;
+    #[doc = r" # Safety"]
+    #[doc = r""]
+    #[doc = r" Caller must ensure that all concurrent use of this"]
+    #[doc = r" peripheral in the firmware is done so in a compatible"]
+    #[doc = r" way. The simplest way to enforce this is to only call"]
+    #[doc = r" this function once."]
+    #[inline(always)]
+    pub unsafe fn new() -> Self {
+        Self { _priv: () }
+    }
+    #[doc = r" Returns a register block that can be used to read and write"]
+    #[doc = r" registers from this peripheral."]
+    #[inline(always)]
+    pub fn regs(&self) -> RegisterBlock<ureg::RealMmioMut<'_>> {
+        RegisterBlock {
+            ptr: Self::PTR,
+            mmio: core::default::Default::default(),
+        }
+    }
+}
 #[derive(Clone, Copy)]
 pub struct RegisterBlock<TMmio: ureg::Mmio + core::borrow::Borrow<TMmio>> {
     ptr: *mut u32,
@@ -79,6 +115,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "Interrupt State Register\n\nRead value: [`regs::IntrStateReadVal`]; Write value: [`regs::IntrStateWriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_intr_state(self) -> ureg::RegRef<crate::meta::IntrState, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "Interrupt Enable Register\n\nRead value: [`regs::IntrEnableReadVal`]; Write value: [`regs::IntrEnableWriteVal`]"]
     #[inline(always)]
     pub fn intr_enable(&self) -> ureg::RegRef<crate::meta::IntrEnable, &TMmio> {
@@ -89,6 +136,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "Interrupt Enable Register\n\nRead value: [`regs::IntrEnableReadVal`]; Write value: [`regs::IntrEnableWriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_intr_enable(self) -> ureg::RegRef<crate::meta::IntrEnable, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(4 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "Interrupt Test Register\n\nRead value: [`regs::IntrTestReadVal`]; Write value: [`regs::IntrTestWriteVal`]"]
     #[inline(always)]
     pub fn intr_test(&self) -> ureg::RegRef<crate::meta::IntrTest, &TMmio> {
@@ -99,6 +157,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "Interrupt Test Register\n\nRead value: [`regs::IntrTestReadVal`]; Write value: [`regs::IntrTestWriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_intr_test(self) -> ureg::RegRef<crate::meta::IntrTest, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(8 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "Alert Test Register\n\nRead value: [`regs::AlertTestReadVal`]; Write value: [`regs::AlertTestWriteVal`]"]
     #[inline(always)]
     pub fn alert_test(&self) -> ureg::RegRef<crate::meta::AlertTest, &TMmio> {
@@ -109,6 +178,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "Alert Test Register\n\nRead value: [`regs::AlertTestReadVal`]; Write value: [`regs::AlertTestWriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_alert_test(self) -> ureg::RegRef<crate::meta::AlertTest, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0xc / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "USB Control\n\nRead value: [`regs::UsbctrlReadVal`]; Write value: [`regs::UsbctrlWriteVal`]"]
     #[inline(always)]
     pub fn usbctrl(&self) -> ureg::RegRef<crate::meta::Usbctrl, &TMmio> {
@@ -119,6 +199,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "USB Control\n\nRead value: [`regs::UsbctrlReadVal`]; Write value: [`regs::UsbctrlWriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_usbctrl(self) -> ureg::RegRef<crate::meta::Usbctrl, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x10 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "Enable an endpoint to respond to transactions in the downstream direction.\nNote that as the default endpoint, endpoint 0 must be enabled in both the IN and OUT directions before enabling the USB interface to connect.\n\nRead value: [`regs::EpOutEnable0ReadVal`]; Write value: [`regs::EpOutEnable0WriteVal`]"]
     #[inline(always)]
     pub fn ep_out_enable0(&self) -> ureg::RegRef<crate::meta::EpOutEnable0, &TMmio> {
@@ -129,6 +220,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "Enable an endpoint to respond to transactions in the downstream direction.\nNote that as the default endpoint, endpoint 0 must be enabled in both the IN and OUT directions before enabling the USB interface to connect.\n\nRead value: [`regs::EpOutEnable0ReadVal`]; Write value: [`regs::EpOutEnable0WriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_ep_out_enable0(self) -> ureg::RegRef<crate::meta::EpOutEnable0, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x14 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "Enable an endpoint to respond to transactions in the upstream direction.\nNote that as the default endpoint, endpoint 0 must be enabled in both the IN and OUT directions before enabling the USB interface to connect.\n\nRead value: [`regs::EpInEnable0ReadVal`]; Write value: [`regs::EpInEnable0WriteVal`]"]
     #[inline(always)]
     pub fn ep_in_enable0(&self) -> ureg::RegRef<crate::meta::EpInEnable0, &TMmio> {
@@ -139,6 +241,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "Enable an endpoint to respond to transactions in the upstream direction.\nNote that as the default endpoint, endpoint 0 must be enabled in both the IN and OUT directions before enabling the USB interface to connect.\n\nRead value: [`regs::EpInEnable0ReadVal`]; Write value: [`regs::EpInEnable0WriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_ep_in_enable0(self) -> ureg::RegRef<crate::meta::EpInEnable0, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x18 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "USB Status\n\nRead value: [`regs::UsbstatReadVal`]; Write value: [`regs::UsbstatWriteVal`]"]
     #[inline(always)]
     pub fn usbstat(&self) -> ureg::RegRef<crate::meta::Usbstat, &TMmio> {
@@ -149,6 +262,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "USB Status\n\nRead value: [`regs::UsbstatReadVal`]; Write value: [`regs::UsbstatWriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_usbstat(self) -> ureg::RegRef<crate::meta::Usbstat, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x1c / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "Available OUT Buffer FIFO\n\nRead value: [`regs::AvoutbufferReadVal`]; Write value: [`regs::AvoutbufferWriteVal`]"]
     #[inline(always)]
     pub fn avoutbuffer(&self) -> ureg::RegRef<crate::meta::Avoutbuffer, &TMmio> {
@@ -159,6 +283,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "Available OUT Buffer FIFO\n\nRead value: [`regs::AvoutbufferReadVal`]; Write value: [`regs::AvoutbufferWriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_avoutbuffer(self) -> ureg::RegRef<crate::meta::Avoutbuffer, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x20 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "Available SETUP Buffer FIFO\n\nRead value: [`regs::AvsetupbufferReadVal`]; Write value: [`regs::AvsetupbufferWriteVal`]"]
     #[inline(always)]
     pub fn avsetupbuffer(&self) -> ureg::RegRef<crate::meta::Avsetupbuffer, &TMmio> {
@@ -169,6 +304,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "Available SETUP Buffer FIFO\n\nRead value: [`regs::AvsetupbufferReadVal`]; Write value: [`regs::AvsetupbufferWriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_avsetupbuffer(self) -> ureg::RegRef<crate::meta::Avsetupbuffer, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x24 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "Received Buffer FIFO\n\nRead value: [`regs::RxfifoReadVal`]; Write value: [`regs::RxfifoWriteVal`]"]
     #[inline(always)]
     pub fn rxfifo(&self) -> ureg::RegRef<crate::meta::Rxfifo, &TMmio> {
@@ -179,6 +325,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "Received Buffer FIFO\n\nRead value: [`regs::RxfifoReadVal`]; Write value: [`regs::RxfifoWriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_rxfifo(self) -> ureg::RegRef<crate::meta::Rxfifo, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x28 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "Receive SETUP transaction enable\n\nRead value: [`regs::RxenableSetup0ReadVal`]; Write value: [`regs::RxenableSetup0WriteVal`]"]
     #[inline(always)]
     pub fn rxenable_setup0(&self) -> ureg::RegRef<crate::meta::RxenableSetup0, &TMmio> {
@@ -189,6 +346,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "Receive SETUP transaction enable\n\nRead value: [`regs::RxenableSetup0ReadVal`]; Write value: [`regs::RxenableSetup0WriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_rxenable_setup0(self) -> ureg::RegRef<crate::meta::RxenableSetup0, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x2c / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "Receive OUT transaction enable\n\nRead value: [`regs::RxenableOut0ReadVal`]; Write value: [`regs::RxenableOut0WriteVal`]"]
     #[inline(always)]
     pub fn rxenable_out0(&self) -> ureg::RegRef<crate::meta::RxenableOut0, &TMmio> {
@@ -199,6 +367,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "Receive OUT transaction enable\n\nRead value: [`regs::RxenableOut0ReadVal`]; Write value: [`regs::RxenableOut0WriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_rxenable_out0(self) -> ureg::RegRef<crate::meta::RxenableOut0, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x30 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "Set NAK after OUT transactions\n\nRead value: [`regs::SetNakOut0ReadVal`]; Write value: [`regs::SetNakOut0WriteVal`]"]
     #[inline(always)]
     pub fn set_nak_out0(&self) -> ureg::RegRef<crate::meta::SetNakOut0, &TMmio> {
@@ -209,6 +388,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "Set NAK after OUT transactions\n\nRead value: [`regs::SetNakOut0ReadVal`]; Write value: [`regs::SetNakOut0WriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_set_nak_out0(self) -> ureg::RegRef<crate::meta::SetNakOut0, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x34 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "IN Transaction Sent\n\nRead value: [`regs::InSent0ReadVal`]; Write value: [`regs::InSent0WriteVal`]"]
     #[inline(always)]
     pub fn in_sent0(&self) -> ureg::RegRef<crate::meta::InSent0, &TMmio> {
@@ -219,6 +409,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "IN Transaction Sent\n\nRead value: [`regs::InSent0ReadVal`]; Write value: [`regs::InSent0WriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_in_sent0(self) -> ureg::RegRef<crate::meta::InSent0, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x38 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "OUT Endpoint STALL control\n\nRead value: [`regs::OutStall0ReadVal`]; Write value: [`regs::OutStall0WriteVal`]"]
     #[inline(always)]
     pub fn out_stall0(&self) -> ureg::RegRef<crate::meta::OutStall0, &TMmio> {
@@ -229,6 +430,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "OUT Endpoint STALL control\n\nRead value: [`regs::OutStall0ReadVal`]; Write value: [`regs::OutStall0WriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_out_stall0(self) -> ureg::RegRef<crate::meta::OutStall0, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x3c / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "IN Endpoint STALL control\n\nRead value: [`regs::InStall0ReadVal`]; Write value: [`regs::InStall0WriteVal`]"]
     #[inline(always)]
     pub fn in_stall0(&self) -> ureg::RegRef<crate::meta::InStall0, &TMmio> {
@@ -239,6 +451,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "IN Endpoint STALL control\n\nRead value: [`regs::InStall0ReadVal`]; Write value: [`regs::InStall0WriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_in_stall0(self) -> ureg::RegRef<crate::meta::InStall0, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x40 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "Configure IN Transaction\n\nRead value: [`regs::ConfiginReadVal`]; Write value: [`regs::ConfiginWriteVal`]"]
     #[inline(always)]
     pub fn configin(&self) -> ureg::Array<12, ureg::RegRef<crate::meta::Configin, &TMmio>> {
@@ -249,6 +472,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "Configure IN Transaction\n\nRead value: [`regs::ConfiginReadVal`]; Write value: [`regs::ConfiginWriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_configin(self) -> ureg::Array<12, ureg::RegRef<crate::meta::Configin, TMmio>> {
+        unsafe {
+            ureg::Array::new_with_mmio(
+                self.ptr.wrapping_add(0x44 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "OUT Endpoint isochronous setting\n\nRead value: [`regs::OutIso0ReadVal`]; Write value: [`regs::OutIso0WriteVal`]"]
     #[inline(always)]
     pub fn out_iso0(&self) -> ureg::RegRef<crate::meta::OutIso0, &TMmio> {
@@ -259,6 +493,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "OUT Endpoint isochronous setting\n\nRead value: [`regs::OutIso0ReadVal`]; Write value: [`regs::OutIso0WriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_out_iso0(self) -> ureg::RegRef<crate::meta::OutIso0, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x74 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "IN Endpoint isochronous setting\n\nRead value: [`regs::InIso0ReadVal`]; Write value: [`regs::InIso0WriteVal`]"]
     #[inline(always)]
     pub fn in_iso0(&self) -> ureg::RegRef<crate::meta::InIso0, &TMmio> {
@@ -269,6 +514,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "IN Endpoint isochronous setting\n\nRead value: [`regs::InIso0ReadVal`]; Write value: [`regs::InIso0WriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_in_iso0(self) -> ureg::RegRef<crate::meta::InIso0, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x78 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "OUT Endpoints Data Toggles\n\nRead value: [`regs::OutDataToggleReadVal`]; Write value: [`regs::OutDataToggleWriteVal`]"]
     #[inline(always)]
     pub fn out_data_toggle(&self) -> ureg::RegRef<crate::meta::OutDataToggle, &TMmio> {
@@ -279,6 +535,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "OUT Endpoints Data Toggles\n\nRead value: [`regs::OutDataToggleReadVal`]; Write value: [`regs::OutDataToggleWriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_out_data_toggle(self) -> ureg::RegRef<crate::meta::OutDataToggle, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x7c / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "IN Endpoints Data Toggles\n\nRead value: [`regs::InDataToggleReadVal`]; Write value: [`regs::InDataToggleWriteVal`]"]
     #[inline(always)]
     pub fn in_data_toggle(&self) -> ureg::RegRef<crate::meta::InDataToggle, &TMmio> {
@@ -289,6 +556,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "IN Endpoints Data Toggles\n\nRead value: [`regs::InDataToggleReadVal`]; Write value: [`regs::InDataToggleWriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_in_data_toggle(self) -> ureg::RegRef<crate::meta::InDataToggle, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x80 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "USB PHY pins sense.\nThis register can be used to read out the state of the USB device inputs and outputs from software.\nThis is designed to be used for debugging purposes or during chip testing.\n\nRead value: [`regs::PhyPinsSenseReadVal`]; Write value: [`regs::PhyPinsSenseWriteVal`]"]
     #[inline(always)]
     pub fn phy_pins_sense(&self) -> ureg::RegRef<crate::meta::PhyPinsSense, &TMmio> {
@@ -299,6 +577,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "USB PHY pins sense.\nThis register can be used to read out the state of the USB device inputs and outputs from software.\nThis is designed to be used for debugging purposes or during chip testing.\n\nRead value: [`regs::PhyPinsSenseReadVal`]; Write value: [`regs::PhyPinsSenseWriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_phy_pins_sense(self) -> ureg::RegRef<crate::meta::PhyPinsSense, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x84 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "USB PHY pins drive.\nThis register can be used to control the USB device inputs and outputs from software.\nThis is designed to be used for debugging purposes or during chip testing.\n\nRead value: [`regs::PhyPinsDriveReadVal`]; Write value: [`regs::PhyPinsDriveWriteVal`]"]
     #[inline(always)]
     pub fn phy_pins_drive(&self) -> ureg::RegRef<crate::meta::PhyPinsDrive, &TMmio> {
@@ -309,6 +598,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "USB PHY pins drive.\nThis register can be used to control the USB device inputs and outputs from software.\nThis is designed to be used for debugging purposes or during chip testing.\n\nRead value: [`regs::PhyPinsDriveReadVal`]; Write value: [`regs::PhyPinsDriveWriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_phy_pins_drive(self) -> ureg::RegRef<crate::meta::PhyPinsDrive, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x88 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "USB PHY Configuration\n\nRead value: [`regs::PhyConfigReadVal`]; Write value: [`regs::PhyConfigWriteVal`]"]
     #[inline(always)]
     pub fn phy_config(&self) -> ureg::RegRef<crate::meta::PhyConfig, &TMmio> {
@@ -319,6 +619,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "USB PHY Configuration\n\nRead value: [`regs::PhyConfigReadVal`]; Write value: [`regs::PhyConfigWriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_phy_config(self) -> ureg::RegRef<crate::meta::PhyConfig, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x8c / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "USB wake module control for suspend / resume\n\nRead value: [`regs::WakeControlReadVal`]; Write value: [`regs::WakeControlWriteVal`]"]
     #[inline(always)]
     pub fn wake_control(&self) -> ureg::RegRef<crate::meta::WakeControl, &TMmio> {
@@ -329,6 +640,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "USB wake module control for suspend / resume\n\nRead value: [`regs::WakeControlReadVal`]; Write value: [`regs::WakeControlWriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_wake_control(self) -> ureg::RegRef<crate::meta::WakeControl, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x90 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "USB wake module events and debug\n\nRead value: [`regs::WakeEventsReadVal`]; Write value: [`regs::WakeEventsWriteVal`]"]
     #[inline(always)]
     pub fn wake_events(&self) -> ureg::RegRef<crate::meta::WakeEvents, &TMmio> {
@@ -339,6 +661,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "USB wake module events and debug\n\nRead value: [`regs::WakeEventsReadVal`]; Write value: [`regs::WakeEventsWriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_wake_events(self) -> ureg::RegRef<crate::meta::WakeEvents, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x94 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "FIFO control register\n\nRead value: [`regs::FifoCtrlReadVal`]; Write value: [`regs::FifoCtrlWriteVal`]"]
     #[inline(always)]
     pub fn fifo_ctrl(&self) -> ureg::RegRef<crate::meta::FifoCtrl, &TMmio> {
@@ -349,6 +682,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "FIFO control register\n\nRead value: [`regs::FifoCtrlReadVal`]; Write value: [`regs::FifoCtrlWriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_fifo_ctrl(self) -> ureg::RegRef<crate::meta::FifoCtrl, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x98 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "Counter for OUT side USB events.\n\nRead value: [`regs::CountOutReadVal`]; Write value: [`regs::CountOutWriteVal`]"]
     #[inline(always)]
     pub fn count_out(&self) -> ureg::RegRef<crate::meta::CountOut, &TMmio> {
@@ -359,6 +703,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "Counter for OUT side USB events.\n\nRead value: [`regs::CountOutReadVal`]; Write value: [`regs::CountOutWriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_count_out(self) -> ureg::RegRef<crate::meta::CountOut, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x9c / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "Counter for IN side USB events.\n\nRead value: [`regs::CountInReadVal`]; Write value: [`regs::CountInWriteVal`]"]
     #[inline(always)]
     pub fn count_in(&self) -> ureg::RegRef<crate::meta::CountIn, &TMmio> {
@@ -369,6 +724,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "Counter for IN side USB events.\n\nRead value: [`regs::CountInReadVal`]; Write value: [`regs::CountInWriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_count_in(self) -> ureg::RegRef<crate::meta::CountIn, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0xa0 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "Count of IN transactions for which no packet data was available.\n\nThis secondary register allows some partitioning of endpoints among the two\ncounters, for more targeted measurement, eg. endpoints may be grouped according to\nthe expected bandwidth usage, or Isochronous vs. non-Isochronous transfers.\n\nRead value: [`regs::CountNodataInReadVal`]; Write value: [`regs::CountNodataInWriteVal`]"]
     #[inline(always)]
     pub fn count_nodata_in(&self) -> ureg::RegRef<crate::meta::CountNodataIn, &TMmio> {
@@ -379,6 +745,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "Count of IN transactions for which no packet data was available.\n\nThis secondary register allows some partitioning of endpoints among the two\ncounters, for more targeted measurement, eg. endpoints may be grouped according to\nthe expected bandwidth usage, or Isochronous vs. non-Isochronous transfers.\n\nRead value: [`regs::CountNodataInReadVal`]; Write value: [`regs::CountNodataInWriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_count_nodata_in(self) -> ureg::RegRef<crate::meta::CountNodataIn, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0xa4 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "Count of error conditions detected on token packets from the host.\n\nRead value: [`regs::CountErrorsReadVal`]; Write value: [`regs::CountErrorsWriteVal`]"]
     #[inline(always)]
     pub fn count_errors(&self) -> ureg::RegRef<crate::meta::CountErrors, &TMmio> {
@@ -389,6 +766,17 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "Count of error conditions detected on token packets from the host.\n\nRead value: [`regs::CountErrorsReadVal`]; Write value: [`regs::CountErrorsWriteVal`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_count_errors(self) -> ureg::RegRef<crate::meta::CountErrors, TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0xa8 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
     #[doc = "2 KiB packet buffer. Divided into thirty two 64-byte buffers.\n\nThe packet buffer is used for sending and receiving packets.\n\nRead value: [`u32`]; Write value: [`u32`]"]
     #[inline(always)]
     pub fn buffer(&self) -> ureg::Array<512, ureg::RegRef<crate::meta::Buffer, &TMmio>> {
@@ -399,16 +787,27 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    #[doc = "2 KiB packet buffer. Divided into thirty two 64-byte buffers.\n\nThe packet buffer is used for sending and receiving packets.\n\nRead value: [`u32`]; Write value: [`u32`]"]
+    #[doc = "This function consumes the entire register block, which is useful when transferring ownership."]
+    #[inline(always)]
+    pub fn into_buffer(self) -> ureg::Array<512, ureg::RegRef<crate::meta::Buffer, TMmio>> {
+        unsafe {
+            ureg::Array::new_with_mmio(
+                self.ptr.wrapping_add(0x800 / core::mem::size_of::<u32>()),
+                self.mmio,
+            )
+        }
+    }
 }
 pub mod regs {
     #![doc = r" Types that represent the values held by registers."]
     #[derive(Clone, Copy)]
-    pub struct AlertTestWriteVal(u32);
+    pub struct AlertTestWriteVal(pub u32);
     impl AlertTestWriteVal {
         #[doc = "Write 1 to trigger one alert event of this kind."]
         #[inline(always)]
-        pub fn fatal_fault(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 0)) | (u32::from(val) << 0))
+        pub const fn fatal_fault(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 0)) | (val as u32) << 0)
         }
     }
     impl From<u32> for AlertTestWriteVal {
@@ -424,96 +823,96 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct IntrEnableReadVal(u32);
+    pub struct IntrEnableReadVal(pub u32);
     impl IntrEnableReadVal {
         #[doc = "Enable interrupt when !!INTR_STATE.pkt_received is set."]
         #[inline(always)]
-        pub fn pkt_received(&self) -> bool {
+        pub const fn pkt_received(&self) -> bool {
             ((self.0 >> 0) & 1) != 0
         }
         #[doc = "Enable interrupt when !!INTR_STATE.pkt_sent is set."]
         #[inline(always)]
-        pub fn pkt_sent(&self) -> bool {
+        pub const fn pkt_sent(&self) -> bool {
             ((self.0 >> 1) & 1) != 0
         }
         #[doc = "Enable interrupt when !!INTR_STATE.disconnected is set."]
         #[inline(always)]
-        pub fn disconnected(&self) -> bool {
+        pub const fn disconnected(&self) -> bool {
             ((self.0 >> 2) & 1) != 0
         }
         #[doc = "Enable interrupt when !!INTR_STATE.host_lost is set."]
         #[inline(always)]
-        pub fn host_lost(&self) -> bool {
+        pub const fn host_lost(&self) -> bool {
             ((self.0 >> 3) & 1) != 0
         }
         #[doc = "Enable interrupt when !!INTR_STATE.link_reset is set."]
         #[inline(always)]
-        pub fn link_reset(&self) -> bool {
+        pub const fn link_reset(&self) -> bool {
             ((self.0 >> 4) & 1) != 0
         }
         #[doc = "Enable interrupt when !!INTR_STATE.link_suspend is set."]
         #[inline(always)]
-        pub fn link_suspend(&self) -> bool {
+        pub const fn link_suspend(&self) -> bool {
             ((self.0 >> 5) & 1) != 0
         }
         #[doc = "Enable interrupt when !!INTR_STATE.link_resume is set."]
         #[inline(always)]
-        pub fn link_resume(&self) -> bool {
+        pub const fn link_resume(&self) -> bool {
             ((self.0 >> 6) & 1) != 0
         }
         #[doc = "Enable interrupt when !!INTR_STATE.av_out_empty is set."]
         #[inline(always)]
-        pub fn av_out_empty(&self) -> bool {
+        pub const fn av_out_empty(&self) -> bool {
             ((self.0 >> 7) & 1) != 0
         }
         #[doc = "Enable interrupt when !!INTR_STATE.rx_full is set."]
         #[inline(always)]
-        pub fn rx_full(&self) -> bool {
+        pub const fn rx_full(&self) -> bool {
             ((self.0 >> 8) & 1) != 0
         }
         #[doc = "Enable interrupt when !!INTR_STATE.av_overflow is set."]
         #[inline(always)]
-        pub fn av_overflow(&self) -> bool {
+        pub const fn av_overflow(&self) -> bool {
             ((self.0 >> 9) & 1) != 0
         }
         #[doc = "Enable interrupt when !!INTR_STATE.link_in_err is set."]
         #[inline(always)]
-        pub fn link_in_err(&self) -> bool {
+        pub const fn link_in_err(&self) -> bool {
             ((self.0 >> 10) & 1) != 0
         }
         #[doc = "Enable interrupt when !!INTR_STATE.rx_crc_err is set."]
         #[inline(always)]
-        pub fn rx_crc_err(&self) -> bool {
+        pub const fn rx_crc_err(&self) -> bool {
             ((self.0 >> 11) & 1) != 0
         }
         #[doc = "Enable interrupt when !!INTR_STATE.rx_pid_err is set."]
         #[inline(always)]
-        pub fn rx_pid_err(&self) -> bool {
+        pub const fn rx_pid_err(&self) -> bool {
             ((self.0 >> 12) & 1) != 0
         }
         #[doc = "Enable interrupt when !!INTR_STATE.rx_bitstuff_err is set."]
         #[inline(always)]
-        pub fn rx_bitstuff_err(&self) -> bool {
+        pub const fn rx_bitstuff_err(&self) -> bool {
             ((self.0 >> 13) & 1) != 0
         }
         #[doc = "Enable interrupt when !!INTR_STATE.frame is set."]
         #[inline(always)]
-        pub fn frame(&self) -> bool {
+        pub const fn frame(&self) -> bool {
             ((self.0 >> 14) & 1) != 0
         }
         #[doc = "Enable interrupt when !!INTR_STATE.powered is set."]
         #[inline(always)]
-        pub fn powered(&self) -> bool {
+        pub const fn powered(&self) -> bool {
             ((self.0 >> 15) & 1) != 0
         }
         #[doc = "Enable interrupt when !!INTR_STATE.link_out_err is set."]
         #[inline(always)]
-        pub fn link_out_err(&self) -> bool {
+        pub const fn link_out_err(&self) -> bool {
             ((self.0 >> 16) & 1) != 0
         }
         #[doc = "Enable interrupt when !!INTR_STATE.av_setup_empty is set."]
         #[inline(always)]
-        pub fn av_setup_empty(&self) -> bool {
+        pub const fn av_setup_empty(&self) -> bool {
             ((self.0 >> 17) & 1) != 0
         }
         #[doc = r" Construct a WriteVal that can be used to modify the contents of this register value."]
@@ -535,97 +934,97 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct IntrEnableWriteVal(u32);
+    pub struct IntrEnableWriteVal(pub u32);
     impl IntrEnableWriteVal {
         #[doc = "Enable interrupt when !!INTR_STATE.pkt_received is set."]
         #[inline(always)]
-        pub fn pkt_received(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 0)) | (u32::from(val) << 0))
+        pub const fn pkt_received(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 0)) | (val as u32) << 0)
         }
         #[doc = "Enable interrupt when !!INTR_STATE.pkt_sent is set."]
         #[inline(always)]
-        pub fn pkt_sent(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 1)) | (u32::from(val) << 1))
+        pub const fn pkt_sent(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 1)) | (val as u32) << 1)
         }
         #[doc = "Enable interrupt when !!INTR_STATE.disconnected is set."]
         #[inline(always)]
-        pub fn disconnected(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 2)) | (u32::from(val) << 2))
+        pub const fn disconnected(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 2)) | (val as u32) << 2)
         }
         #[doc = "Enable interrupt when !!INTR_STATE.host_lost is set."]
         #[inline(always)]
-        pub fn host_lost(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 3)) | (u32::from(val) << 3))
+        pub const fn host_lost(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 3)) | (val as u32) << 3)
         }
         #[doc = "Enable interrupt when !!INTR_STATE.link_reset is set."]
         #[inline(always)]
-        pub fn link_reset(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 4)) | (u32::from(val) << 4))
+        pub const fn link_reset(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 4)) | (val as u32) << 4)
         }
         #[doc = "Enable interrupt when !!INTR_STATE.link_suspend is set."]
         #[inline(always)]
-        pub fn link_suspend(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 5)) | (u32::from(val) << 5))
+        pub const fn link_suspend(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 5)) | (val as u32) << 5)
         }
         #[doc = "Enable interrupt when !!INTR_STATE.link_resume is set."]
         #[inline(always)]
-        pub fn link_resume(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 6)) | (u32::from(val) << 6))
+        pub const fn link_resume(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 6)) | (val as u32) << 6)
         }
         #[doc = "Enable interrupt when !!INTR_STATE.av_out_empty is set."]
         #[inline(always)]
-        pub fn av_out_empty(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 7)) | (u32::from(val) << 7))
+        pub const fn av_out_empty(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 7)) | (val as u32) << 7)
         }
         #[doc = "Enable interrupt when !!INTR_STATE.rx_full is set."]
         #[inline(always)]
-        pub fn rx_full(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 8)) | (u32::from(val) << 8))
+        pub const fn rx_full(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 8)) | (val as u32) << 8)
         }
         #[doc = "Enable interrupt when !!INTR_STATE.av_overflow is set."]
         #[inline(always)]
-        pub fn av_overflow(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 9)) | (u32::from(val) << 9))
+        pub const fn av_overflow(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 9)) | (val as u32) << 9)
         }
         #[doc = "Enable interrupt when !!INTR_STATE.link_in_err is set."]
         #[inline(always)]
-        pub fn link_in_err(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 10)) | (u32::from(val) << 10))
+        pub const fn link_in_err(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 10)) | (val as u32) << 10)
         }
         #[doc = "Enable interrupt when !!INTR_STATE.rx_crc_err is set."]
         #[inline(always)]
-        pub fn rx_crc_err(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 11)) | (u32::from(val) << 11))
+        pub const fn rx_crc_err(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 11)) | (val as u32) << 11)
         }
         #[doc = "Enable interrupt when !!INTR_STATE.rx_pid_err is set."]
         #[inline(always)]
-        pub fn rx_pid_err(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 12)) | (u32::from(val) << 12))
+        pub const fn rx_pid_err(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 12)) | (val as u32) << 12)
         }
         #[doc = "Enable interrupt when !!INTR_STATE.rx_bitstuff_err is set."]
         #[inline(always)]
-        pub fn rx_bitstuff_err(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 13)) | (u32::from(val) << 13))
+        pub const fn rx_bitstuff_err(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 13)) | (val as u32) << 13)
         }
         #[doc = "Enable interrupt when !!INTR_STATE.frame is set."]
         #[inline(always)]
-        pub fn frame(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 14)) | (u32::from(val) << 14))
+        pub const fn frame(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 14)) | (val as u32) << 14)
         }
         #[doc = "Enable interrupt when !!INTR_STATE.powered is set."]
         #[inline(always)]
-        pub fn powered(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 15)) | (u32::from(val) << 15))
+        pub const fn powered(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 15)) | (val as u32) << 15)
         }
         #[doc = "Enable interrupt when !!INTR_STATE.link_out_err is set."]
         #[inline(always)]
-        pub fn link_out_err(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 16)) | (u32::from(val) << 16))
+        pub const fn link_out_err(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 16)) | (val as u32) << 16)
         }
         #[doc = "Enable interrupt when !!INTR_STATE.av_setup_empty is set."]
         #[inline(always)]
-        pub fn av_setup_empty(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 17)) | (u32::from(val) << 17))
+        pub const fn av_setup_empty(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 17)) | (val as u32) << 17)
         }
     }
     impl From<u32> for IntrEnableWriteVal {
@@ -641,96 +1040,96 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct IntrStateReadVal(u32);
+    pub struct IntrStateReadVal(pub u32);
     impl IntrStateReadVal {
         #[doc = "Raised if a packet was received using an OUT or SETUP transaction.\nThis interrupt is directly tied to whether the RX FIFO is empty, so it should be cleared only after handling the FIFO entry."]
         #[inline(always)]
-        pub fn pkt_received(&self) -> bool {
+        pub const fn pkt_received(&self) -> bool {
             ((self.0 >> 0) & 1) != 0
         }
         #[doc = "Raised if a packet was sent as part of an IN transaction.\nThis interrupt is directly tied to whether a sent packet has not been acknowledged in the !!in_sent register.\nIt should be cleared only after clearing all bits in the !!in_sent register."]
         #[inline(always)]
-        pub fn pkt_sent(&self) -> bool {
+        pub const fn pkt_sent(&self) -> bool {
             ((self.0 >> 1) & 1) != 0
         }
         #[doc = "Raised if VBUS is lost, thus the link is disconnected."]
         #[inline(always)]
-        pub fn disconnected(&self) -> bool {
+        pub const fn disconnected(&self) -> bool {
             ((self.0 >> 2) & 1) != 0
         }
         #[doc = "Raised if link is active but SOF was not received from host for 4.096 ms. The SOF should be every 1 ms."]
         #[inline(always)]
-        pub fn host_lost(&self) -> bool {
+        pub const fn host_lost(&self) -> bool {
             ((self.0 >> 3) & 1) != 0
         }
         #[doc = "Raised if the link is at SE0 longer than 3 us indicating a link reset (host asserts for min 10 ms, device can react after 2.5 us)."]
         #[inline(always)]
-        pub fn link_reset(&self) -> bool {
+        pub const fn link_reset(&self) -> bool {
             ((self.0 >> 4) & 1) != 0
         }
         #[doc = "Raised if the line has signaled J for longer than 3ms and is therefore in suspend state."]
         #[inline(always)]
-        pub fn link_suspend(&self) -> bool {
+        pub const fn link_suspend(&self) -> bool {
             ((self.0 >> 5) & 1) != 0
         }
         #[doc = "Raised when the link becomes active again after being suspended."]
         #[inline(always)]
-        pub fn link_resume(&self) -> bool {
+        pub const fn link_resume(&self) -> bool {
             ((self.0 >> 6) & 1) != 0
         }
         #[doc = "Raised when the Available OUT Buffer FIFO is empty and the device interface is enabled.\nThis interrupt is directly tied to the FIFO status, so the Available OUT Buffer FIFO must be provided with a free buffer before the interrupt can be cleared."]
         #[inline(always)]
-        pub fn av_out_empty(&self) -> bool {
+        pub const fn av_out_empty(&self) -> bool {
             ((self.0 >> 7) & 1) != 0
         }
         #[doc = "Raised when the RX FIFO is full and the device interface is enabled.\nThis interrupt is directly tied to the FIFO status, so the RX FIFO must have an entry removed before the interrupt is cleared.\nIf the condition is not cleared, the interrupt can re-assert."]
         #[inline(always)]
-        pub fn rx_full(&self) -> bool {
+        pub const fn rx_full(&self) -> bool {
             ((self.0 >> 8) & 1) != 0
         }
         #[doc = "Raised if a write was done to either the Available OUT Buffer FIFO or the Available SETUP Buffer FIFO when the FIFO was full."]
         #[inline(always)]
-        pub fn av_overflow(&self) -> bool {
+        pub const fn av_overflow(&self) -> bool {
             ((self.0 >> 9) & 1) != 0
         }
         #[doc = "Raised if a packet to an IN endpoint started to be received but was\nthen dropped due to an error. After transmitting the IN payload,\nthe USB device expects a valid ACK handshake packet. This error is\nraised if either the packet or CRC is invalid, leading to a NAK instead,\nor if a different token was received."]
         #[inline(always)]
-        pub fn link_in_err(&self) -> bool {
+        pub const fn link_in_err(&self) -> bool {
             ((self.0 >> 10) & 1) != 0
         }
         #[doc = "Raised if a CRC error occurred on a received packet."]
         #[inline(always)]
-        pub fn rx_crc_err(&self) -> bool {
+        pub const fn rx_crc_err(&self) -> bool {
             ((self.0 >> 11) & 1) != 0
         }
         #[doc = "Raised if an invalid Packet IDentifier (PID) was received."]
         #[inline(always)]
-        pub fn rx_pid_err(&self) -> bool {
+        pub const fn rx_pid_err(&self) -> bool {
             ((self.0 >> 12) & 1) != 0
         }
         #[doc = "Raised if an invalid bitstuffing was received."]
         #[inline(always)]
-        pub fn rx_bitstuff_err(&self) -> bool {
+        pub const fn rx_bitstuff_err(&self) -> bool {
             ((self.0 >> 13) & 1) != 0
         }
         #[doc = "Raised when the USB frame number is updated with a valid SOF."]
         #[inline(always)]
-        pub fn frame(&self) -> bool {
+        pub const fn frame(&self) -> bool {
             ((self.0 >> 14) & 1) != 0
         }
         #[doc = "Raised if VBUS is applied."]
         #[inline(always)]
-        pub fn powered(&self) -> bool {
+        pub const fn powered(&self) -> bool {
             ((self.0 >> 15) & 1) != 0
         }
         #[doc = "Raised if a packet to an OUT endpoint started to be received but was then dropped due to an error.\nThis error is raised if the data toggle, token, packet and/or CRC are invalid, or if the appropriate Available OUT Buffer FIFO is empty and/or the Received Buffer FIFO is full when a packet should have been received."]
         #[inline(always)]
-        pub fn link_out_err(&self) -> bool {
+        pub const fn link_out_err(&self) -> bool {
             ((self.0 >> 16) & 1) != 0
         }
         #[doc = "Raised when the Available SETUP Buffer FIFO is empty and the device interface is enabled.\nThis interrupt is directly tied to the FIFO status, so the Available SETUP Buffer FIFO must be provided with a free buffer before the interrupt can be cleared."]
         #[inline(always)]
-        pub fn av_setup_empty(&self) -> bool {
+        pub const fn av_setup_empty(&self) -> bool {
             ((self.0 >> 17) & 1) != 0
         }
         #[doc = r" Construct a WriteVal that can be used to modify the contents of this register value."]
@@ -752,71 +1151,71 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct IntrStateWriteVal(u32);
+    pub struct IntrStateWriteVal(pub u32);
     impl IntrStateWriteVal {
         #[doc = "Raised if VBUS is lost, thus the link is disconnected."]
         #[inline(always)]
-        pub fn disconnected_clear(self) -> Self {
+        pub const fn disconnected_clear(self) -> Self {
             Self(self.0 | (1 << 2))
         }
         #[doc = "Raised if link is active but SOF was not received from host for 4.096 ms. The SOF should be every 1 ms."]
         #[inline(always)]
-        pub fn host_lost_clear(self) -> Self {
+        pub const fn host_lost_clear(self) -> Self {
             Self(self.0 | (1 << 3))
         }
         #[doc = "Raised if the link is at SE0 longer than 3 us indicating a link reset (host asserts for min 10 ms, device can react after 2.5 us)."]
         #[inline(always)]
-        pub fn link_reset_clear(self) -> Self {
+        pub const fn link_reset_clear(self) -> Self {
             Self(self.0 | (1 << 4))
         }
         #[doc = "Raised if the line has signaled J for longer than 3ms and is therefore in suspend state."]
         #[inline(always)]
-        pub fn link_suspend_clear(self) -> Self {
+        pub const fn link_suspend_clear(self) -> Self {
             Self(self.0 | (1 << 5))
         }
         #[doc = "Raised when the link becomes active again after being suspended."]
         #[inline(always)]
-        pub fn link_resume_clear(self) -> Self {
+        pub const fn link_resume_clear(self) -> Self {
             Self(self.0 | (1 << 6))
         }
         #[doc = "Raised if a write was done to either the Available OUT Buffer FIFO or the Available SETUP Buffer FIFO when the FIFO was full."]
         #[inline(always)]
-        pub fn av_overflow_clear(self) -> Self {
+        pub const fn av_overflow_clear(self) -> Self {
             Self(self.0 | (1 << 9))
         }
         #[doc = "Raised if a packet to an IN endpoint started to be received but was\nthen dropped due to an error. After transmitting the IN payload,\nthe USB device expects a valid ACK handshake packet. This error is\nraised if either the packet or CRC is invalid, leading to a NAK instead,\nor if a different token was received."]
         #[inline(always)]
-        pub fn link_in_err_clear(self) -> Self {
+        pub const fn link_in_err_clear(self) -> Self {
             Self(self.0 | (1 << 10))
         }
         #[doc = "Raised if a CRC error occurred on a received packet."]
         #[inline(always)]
-        pub fn rx_crc_err_clear(self) -> Self {
+        pub const fn rx_crc_err_clear(self) -> Self {
             Self(self.0 | (1 << 11))
         }
         #[doc = "Raised if an invalid Packet IDentifier (PID) was received."]
         #[inline(always)]
-        pub fn rx_pid_err_clear(self) -> Self {
+        pub const fn rx_pid_err_clear(self) -> Self {
             Self(self.0 | (1 << 12))
         }
         #[doc = "Raised if an invalid bitstuffing was received."]
         #[inline(always)]
-        pub fn rx_bitstuff_err_clear(self) -> Self {
+        pub const fn rx_bitstuff_err_clear(self) -> Self {
             Self(self.0 | (1 << 13))
         }
         #[doc = "Raised when the USB frame number is updated with a valid SOF."]
         #[inline(always)]
-        pub fn frame_clear(self) -> Self {
+        pub const fn frame_clear(self) -> Self {
             Self(self.0 | (1 << 14))
         }
         #[doc = "Raised if VBUS is applied."]
         #[inline(always)]
-        pub fn powered_clear(self) -> Self {
+        pub const fn powered_clear(self) -> Self {
             Self(self.0 | (1 << 15))
         }
         #[doc = "Raised if a packet to an OUT endpoint started to be received but was then dropped due to an error.\nThis error is raised if the data toggle, token, packet and/or CRC are invalid, or if the appropriate Available OUT Buffer FIFO is empty and/or the Received Buffer FIFO is full when a packet should have been received."]
         #[inline(always)]
-        pub fn link_out_err_clear(self) -> Self {
+        pub const fn link_out_err_clear(self) -> Self {
             Self(self.0 | (1 << 16))
         }
     }
@@ -833,97 +1232,97 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct IntrTestWriteVal(u32);
+    pub struct IntrTestWriteVal(pub u32);
     impl IntrTestWriteVal {
         #[doc = "Write 1 to force !!INTR_STATE.pkt_received to 1."]
         #[inline(always)]
-        pub fn pkt_received(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 0)) | (u32::from(val) << 0))
+        pub const fn pkt_received(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 0)) | (val as u32) << 0)
         }
         #[doc = "Write 1 to force !!INTR_STATE.pkt_sent to 1."]
         #[inline(always)]
-        pub fn pkt_sent(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 1)) | (u32::from(val) << 1))
+        pub const fn pkt_sent(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 1)) | (val as u32) << 1)
         }
         #[doc = "Write 1 to force !!INTR_STATE.disconnected to 1."]
         #[inline(always)]
-        pub fn disconnected(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 2)) | (u32::from(val) << 2))
+        pub const fn disconnected(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 2)) | (val as u32) << 2)
         }
         #[doc = "Write 1 to force !!INTR_STATE.host_lost to 1."]
         #[inline(always)]
-        pub fn host_lost(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 3)) | (u32::from(val) << 3))
+        pub const fn host_lost(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 3)) | (val as u32) << 3)
         }
         #[doc = "Write 1 to force !!INTR_STATE.link_reset to 1."]
         #[inline(always)]
-        pub fn link_reset(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 4)) | (u32::from(val) << 4))
+        pub const fn link_reset(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 4)) | (val as u32) << 4)
         }
         #[doc = "Write 1 to force !!INTR_STATE.link_suspend to 1."]
         #[inline(always)]
-        pub fn link_suspend(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 5)) | (u32::from(val) << 5))
+        pub const fn link_suspend(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 5)) | (val as u32) << 5)
         }
         #[doc = "Write 1 to force !!INTR_STATE.link_resume to 1."]
         #[inline(always)]
-        pub fn link_resume(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 6)) | (u32::from(val) << 6))
+        pub const fn link_resume(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 6)) | (val as u32) << 6)
         }
         #[doc = "Write 1 to force !!INTR_STATE.av_out_empty to 1."]
         #[inline(always)]
-        pub fn av_out_empty(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 7)) | (u32::from(val) << 7))
+        pub const fn av_out_empty(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 7)) | (val as u32) << 7)
         }
         #[doc = "Write 1 to force !!INTR_STATE.rx_full to 1."]
         #[inline(always)]
-        pub fn rx_full(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 8)) | (u32::from(val) << 8))
+        pub const fn rx_full(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 8)) | (val as u32) << 8)
         }
         #[doc = "Write 1 to force !!INTR_STATE.av_overflow to 1."]
         #[inline(always)]
-        pub fn av_overflow(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 9)) | (u32::from(val) << 9))
+        pub const fn av_overflow(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 9)) | (val as u32) << 9)
         }
         #[doc = "Write 1 to force !!INTR_STATE.link_in_err to 1."]
         #[inline(always)]
-        pub fn link_in_err(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 10)) | (u32::from(val) << 10))
+        pub const fn link_in_err(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 10)) | (val as u32) << 10)
         }
         #[doc = "Write 1 to force !!INTR_STATE.rx_crc_err to 1."]
         #[inline(always)]
-        pub fn rx_crc_err(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 11)) | (u32::from(val) << 11))
+        pub const fn rx_crc_err(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 11)) | (val as u32) << 11)
         }
         #[doc = "Write 1 to force !!INTR_STATE.rx_pid_err to 1."]
         #[inline(always)]
-        pub fn rx_pid_err(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 12)) | (u32::from(val) << 12))
+        pub const fn rx_pid_err(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 12)) | (val as u32) << 12)
         }
         #[doc = "Write 1 to force !!INTR_STATE.rx_bitstuff_err to 1."]
         #[inline(always)]
-        pub fn rx_bitstuff_err(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 13)) | (u32::from(val) << 13))
+        pub const fn rx_bitstuff_err(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 13)) | (val as u32) << 13)
         }
         #[doc = "Write 1 to force !!INTR_STATE.frame to 1."]
         #[inline(always)]
-        pub fn frame(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 14)) | (u32::from(val) << 14))
+        pub const fn frame(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 14)) | (val as u32) << 14)
         }
         #[doc = "Write 1 to force !!INTR_STATE.powered to 1."]
         #[inline(always)]
-        pub fn powered(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 15)) | (u32::from(val) << 15))
+        pub const fn powered(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 15)) | (val as u32) << 15)
         }
         #[doc = "Write 1 to force !!INTR_STATE.link_out_err to 1."]
         #[inline(always)]
-        pub fn link_out_err(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 16)) | (u32::from(val) << 16))
+        pub const fn link_out_err(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 16)) | (val as u32) << 16)
         }
         #[doc = "Write 1 to force !!INTR_STATE.av_setup_empty to 1."]
         #[inline(always)]
-        pub fn av_setup_empty(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 17)) | (u32::from(val) << 17))
+        pub const fn av_setup_empty(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 17)) | (val as u32) << 17)
         }
     }
     impl From<u32> for IntrTestWriteVal {
@@ -939,11 +1338,11 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct AvoutbufferWriteVal(u32);
+    pub struct AvoutbufferWriteVal(pub u32);
     impl AvoutbufferWriteVal {
         #[doc = "This field contains the buffer ID being passed to the USB receive engine.\n\nIf the Available OUT Buffer FIFO is full, any write operations are discarded."]
         #[inline(always)]
-        pub fn buffer(self, val: u32) -> Self {
+        pub const fn buffer(self, val: u32) -> Self {
             Self((self.0 & !(0x1f << 0)) | ((val & 0x1f) << 0))
         }
     }
@@ -960,11 +1359,11 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct AvsetupbufferWriteVal(u32);
+    pub struct AvsetupbufferWriteVal(pub u32);
     impl AvsetupbufferWriteVal {
         #[doc = "This field contains the buffer ID being passed to the USB receive engine.\n\nIf the Available SETUP Buffer FIFO is full, any write operations are discarded."]
         #[inline(always)]
-        pub fn buffer(self, val: u32) -> Self {
+        pub const fn buffer(self, val: u32) -> Self {
             Self((self.0 & !(0x1f << 0)) | ((val & 0x1f) << 0))
         }
     }
@@ -981,31 +1380,31 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct ConfiginReadVal(u32);
+    pub struct ConfiginReadVal(pub u32);
     impl ConfiginReadVal {
         #[doc = "The buffer ID containing the data to send when an IN transaction is received on the endpoint."]
         #[inline(always)]
-        pub fn buffer(&self) -> u32 {
+        pub const fn buffer(&self) -> u32 {
             (self.0 >> 0) & 0x1f
         }
         #[doc = "The number of bytes to send from the buffer.\n\nIf this is 0 then a CRC only packet is sent.\n\nIf this is greater than 64 then 64 bytes are sent."]
         #[inline(always)]
-        pub fn size(&self) -> u32 {
+        pub const fn size(&self) -> u32 {
             (self.0 >> 8) & 0x7f
         }
         #[doc = "This bit indicates that the buffer is in the process of being collected by the\nhost. It becomes set upon the first attempt by the host to collect a buffer from\nthis endpoint when the rdy bit was set.\n\nIt is cleared when the packet has been collected successfully or the pending\ntransaction has been canceled by the hardware through detection of a\nlink reset or receipt of a SETUP packet."]
         #[inline(always)]
-        pub fn sending(&self) -> bool {
+        pub const fn sending(&self) -> bool {
             ((self.0 >> 29) & 1) != 0
         }
         #[doc = "This bit indicates a pending transaction was canceled by the hardware.\n\nThe bit is set when the rdy bit is cleared by hardware because of a\nSETUP packet being received or a link reset being detected.\n\nThe bit remains set until cleared by being written with a 1."]
         #[inline(always)]
-        pub fn pend(&self) -> bool {
+        pub const fn pend(&self) -> bool {
             ((self.0 >> 30) & 1) != 0
         }
         #[doc = "This bit should be set to indicate the buffer is ready for sending.\nIt will be cleared when the ACK is received indicating the host has accepted the data.\n\nThis bit will also be cleared if an enabled SETUP transaction is received on the endpoint.\nThis allows use of the IN channel for transfer of SETUP information.\nThe original buffer must be resubmitted after the SETUP sequence is complete.\nA link reset also clears the bit.\nIn either of the cases where the hardware cancels the transaction it will also set the pend bit."]
         #[inline(always)]
-        pub fn rdy(&self) -> bool {
+        pub const fn rdy(&self) -> bool {
             ((self.0 >> 31) & 1) != 0
         }
         #[doc = r" Construct a WriteVal that can be used to modify the contents of this register value."]
@@ -1027,32 +1426,32 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct ConfiginWriteVal(u32);
+    pub struct ConfiginWriteVal(pub u32);
     impl ConfiginWriteVal {
         #[doc = "The buffer ID containing the data to send when an IN transaction is received on the endpoint."]
         #[inline(always)]
-        pub fn buffer(self, val: u32) -> Self {
+        pub const fn buffer(self, val: u32) -> Self {
             Self((self.0 & !(0x1f << 0)) | ((val & 0x1f) << 0))
         }
         #[doc = "The number of bytes to send from the buffer.\n\nIf this is 0 then a CRC only packet is sent.\n\nIf this is greater than 64 then 64 bytes are sent."]
         #[inline(always)]
-        pub fn size(self, val: u32) -> Self {
+        pub const fn size(self, val: u32) -> Self {
             Self((self.0 & !(0x7f << 8)) | ((val & 0x7f) << 8))
         }
         #[doc = "This bit indicates that the buffer is in the process of being collected by the\nhost. It becomes set upon the first attempt by the host to collect a buffer from\nthis endpoint when the rdy bit was set.\n\nIt is cleared when the packet has been collected successfully or the pending\ntransaction has been canceled by the hardware through detection of a\nlink reset or receipt of a SETUP packet."]
         #[inline(always)]
-        pub fn sending_clear(self) -> Self {
+        pub const fn sending_clear(self) -> Self {
             Self(self.0 | (1 << 29))
         }
         #[doc = "This bit indicates a pending transaction was canceled by the hardware.\n\nThe bit is set when the rdy bit is cleared by hardware because of a\nSETUP packet being received or a link reset being detected.\n\nThe bit remains set until cleared by being written with a 1."]
         #[inline(always)]
-        pub fn pend_clear(self) -> Self {
+        pub const fn pend_clear(self) -> Self {
             Self(self.0 | (1 << 30))
         }
         #[doc = "This bit should be set to indicate the buffer is ready for sending.\nIt will be cleared when the ACK is received indicating the host has accepted the data.\n\nThis bit will also be cleared if an enabled SETUP transaction is received on the endpoint.\nThis allows use of the IN channel for transfer of SETUP information.\nThe original buffer must be resubmitted after the SETUP sequence is complete.\nA link reset also clears the bit.\nIn either of the cases where the hardware cancels the transaction it will also set the pend bit."]
         #[inline(always)]
-        pub fn rdy(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 31)) | (u32::from(val) << 31))
+        pub const fn rdy(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 31)) | (val as u32) << 31)
         }
     }
     impl From<u32> for ConfiginWriteVal {
@@ -1068,31 +1467,31 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct CountErrorsReadVal(u32);
+    pub struct CountErrorsReadVal(pub u32);
     impl CountErrorsReadVal {
         #[doc = "Number of events counted."]
         #[inline(always)]
-        pub fn count(&self) -> u32 {
+        pub const fn count(&self) -> u32 {
             (self.0 >> 0) & 0xff
         }
         #[doc = "Number of Invalid PIDs detected on packets from the host. Invalid PIDs may\nindicate very unreliable communication and/or a substantial frequency mismatch\nbetween the host and the device."]
         #[inline(always)]
-        pub fn pid_invalid(&self) -> bool {
+        pub const fn pid_invalid(&self) -> bool {
             ((self.0 >> 27) & 1) != 0
         }
         #[doc = "Number of SETUP/OUT packets that were ignored, dropped or NAKed because a\nBit Stuffing error was detected."]
         #[inline(always)]
-        pub fn bitstuff(&self) -> bool {
+        pub const fn bitstuff(&self) -> bool {
             ((self.0 >> 28) & 1) != 0
         }
         #[doc = "Count SETUP/OUT DATA packets that were ignored, dropped or NAKed because a\nCRC16 error was detected."]
         #[inline(always)]
-        pub fn crc16(&self) -> bool {
+        pub const fn crc16(&self) -> bool {
             ((self.0 >> 29) & 1) != 0
         }
         #[doc = "Count CRC5 errors detected on token packets sent by the host. CRC5 errors on\ntoken packets received from the host indicate very unreliable communication and\npossibly a substantial frequency mismatch between the host and the device."]
         #[inline(always)]
-        pub fn crc5(&self) -> bool {
+        pub const fn crc5(&self) -> bool {
             ((self.0 >> 30) & 1) != 0
         }
         #[doc = r" Construct a WriteVal that can be used to modify the contents of this register value."]
@@ -1114,32 +1513,32 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct CountErrorsWriteVal(u32);
+    pub struct CountErrorsWriteVal(pub u32);
     impl CountErrorsWriteVal {
         #[doc = "Number of Invalid PIDs detected on packets from the host. Invalid PIDs may\nindicate very unreliable communication and/or a substantial frequency mismatch\nbetween the host and the device."]
         #[inline(always)]
-        pub fn pid_invalid(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 27)) | (u32::from(val) << 27))
+        pub const fn pid_invalid(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 27)) | (val as u32) << 27)
         }
         #[doc = "Number of SETUP/OUT packets that were ignored, dropped or NAKed because a\nBit Stuffing error was detected."]
         #[inline(always)]
-        pub fn bitstuff(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 28)) | (u32::from(val) << 28))
+        pub const fn bitstuff(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 28)) | (val as u32) << 28)
         }
         #[doc = "Count SETUP/OUT DATA packets that were ignored, dropped or NAKed because a\nCRC16 error was detected."]
         #[inline(always)]
-        pub fn crc16(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 29)) | (u32::from(val) << 29))
+        pub const fn crc16(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 29)) | (val as u32) << 29)
         }
         #[doc = "Count CRC5 errors detected on token packets sent by the host. CRC5 errors on\ntoken packets received from the host indicate very unreliable communication and\npossibly a substantial frequency mismatch between the host and the device."]
         #[inline(always)]
-        pub fn crc5(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 30)) | (u32::from(val) << 30))
+        pub const fn crc5(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 30)) | (val as u32) << 30)
         }
         #[doc = "Write 1 to reset the counter."]
         #[inline(always)]
-        pub fn rst(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 31)) | (u32::from(val) << 31))
+        pub const fn rst(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 31)) | (val as u32) << 31)
         }
     }
     impl From<u32> for CountErrorsWriteVal {
@@ -1155,31 +1554,31 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct CountInReadVal(u32);
+    pub struct CountInReadVal(pub u32);
     impl CountInReadVal {
         #[doc = "Number of events counted."]
         #[inline(always)]
-        pub fn count(&self) -> u32 {
+        pub const fn count(&self) -> u32 {
             (self.0 >> 0) & 0xff
         }
         #[doc = "Count the IN transactions that were attempted when there was no packet available\nin the corresponding 'configin' register(s). This is not necessarily an error\ncondition, and the counter primarily offers some visibility into when the IN\ntraffic is underusing the available bus bandwidth.\nIt is of particular utility to Isochronous IN endpoints."]
         #[inline(always)]
-        pub fn nodata(&self) -> bool {
+        pub const fn nodata(&self) -> bool {
             ((self.0 >> 13) & 1) != 0
         }
         #[doc = "Count the IN transactions rejected by the host responding with a NAK handshake."]
         #[inline(always)]
-        pub fn nak(&self) -> bool {
+        pub const fn nak(&self) -> bool {
             ((self.0 >> 14) & 1) != 0
         }
         #[doc = "Count the IN transactions for which the USB host did not respond with a handshake,\nand the transactions timed out. This indicates that the host did not receive it\nand decode it as a valid packet, suggesting that communication is unreliable.\n\nIsochronous IN transactions are excluded from this count because there is no\nhandshake response to Isochronous packet transfers."]
         #[inline(always)]
-        pub fn timeout(&self) -> bool {
+        pub const fn timeout(&self) -> bool {
             ((self.0 >> 15) & 1) != 0
         }
         #[doc = "Set of endpoints for which this counter is enabled."]
         #[inline(always)]
-        pub fn endpoints(&self) -> u32 {
+        pub const fn endpoints(&self) -> u32 {
             (self.0 >> 16) & 0xfff
         }
         #[doc = r" Construct a WriteVal that can be used to modify the contents of this register value."]
@@ -1201,32 +1600,32 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct CountInWriteVal(u32);
+    pub struct CountInWriteVal(pub u32);
     impl CountInWriteVal {
         #[doc = "Count the IN transactions that were attempted when there was no packet available\nin the corresponding 'configin' register(s). This is not necessarily an error\ncondition, and the counter primarily offers some visibility into when the IN\ntraffic is underusing the available bus bandwidth.\nIt is of particular utility to Isochronous IN endpoints."]
         #[inline(always)]
-        pub fn nodata(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 13)) | (u32::from(val) << 13))
+        pub const fn nodata(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 13)) | (val as u32) << 13)
         }
         #[doc = "Count the IN transactions rejected by the host responding with a NAK handshake."]
         #[inline(always)]
-        pub fn nak(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 14)) | (u32::from(val) << 14))
+        pub const fn nak(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 14)) | (val as u32) << 14)
         }
         #[doc = "Count the IN transactions for which the USB host did not respond with a handshake,\nand the transactions timed out. This indicates that the host did not receive it\nand decode it as a valid packet, suggesting that communication is unreliable.\n\nIsochronous IN transactions are excluded from this count because there is no\nhandshake response to Isochronous packet transfers."]
         #[inline(always)]
-        pub fn timeout(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 15)) | (u32::from(val) << 15))
+        pub const fn timeout(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 15)) | (val as u32) << 15)
         }
         #[doc = "Set of endpoints for which this counter is enabled."]
         #[inline(always)]
-        pub fn endpoints(self, val: u32) -> Self {
+        pub const fn endpoints(self, val: u32) -> Self {
             Self((self.0 & !(0xfff << 16)) | ((val & 0xfff) << 16))
         }
         #[doc = "Write 1 to reset the counter."]
         #[inline(always)]
-        pub fn rst(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 31)) | (u32::from(val) << 31))
+        pub const fn rst(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 31)) | (val as u32) << 31)
         }
     }
     impl From<u32> for CountInWriteVal {
@@ -1242,16 +1641,16 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct CountNodataInReadVal(u32);
+    pub struct CountNodataInReadVal(pub u32);
     impl CountNodataInReadVal {
         #[doc = "Number of IN transactions that were attempted when there was no packet available\nin the corresponding 'configin' register(s)."]
         #[inline(always)]
-        pub fn count(&self) -> u32 {
+        pub const fn count(&self) -> u32 {
             (self.0 >> 0) & 0xff
         }
         #[doc = "Set of endpoints for which this counter is enabled."]
         #[inline(always)]
-        pub fn endpoints(&self) -> u32 {
+        pub const fn endpoints(&self) -> u32 {
             (self.0 >> 16) & 0xfff
         }
         #[doc = r" Construct a WriteVal that can be used to modify the contents of this register value."]
@@ -1273,17 +1672,17 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct CountNodataInWriteVal(u32);
+    pub struct CountNodataInWriteVal(pub u32);
     impl CountNodataInWriteVal {
         #[doc = "Set of endpoints for which this counter is enabled."]
         #[inline(always)]
-        pub fn endpoints(self, val: u32) -> Self {
+        pub const fn endpoints(self, val: u32) -> Self {
             Self((self.0 & !(0xfff << 16)) | ((val & 0xfff) << 16))
         }
         #[doc = "Write 1 to reset the counter."]
         #[inline(always)]
-        pub fn rst(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 31)) | (u32::from(val) << 31))
+        pub const fn rst(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 31)) | (val as u32) << 31)
         }
     }
     impl From<u32> for CountNodataInWriteVal {
@@ -1299,36 +1698,36 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct CountOutReadVal(u32);
+    pub struct CountOutReadVal(pub u32);
     impl CountOutReadVal {
         #[doc = "Number of events counted."]
         #[inline(always)]
-        pub fn count(&self) -> u32 {
+        pub const fn count(&self) -> u32 {
             (self.0 >> 0) & 0xff
         }
         #[doc = "Count the OUT transactions for which the USB device acknowledged the OUT packet\nand dropped it internally, which is the correct response to a packet transmitted\nwith an incorrect Data Toggle.\n\nThe expectation is that this packet is a retry of the previous packet transmission\nand that the handshake response was not received intact by the USB host, indicating\nunreliable communications.\n\nOther causes of Data Toggle synchronization failure may result in data loss."]
         #[inline(always)]
-        pub fn datatog_out(&self) -> bool {
+        pub const fn datatog_out(&self) -> bool {
             ((self.0 >> 12) & 1) != 0
         }
         #[doc = "Count the SETUP/OUT packets ignored, dropped or NAKed because the RX FIFO was full.\nSETUP packets have been ignored, Isochronous OUT packets have been dropped, and\nnon-Isochronous OUT packets have been NAKed."]
         #[inline(always)]
-        pub fn drop_rx(&self) -> bool {
+        pub const fn drop_rx(&self) -> bool {
             ((self.0 >> 13) & 1) != 0
         }
         #[doc = "Count the OUT packets that could not be accepted because there was no buffer in the\nAv OUT FIFO. Non-Isochronous OUT packets have been NAKed.\nIsochronous OUT packets were ignored."]
         #[inline(always)]
-        pub fn drop_avout(&self) -> bool {
+        pub const fn drop_avout(&self) -> bool {
             ((self.0 >> 14) & 1) != 0
         }
         #[doc = "Count the SETUP packets that were ignored because there was no buffer in the\nAv SETUP FIFO."]
         #[inline(always)]
-        pub fn ign_avsetup(&self) -> bool {
+        pub const fn ign_avsetup(&self) -> bool {
             ((self.0 >> 15) & 1) != 0
         }
         #[doc = "Set of OUT endpoints for which this counter is enabled."]
         #[inline(always)]
-        pub fn endpoints(&self) -> u32 {
+        pub const fn endpoints(&self) -> u32 {
             (self.0 >> 16) & 0xfff
         }
         #[doc = r" Construct a WriteVal that can be used to modify the contents of this register value."]
@@ -1350,37 +1749,37 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct CountOutWriteVal(u32);
+    pub struct CountOutWriteVal(pub u32);
     impl CountOutWriteVal {
         #[doc = "Count the OUT transactions for which the USB device acknowledged the OUT packet\nand dropped it internally, which is the correct response to a packet transmitted\nwith an incorrect Data Toggle.\n\nThe expectation is that this packet is a retry of the previous packet transmission\nand that the handshake response was not received intact by the USB host, indicating\nunreliable communications.\n\nOther causes of Data Toggle synchronization failure may result in data loss."]
         #[inline(always)]
-        pub fn datatog_out(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 12)) | (u32::from(val) << 12))
+        pub const fn datatog_out(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 12)) | (val as u32) << 12)
         }
         #[doc = "Count the SETUP/OUT packets ignored, dropped or NAKed because the RX FIFO was full.\nSETUP packets have been ignored, Isochronous OUT packets have been dropped, and\nnon-Isochronous OUT packets have been NAKed."]
         #[inline(always)]
-        pub fn drop_rx(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 13)) | (u32::from(val) << 13))
+        pub const fn drop_rx(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 13)) | (val as u32) << 13)
         }
         #[doc = "Count the OUT packets that could not be accepted because there was no buffer in the\nAv OUT FIFO. Non-Isochronous OUT packets have been NAKed.\nIsochronous OUT packets were ignored."]
         #[inline(always)]
-        pub fn drop_avout(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 14)) | (u32::from(val) << 14))
+        pub const fn drop_avout(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 14)) | (val as u32) << 14)
         }
         #[doc = "Count the SETUP packets that were ignored because there was no buffer in the\nAv SETUP FIFO."]
         #[inline(always)]
-        pub fn ign_avsetup(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 15)) | (u32::from(val) << 15))
+        pub const fn ign_avsetup(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 15)) | (val as u32) << 15)
         }
         #[doc = "Set of OUT endpoints for which this counter is enabled."]
         #[inline(always)]
-        pub fn endpoints(self, val: u32) -> Self {
+        pub const fn endpoints(self, val: u32) -> Self {
             Self((self.0 & !(0xfff << 16)) | ((val & 0xfff) << 16))
         }
         #[doc = "Write 1 to reset the counter."]
         #[inline(always)]
-        pub fn rst(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 31)) | (u32::from(val) << 31))
+        pub const fn rst(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 31)) | (val as u32) << 31)
         }
     }
     impl From<u32> for CountOutWriteVal {
@@ -1396,66 +1795,66 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct EpInEnable0ReadVal(u32);
+    pub struct EpInEnable0ReadVal(pub u32);
     impl EpInEnable0ReadVal {
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable0(&self) -> bool {
+        pub const fn enable0(&self) -> bool {
             ((self.0 >> 0) & 1) != 0
         }
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable1(&self) -> bool {
+        pub const fn enable1(&self) -> bool {
             ((self.0 >> 1) & 1) != 0
         }
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable2(&self) -> bool {
+        pub const fn enable2(&self) -> bool {
             ((self.0 >> 2) & 1) != 0
         }
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable3(&self) -> bool {
+        pub const fn enable3(&self) -> bool {
             ((self.0 >> 3) & 1) != 0
         }
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable4(&self) -> bool {
+        pub const fn enable4(&self) -> bool {
             ((self.0 >> 4) & 1) != 0
         }
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable5(&self) -> bool {
+        pub const fn enable5(&self) -> bool {
             ((self.0 >> 5) & 1) != 0
         }
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable6(&self) -> bool {
+        pub const fn enable6(&self) -> bool {
             ((self.0 >> 6) & 1) != 0
         }
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable7(&self) -> bool {
+        pub const fn enable7(&self) -> bool {
             ((self.0 >> 7) & 1) != 0
         }
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable8(&self) -> bool {
+        pub const fn enable8(&self) -> bool {
             ((self.0 >> 8) & 1) != 0
         }
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable9(&self) -> bool {
+        pub const fn enable9(&self) -> bool {
             ((self.0 >> 9) & 1) != 0
         }
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable10(&self) -> bool {
+        pub const fn enable10(&self) -> bool {
             ((self.0 >> 10) & 1) != 0
         }
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable11(&self) -> bool {
+        pub const fn enable11(&self) -> bool {
             ((self.0 >> 11) & 1) != 0
         }
         #[doc = r" Construct a WriteVal that can be used to modify the contents of this register value."]
@@ -1477,67 +1876,67 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct EpInEnable0WriteVal(u32);
+    pub struct EpInEnable0WriteVal(pub u32);
     impl EpInEnable0WriteVal {
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable0(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 0)) | (u32::from(val) << 0))
+        pub const fn enable0(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 0)) | (val as u32) << 0)
         }
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable1(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 1)) | (u32::from(val) << 1))
+        pub const fn enable1(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 1)) | (val as u32) << 1)
         }
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable2(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 2)) | (u32::from(val) << 2))
+        pub const fn enable2(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 2)) | (val as u32) << 2)
         }
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable3(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 3)) | (u32::from(val) << 3))
+        pub const fn enable3(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 3)) | (val as u32) << 3)
         }
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable4(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 4)) | (u32::from(val) << 4))
+        pub const fn enable4(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 4)) | (val as u32) << 4)
         }
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable5(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 5)) | (u32::from(val) << 5))
+        pub const fn enable5(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 5)) | (val as u32) << 5)
         }
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable6(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 6)) | (u32::from(val) << 6))
+        pub const fn enable6(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 6)) | (val as u32) << 6)
         }
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable7(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 7)) | (u32::from(val) << 7))
+        pub const fn enable7(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 7)) | (val as u32) << 7)
         }
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable8(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 8)) | (u32::from(val) << 8))
+        pub const fn enable8(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 8)) | (val as u32) << 8)
         }
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable9(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 9)) | (u32::from(val) << 9))
+        pub const fn enable9(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 9)) | (val as u32) << 9)
         }
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable10(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 10)) | (u32::from(val) << 10))
+        pub const fn enable10(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 10)) | (val as u32) << 10)
         }
         #[doc = "This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear then any IN packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable11(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 11)) | (u32::from(val) << 11))
+        pub const fn enable11(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 11)) | (val as u32) << 11)
         }
     }
     impl From<u32> for EpInEnable0WriteVal {
@@ -1553,66 +1952,66 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct EpOutEnable0ReadVal(u32);
+    pub struct EpOutEnable0ReadVal(pub u32);
     impl EpOutEnable0ReadVal {
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable0(&self) -> bool {
+        pub const fn enable0(&self) -> bool {
             ((self.0 >> 0) & 1) != 0
         }
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable1(&self) -> bool {
+        pub const fn enable1(&self) -> bool {
             ((self.0 >> 1) & 1) != 0
         }
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable2(&self) -> bool {
+        pub const fn enable2(&self) -> bool {
             ((self.0 >> 2) & 1) != 0
         }
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable3(&self) -> bool {
+        pub const fn enable3(&self) -> bool {
             ((self.0 >> 3) & 1) != 0
         }
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable4(&self) -> bool {
+        pub const fn enable4(&self) -> bool {
             ((self.0 >> 4) & 1) != 0
         }
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable5(&self) -> bool {
+        pub const fn enable5(&self) -> bool {
             ((self.0 >> 5) & 1) != 0
         }
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable6(&self) -> bool {
+        pub const fn enable6(&self) -> bool {
             ((self.0 >> 6) & 1) != 0
         }
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable7(&self) -> bool {
+        pub const fn enable7(&self) -> bool {
             ((self.0 >> 7) & 1) != 0
         }
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable8(&self) -> bool {
+        pub const fn enable8(&self) -> bool {
             ((self.0 >> 8) & 1) != 0
         }
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable9(&self) -> bool {
+        pub const fn enable9(&self) -> bool {
             ((self.0 >> 9) & 1) != 0
         }
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable10(&self) -> bool {
+        pub const fn enable10(&self) -> bool {
             ((self.0 >> 10) & 1) != 0
         }
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable11(&self) -> bool {
+        pub const fn enable11(&self) -> bool {
             ((self.0 >> 11) & 1) != 0
         }
         #[doc = r" Construct a WriteVal that can be used to modify the contents of this register value."]
@@ -1634,67 +2033,67 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct EpOutEnable0WriteVal(u32);
+    pub struct EpOutEnable0WriteVal(pub u32);
     impl EpOutEnable0WriteVal {
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable0(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 0)) | (u32::from(val) << 0))
+        pub const fn enable0(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 0)) | (val as u32) << 0)
         }
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable1(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 1)) | (u32::from(val) << 1))
+        pub const fn enable1(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 1)) | (val as u32) << 1)
         }
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable2(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 2)) | (u32::from(val) << 2))
+        pub const fn enable2(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 2)) | (val as u32) << 2)
         }
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable3(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 3)) | (u32::from(val) << 3))
+        pub const fn enable3(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 3)) | (val as u32) << 3)
         }
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable4(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 4)) | (u32::from(val) << 4))
+        pub const fn enable4(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 4)) | (val as u32) << 4)
         }
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable5(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 5)) | (u32::from(val) << 5))
+        pub const fn enable5(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 5)) | (val as u32) << 5)
         }
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable6(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 6)) | (u32::from(val) << 6))
+        pub const fn enable6(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 6)) | (val as u32) << 6)
         }
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable7(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 7)) | (u32::from(val) << 7))
+        pub const fn enable7(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 7)) | (val as u32) << 7)
         }
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable8(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 8)) | (u32::from(val) << 8))
+        pub const fn enable8(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 8)) | (val as u32) << 8)
         }
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable9(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 9)) | (u32::from(val) << 9))
+        pub const fn enable9(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 9)) | (val as u32) << 9)
         }
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable10(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 10)) | (u32::from(val) << 10))
+        pub const fn enable10(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 10)) | (val as u32) << 10)
         }
         #[doc = "This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses.\nIf the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored."]
         #[inline(always)]
-        pub fn enable11(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 11)) | (u32::from(val) << 11))
+        pub const fn enable11(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 11)) | (val as u32) << 11)
         }
     }
     impl From<u32> for EpOutEnable0WriteVal {
@@ -1710,22 +2109,22 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct FifoCtrlWriteVal(u32);
+    pub struct FifoCtrlWriteVal(pub u32);
     impl FifoCtrlWriteVal {
         #[doc = "Software reset of the Available OUT Buffer FIFO. This must be used only when the USB device\nis not connected to the USB."]
         #[inline(always)]
-        pub fn avout_rst(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 0)) | (u32::from(val) << 0))
+        pub const fn avout_rst(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 0)) | (val as u32) << 0)
         }
         #[doc = "Software reset of the Available SETUP Buffer FIFO. This must be used only when the USB device\nis not connected to the USB."]
         #[inline(always)]
-        pub fn avsetup_rst(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 1)) | (u32::from(val) << 1))
+        pub const fn avsetup_rst(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 1)) | (val as u32) << 1)
         }
         #[doc = "Software reset the of Rx Buffer FIFO. This must be used only when the USB device is not\nconnected to the USB."]
         #[inline(always)]
-        pub fn rx_rst(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 2)) | (u32::from(val) << 2))
+        pub const fn rx_rst(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 2)) | (val as u32) << 2)
         }
     }
     impl From<u32> for FifoCtrlWriteVal {
@@ -1741,16 +2140,16 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct InDataToggleReadVal(u32);
+    pub struct InDataToggleReadVal(pub u32);
     impl InDataToggleReadVal {
         #[doc = "Reading returns the current state of the IN endpoint Data Toggle flags.\nWriting sets the Data Toggle flag for each endpoint if the corresponding mask bit\nin the upper half of this register is set."]
         #[inline(always)]
-        pub fn status(&self) -> u32 {
+        pub const fn status(&self) -> u32 {
             (self.0 >> 0) & 0xfff
         }
         #[doc = "Reads as zero.\nWhen writing, a set bit will cause the Data Toggle flag of the corresponding\nIN endpoint to be updated. A clear bit will leave the flag for the corresponding\nendpoint unchanged."]
         #[inline(always)]
-        pub fn mask(&self) -> u32 {
+        pub const fn mask(&self) -> u32 {
             (self.0 >> 16) & 0xfff
         }
         #[doc = r" Construct a WriteVal that can be used to modify the contents of this register value."]
@@ -1772,16 +2171,16 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct InDataToggleWriteVal(u32);
+    pub struct InDataToggleWriteVal(pub u32);
     impl InDataToggleWriteVal {
         #[doc = "Reading returns the current state of the IN endpoint Data Toggle flags.\nWriting sets the Data Toggle flag for each endpoint if the corresponding mask bit\nin the upper half of this register is set."]
         #[inline(always)]
-        pub fn status(self, val: u32) -> Self {
+        pub const fn status(self, val: u32) -> Self {
             Self((self.0 & !(0xfff << 0)) | ((val & 0xfff) << 0))
         }
         #[doc = "Reads as zero.\nWhen writing, a set bit will cause the Data Toggle flag of the corresponding\nIN endpoint to be updated. A clear bit will leave the flag for the corresponding\nendpoint unchanged."]
         #[inline(always)]
-        pub fn mask(self, val: u32) -> Self {
+        pub const fn mask(self, val: u32) -> Self {
             Self((self.0 & !(0xfff << 16)) | ((val & 0xfff) << 16))
         }
     }
@@ -1798,66 +2197,66 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct InIso0ReadVal(u32);
+    pub struct InIso0ReadVal(pub u32);
     impl InIso0ReadVal {
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso0(&self) -> bool {
+        pub const fn iso0(&self) -> bool {
             ((self.0 >> 0) & 1) != 0
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso1(&self) -> bool {
+        pub const fn iso1(&self) -> bool {
             ((self.0 >> 1) & 1) != 0
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso2(&self) -> bool {
+        pub const fn iso2(&self) -> bool {
             ((self.0 >> 2) & 1) != 0
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso3(&self) -> bool {
+        pub const fn iso3(&self) -> bool {
             ((self.0 >> 3) & 1) != 0
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso4(&self) -> bool {
+        pub const fn iso4(&self) -> bool {
             ((self.0 >> 4) & 1) != 0
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso5(&self) -> bool {
+        pub const fn iso5(&self) -> bool {
             ((self.0 >> 5) & 1) != 0
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso6(&self) -> bool {
+        pub const fn iso6(&self) -> bool {
             ((self.0 >> 6) & 1) != 0
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso7(&self) -> bool {
+        pub const fn iso7(&self) -> bool {
             ((self.0 >> 7) & 1) != 0
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso8(&self) -> bool {
+        pub const fn iso8(&self) -> bool {
             ((self.0 >> 8) & 1) != 0
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso9(&self) -> bool {
+        pub const fn iso9(&self) -> bool {
             ((self.0 >> 9) & 1) != 0
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso10(&self) -> bool {
+        pub const fn iso10(&self) -> bool {
             ((self.0 >> 10) & 1) != 0
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso11(&self) -> bool {
+        pub const fn iso11(&self) -> bool {
             ((self.0 >> 11) & 1) != 0
         }
         #[doc = r" Construct a WriteVal that can be used to modify the contents of this register value."]
@@ -1879,67 +2278,67 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct InIso0WriteVal(u32);
+    pub struct InIso0WriteVal(pub u32);
     impl InIso0WriteVal {
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso0(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 0)) | (u32::from(val) << 0))
+        pub const fn iso0(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 0)) | (val as u32) << 0)
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso1(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 1)) | (u32::from(val) << 1))
+        pub const fn iso1(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 1)) | (val as u32) << 1)
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso2(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 2)) | (u32::from(val) << 2))
+        pub const fn iso2(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 2)) | (val as u32) << 2)
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso3(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 3)) | (u32::from(val) << 3))
+        pub const fn iso3(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 3)) | (val as u32) << 3)
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso4(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 4)) | (u32::from(val) << 4))
+        pub const fn iso4(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 4)) | (val as u32) << 4)
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso5(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 5)) | (u32::from(val) << 5))
+        pub const fn iso5(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 5)) | (val as u32) << 5)
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso6(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 6)) | (u32::from(val) << 6))
+        pub const fn iso6(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 6)) | (val as u32) << 6)
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso7(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 7)) | (u32::from(val) << 7))
+        pub const fn iso7(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 7)) | (val as u32) << 7)
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso8(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 8)) | (u32::from(val) << 8))
+        pub const fn iso8(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 8)) | (val as u32) << 8)
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso9(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 9)) | (u32::from(val) << 9))
+        pub const fn iso9(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 9)) | (val as u32) << 9)
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso10(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 10)) | (u32::from(val) << 10))
+        pub const fn iso10(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 10)) | (val as u32) << 10)
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be expected for an IN transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso11(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 11)) | (u32::from(val) << 11))
+        pub const fn iso11(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 11)) | (val as u32) << 11)
         }
     }
     impl From<u32> for InIso0WriteVal {
@@ -1955,66 +2354,66 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct InSent0ReadVal(u32);
+    pub struct InSent0ReadVal(pub u32);
     impl InSent0ReadVal {
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent0(&self) -> bool {
+        pub const fn sent0(&self) -> bool {
             ((self.0 >> 0) & 1) != 0
         }
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent1(&self) -> bool {
+        pub const fn sent1(&self) -> bool {
             ((self.0 >> 1) & 1) != 0
         }
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent2(&self) -> bool {
+        pub const fn sent2(&self) -> bool {
             ((self.0 >> 2) & 1) != 0
         }
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent3(&self) -> bool {
+        pub const fn sent3(&self) -> bool {
             ((self.0 >> 3) & 1) != 0
         }
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent4(&self) -> bool {
+        pub const fn sent4(&self) -> bool {
             ((self.0 >> 4) & 1) != 0
         }
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent5(&self) -> bool {
+        pub const fn sent5(&self) -> bool {
             ((self.0 >> 5) & 1) != 0
         }
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent6(&self) -> bool {
+        pub const fn sent6(&self) -> bool {
             ((self.0 >> 6) & 1) != 0
         }
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent7(&self) -> bool {
+        pub const fn sent7(&self) -> bool {
             ((self.0 >> 7) & 1) != 0
         }
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent8(&self) -> bool {
+        pub const fn sent8(&self) -> bool {
             ((self.0 >> 8) & 1) != 0
         }
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent9(&self) -> bool {
+        pub const fn sent9(&self) -> bool {
             ((self.0 >> 9) & 1) != 0
         }
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent10(&self) -> bool {
+        pub const fn sent10(&self) -> bool {
             ((self.0 >> 10) & 1) != 0
         }
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent11(&self) -> bool {
+        pub const fn sent11(&self) -> bool {
             ((self.0 >> 11) & 1) != 0
         }
         #[doc = r" Construct a WriteVal that can be used to modify the contents of this register value."]
@@ -2036,66 +2435,66 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct InSent0WriteVal(u32);
+    pub struct InSent0WriteVal(pub u32);
     impl InSent0WriteVal {
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent0_clear(self) -> Self {
+        pub const fn sent0_clear(self) -> Self {
             Self(self.0 | (1 << 0))
         }
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent1_clear(self) -> Self {
+        pub const fn sent1_clear(self) -> Self {
             Self(self.0 | (1 << 1))
         }
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent2_clear(self) -> Self {
+        pub const fn sent2_clear(self) -> Self {
             Self(self.0 | (1 << 2))
         }
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent3_clear(self) -> Self {
+        pub const fn sent3_clear(self) -> Self {
             Self(self.0 | (1 << 3))
         }
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent4_clear(self) -> Self {
+        pub const fn sent4_clear(self) -> Self {
             Self(self.0 | (1 << 4))
         }
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent5_clear(self) -> Self {
+        pub const fn sent5_clear(self) -> Self {
             Self(self.0 | (1 << 5))
         }
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent6_clear(self) -> Self {
+        pub const fn sent6_clear(self) -> Self {
             Self(self.0 | (1 << 6))
         }
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent7_clear(self) -> Self {
+        pub const fn sent7_clear(self) -> Self {
             Self(self.0 | (1 << 7))
         }
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent8_clear(self) -> Self {
+        pub const fn sent8_clear(self) -> Self {
             Self(self.0 | (1 << 8))
         }
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent9_clear(self) -> Self {
+        pub const fn sent9_clear(self) -> Self {
             Self(self.0 | (1 << 9))
         }
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent10_clear(self) -> Self {
+        pub const fn sent10_clear(self) -> Self {
             Self(self.0 | (1 << 10))
         }
         #[doc = "This bit will be set when the ACK is received from\nthe host to indicate successful packet delivery\nas part of an IN transaction."]
         #[inline(always)]
-        pub fn sent11_clear(self) -> Self {
+        pub const fn sent11_clear(self) -> Self {
             Self(self.0 | (1 << 11))
         }
     }
@@ -2112,66 +2511,66 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct InStall0ReadVal(u32);
+    pub struct InStall0ReadVal(pub u32);
     impl InStall0ReadVal {
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint0(&self) -> bool {
+        pub const fn endpoint0(&self) -> bool {
             ((self.0 >> 0) & 1) != 0
         }
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint1(&self) -> bool {
+        pub const fn endpoint1(&self) -> bool {
             ((self.0 >> 1) & 1) != 0
         }
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint2(&self) -> bool {
+        pub const fn endpoint2(&self) -> bool {
             ((self.0 >> 2) & 1) != 0
         }
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint3(&self) -> bool {
+        pub const fn endpoint3(&self) -> bool {
             ((self.0 >> 3) & 1) != 0
         }
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint4(&self) -> bool {
+        pub const fn endpoint4(&self) -> bool {
             ((self.0 >> 4) & 1) != 0
         }
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint5(&self) -> bool {
+        pub const fn endpoint5(&self) -> bool {
             ((self.0 >> 5) & 1) != 0
         }
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint6(&self) -> bool {
+        pub const fn endpoint6(&self) -> bool {
             ((self.0 >> 6) & 1) != 0
         }
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint7(&self) -> bool {
+        pub const fn endpoint7(&self) -> bool {
             ((self.0 >> 7) & 1) != 0
         }
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint8(&self) -> bool {
+        pub const fn endpoint8(&self) -> bool {
             ((self.0 >> 8) & 1) != 0
         }
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint9(&self) -> bool {
+        pub const fn endpoint9(&self) -> bool {
             ((self.0 >> 9) & 1) != 0
         }
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint10(&self) -> bool {
+        pub const fn endpoint10(&self) -> bool {
             ((self.0 >> 10) & 1) != 0
         }
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint11(&self) -> bool {
+        pub const fn endpoint11(&self) -> bool {
             ((self.0 >> 11) & 1) != 0
         }
         #[doc = r" Construct a WriteVal that can be used to modify the contents of this register value."]
@@ -2193,67 +2592,67 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct InStall0WriteVal(u32);
+    pub struct InStall0WriteVal(pub u32);
     impl InStall0WriteVal {
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint0(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 0)) | (u32::from(val) << 0))
+        pub const fn endpoint0(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 0)) | (val as u32) << 0)
         }
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint1(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 1)) | (u32::from(val) << 1))
+        pub const fn endpoint1(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 1)) | (val as u32) << 1)
         }
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint2(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 2)) | (u32::from(val) << 2))
+        pub const fn endpoint2(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 2)) | (val as u32) << 2)
         }
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint3(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 3)) | (u32::from(val) << 3))
+        pub const fn endpoint3(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 3)) | (val as u32) << 3)
         }
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint4(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 4)) | (u32::from(val) << 4))
+        pub const fn endpoint4(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 4)) | (val as u32) << 4)
         }
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint5(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 5)) | (u32::from(val) << 5))
+        pub const fn endpoint5(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 5)) | (val as u32) << 5)
         }
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint6(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 6)) | (u32::from(val) << 6))
+        pub const fn endpoint6(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 6)) | (val as u32) << 6)
         }
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint7(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 7)) | (u32::from(val) << 7))
+        pub const fn endpoint7(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 7)) | (val as u32) << 7)
         }
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint8(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 8)) | (u32::from(val) << 8))
+        pub const fn endpoint8(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 8)) | (val as u32) << 8)
         }
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint9(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 9)) | (u32::from(val) << 9))
+        pub const fn endpoint9(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 9)) | (val as u32) << 9)
         }
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint10(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 10)) | (u32::from(val) << 10))
+        pub const fn endpoint10(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 10)) | (val as u32) << 10)
         }
         #[doc = "If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint11(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 11)) | (u32::from(val) << 11))
+        pub const fn endpoint11(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 11)) | (val as u32) << 11)
         }
     }
     impl From<u32> for InStall0WriteVal {
@@ -2269,16 +2668,16 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct OutDataToggleReadVal(u32);
+    pub struct OutDataToggleReadVal(pub u32);
     impl OutDataToggleReadVal {
         #[doc = "Reading returns the current state of the OUT endpoint Data Toggle flags.\nWriting sets the Data Toggle flag for each endpoint if the corresponding mask bit\nin the upper half of this register is set."]
         #[inline(always)]
-        pub fn status(&self) -> u32 {
+        pub const fn status(&self) -> u32 {
             (self.0 >> 0) & 0xfff
         }
         #[doc = "Reads as zero.\nWhen writing, a set bit will cause the Data Toggle flag of the corresponding\nOUT endpoint to be updated. A clear bit will leave the flag for the corresponding\nendpoint unchanged."]
         #[inline(always)]
-        pub fn mask(&self) -> u32 {
+        pub const fn mask(&self) -> u32 {
             (self.0 >> 16) & 0xfff
         }
         #[doc = r" Construct a WriteVal that can be used to modify the contents of this register value."]
@@ -2300,16 +2699,16 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct OutDataToggleWriteVal(u32);
+    pub struct OutDataToggleWriteVal(pub u32);
     impl OutDataToggleWriteVal {
         #[doc = "Reading returns the current state of the OUT endpoint Data Toggle flags.\nWriting sets the Data Toggle flag for each endpoint if the corresponding mask bit\nin the upper half of this register is set."]
         #[inline(always)]
-        pub fn status(self, val: u32) -> Self {
+        pub const fn status(self, val: u32) -> Self {
             Self((self.0 & !(0xfff << 0)) | ((val & 0xfff) << 0))
         }
         #[doc = "Reads as zero.\nWhen writing, a set bit will cause the Data Toggle flag of the corresponding\nOUT endpoint to be updated. A clear bit will leave the flag for the corresponding\nendpoint unchanged."]
         #[inline(always)]
-        pub fn mask(self, val: u32) -> Self {
+        pub const fn mask(self, val: u32) -> Self {
             Self((self.0 & !(0xfff << 16)) | ((val & 0xfff) << 16))
         }
     }
@@ -2326,66 +2725,66 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct OutIso0ReadVal(u32);
+    pub struct OutIso0ReadVal(pub u32);
     impl OutIso0ReadVal {
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso0(&self) -> bool {
+        pub const fn iso0(&self) -> bool {
             ((self.0 >> 0) & 1) != 0
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso1(&self) -> bool {
+        pub const fn iso1(&self) -> bool {
             ((self.0 >> 1) & 1) != 0
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso2(&self) -> bool {
+        pub const fn iso2(&self) -> bool {
             ((self.0 >> 2) & 1) != 0
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso3(&self) -> bool {
+        pub const fn iso3(&self) -> bool {
             ((self.0 >> 3) & 1) != 0
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso4(&self) -> bool {
+        pub const fn iso4(&self) -> bool {
             ((self.0 >> 4) & 1) != 0
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso5(&self) -> bool {
+        pub const fn iso5(&self) -> bool {
             ((self.0 >> 5) & 1) != 0
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso6(&self) -> bool {
+        pub const fn iso6(&self) -> bool {
             ((self.0 >> 6) & 1) != 0
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso7(&self) -> bool {
+        pub const fn iso7(&self) -> bool {
             ((self.0 >> 7) & 1) != 0
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso8(&self) -> bool {
+        pub const fn iso8(&self) -> bool {
             ((self.0 >> 8) & 1) != 0
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso9(&self) -> bool {
+        pub const fn iso9(&self) -> bool {
             ((self.0 >> 9) & 1) != 0
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso10(&self) -> bool {
+        pub const fn iso10(&self) -> bool {
             ((self.0 >> 10) & 1) != 0
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso11(&self) -> bool {
+        pub const fn iso11(&self) -> bool {
             ((self.0 >> 11) & 1) != 0
         }
         #[doc = r" Construct a WriteVal that can be used to modify the contents of this register value."]
@@ -2407,67 +2806,67 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct OutIso0WriteVal(u32);
+    pub struct OutIso0WriteVal(pub u32);
     impl OutIso0WriteVal {
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso0(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 0)) | (u32::from(val) << 0))
+        pub const fn iso0(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 0)) | (val as u32) << 0)
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso1(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 1)) | (u32::from(val) << 1))
+        pub const fn iso1(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 1)) | (val as u32) << 1)
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso2(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 2)) | (u32::from(val) << 2))
+        pub const fn iso2(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 2)) | (val as u32) << 2)
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso3(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 3)) | (u32::from(val) << 3))
+        pub const fn iso3(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 3)) | (val as u32) << 3)
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso4(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 4)) | (u32::from(val) << 4))
+        pub const fn iso4(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 4)) | (val as u32) << 4)
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso5(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 5)) | (u32::from(val) << 5))
+        pub const fn iso5(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 5)) | (val as u32) << 5)
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso6(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 6)) | (u32::from(val) << 6))
+        pub const fn iso6(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 6)) | (val as u32) << 6)
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso7(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 7)) | (u32::from(val) << 7))
+        pub const fn iso7(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 7)) | (val as u32) << 7)
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso8(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 8)) | (u32::from(val) << 8))
+        pub const fn iso8(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 8)) | (val as u32) << 8)
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso9(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 9)) | (u32::from(val) << 9))
+        pub const fn iso9(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 9)) | (val as u32) << 9)
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso10(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 10)) | (u32::from(val) << 10))
+        pub const fn iso10(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 10)) | (val as u32) << 10)
         }
         #[doc = "If this bit is set then the endpoint will be treated as an isochronous endpoint.\nNo handshake packet will be sent for an OUT transaction.\nNote that if a rxenable_setup is set for this endpoint's number, this bit will not take effect.\nControl endpoint configuration trumps isochronous endpoint configuration."]
         #[inline(always)]
-        pub fn iso11(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 11)) | (u32::from(val) << 11))
+        pub const fn iso11(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 11)) | (val as u32) << 11)
         }
     }
     impl From<u32> for OutIso0WriteVal {
@@ -2483,66 +2882,66 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct OutStall0ReadVal(u32);
+    pub struct OutStall0ReadVal(pub u32);
     impl OutStall0ReadVal {
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint0(&self) -> bool {
+        pub const fn endpoint0(&self) -> bool {
             ((self.0 >> 0) & 1) != 0
         }
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint1(&self) -> bool {
+        pub const fn endpoint1(&self) -> bool {
             ((self.0 >> 1) & 1) != 0
         }
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint2(&self) -> bool {
+        pub const fn endpoint2(&self) -> bool {
             ((self.0 >> 2) & 1) != 0
         }
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint3(&self) -> bool {
+        pub const fn endpoint3(&self) -> bool {
             ((self.0 >> 3) & 1) != 0
         }
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint4(&self) -> bool {
+        pub const fn endpoint4(&self) -> bool {
             ((self.0 >> 4) & 1) != 0
         }
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint5(&self) -> bool {
+        pub const fn endpoint5(&self) -> bool {
             ((self.0 >> 5) & 1) != 0
         }
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint6(&self) -> bool {
+        pub const fn endpoint6(&self) -> bool {
             ((self.0 >> 6) & 1) != 0
         }
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint7(&self) -> bool {
+        pub const fn endpoint7(&self) -> bool {
             ((self.0 >> 7) & 1) != 0
         }
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint8(&self) -> bool {
+        pub const fn endpoint8(&self) -> bool {
             ((self.0 >> 8) & 1) != 0
         }
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint9(&self) -> bool {
+        pub const fn endpoint9(&self) -> bool {
             ((self.0 >> 9) & 1) != 0
         }
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint10(&self) -> bool {
+        pub const fn endpoint10(&self) -> bool {
             ((self.0 >> 10) & 1) != 0
         }
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint11(&self) -> bool {
+        pub const fn endpoint11(&self) -> bool {
             ((self.0 >> 11) & 1) != 0
         }
         #[doc = r" Construct a WriteVal that can be used to modify the contents of this register value."]
@@ -2564,67 +2963,67 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct OutStall0WriteVal(u32);
+    pub struct OutStall0WriteVal(pub u32);
     impl OutStall0WriteVal {
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint0(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 0)) | (u32::from(val) << 0))
+        pub const fn endpoint0(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 0)) | (val as u32) << 0)
         }
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint1(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 1)) | (u32::from(val) << 1))
+        pub const fn endpoint1(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 1)) | (val as u32) << 1)
         }
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint2(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 2)) | (u32::from(val) << 2))
+        pub const fn endpoint2(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 2)) | (val as u32) << 2)
         }
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint3(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 3)) | (u32::from(val) << 3))
+        pub const fn endpoint3(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 3)) | (val as u32) << 3)
         }
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint4(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 4)) | (u32::from(val) << 4))
+        pub const fn endpoint4(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 4)) | (val as u32) << 4)
         }
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint5(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 5)) | (u32::from(val) << 5))
+        pub const fn endpoint5(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 5)) | (val as u32) << 5)
         }
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint6(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 6)) | (u32::from(val) << 6))
+        pub const fn endpoint6(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 6)) | (val as u32) << 6)
         }
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint7(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 7)) | (u32::from(val) << 7))
+        pub const fn endpoint7(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 7)) | (val as u32) << 7)
         }
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint8(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 8)) | (u32::from(val) << 8))
+        pub const fn endpoint8(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 8)) | (val as u32) << 8)
         }
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint9(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 9)) | (u32::from(val) << 9))
+        pub const fn endpoint9(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 9)) | (val as u32) << 9)
         }
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint10(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 10)) | (u32::from(val) << 10))
+        pub const fn endpoint10(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 10)) | (val as u32) << 10)
         }
         #[doc = "If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled.\nIf the configuration has both STALL and NAK enabled, the STALL handshake will take priority.\n\nNote that SETUP transactions are always either accepted or ignored.\nFor endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions."]
         #[inline(always)]
-        pub fn endpoint11(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 11)) | (u32::from(val) << 11))
+        pub const fn endpoint11(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 11)) | (val as u32) << 11)
         }
     }
     impl From<u32> for OutStall0WriteVal {
@@ -2640,36 +3039,36 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct PhyConfigReadVal(u32);
+    pub struct PhyConfigReadVal(pub u32);
     impl PhyConfigReadVal {
         #[doc = "Detect received K and J symbols from the usb_rx_d signal, which must be driven from an external differential receiver.\nIf 1, make use of the usb_rx_d input.\nIf 0, the usb_rx_d input is ignored and the usb_rx_dp and usb_rx_dn pair are used to detect K and J (useful for some environments, but will be unlikely to pass full USB compliance).\nRegardless of the state of this field usb_rx_dp and usb_rx_dn are always used to detect SE0.\nThis bit also feeds the rx_enable pin, activating the receiver when the device is not suspended."]
         #[inline(always)]
-        pub fn use_diff_rcvr(&self) -> bool {
+        pub const fn use_diff_rcvr(&self) -> bool {
             ((self.0 >> 0) & 1) != 0
         }
         #[doc = "If 1, select the d and se0 TX interface.\nIf 0, select the dp and dn TX interface.\nThis directly controls the output pin of the same name.\nIt is intended to be used to enable the use of a variety of external transceivers, to select an encoding that matches the transceiver."]
         #[inline(always)]
-        pub fn tx_use_d_se0(&self) -> bool {
+        pub const fn tx_use_d_se0(&self) -> bool {
             ((self.0 >> 1) & 1) != 0
         }
         #[doc = "Recognize a single SE0 bit as an end of packet, otherwise two successive bits are required."]
         #[inline(always)]
-        pub fn eop_single_bit(&self) -> bool {
+        pub const fn eop_single_bit(&self) -> bool {
             ((self.0 >> 2) & 1) != 0
         }
         #[doc = "Flip the D+/D- pins.\nParticularly useful if D+/D- are mapped to SBU1/SBU2 pins of USB-C.\n"]
         #[inline(always)]
-        pub fn pinflip(&self) -> bool {
+        pub const fn pinflip(&self) -> bool {
             ((self.0 >> 5) & 1) != 0
         }
         #[doc = "0: Enable reference signal generation for clock synchronization, 1: disable it by forcing the associated signals to zero.\n"]
         #[inline(always)]
-        pub fn usb_ref_disable(&self) -> bool {
+        pub const fn usb_ref_disable(&self) -> bool {
             ((self.0 >> 6) & 1) != 0
         }
         #[doc = "Disable (0) or enable (1) oscillator test mode.\nIf enabled, the device constantly transmits a J/K pattern, which is useful for testing the USB clock.\nNote that while in oscillator test mode, the device no longer receives SOFs and consequently does not generate the reference signal for clock synchronization.\nThe clock might drift off.\n"]
         #[inline(always)]
-        pub fn tx_osc_test_mode(&self) -> bool {
+        pub const fn tx_osc_test_mode(&self) -> bool {
             ((self.0 >> 7) & 1) != 0
         }
         #[doc = r" Construct a WriteVal that can be used to modify the contents of this register value."]
@@ -2691,37 +3090,37 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct PhyConfigWriteVal(u32);
+    pub struct PhyConfigWriteVal(pub u32);
     impl PhyConfigWriteVal {
         #[doc = "Detect received K and J symbols from the usb_rx_d signal, which must be driven from an external differential receiver.\nIf 1, make use of the usb_rx_d input.\nIf 0, the usb_rx_d input is ignored and the usb_rx_dp and usb_rx_dn pair are used to detect K and J (useful for some environments, but will be unlikely to pass full USB compliance).\nRegardless of the state of this field usb_rx_dp and usb_rx_dn are always used to detect SE0.\nThis bit also feeds the rx_enable pin, activating the receiver when the device is not suspended."]
         #[inline(always)]
-        pub fn use_diff_rcvr(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 0)) | (u32::from(val) << 0))
+        pub const fn use_diff_rcvr(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 0)) | (val as u32) << 0)
         }
         #[doc = "If 1, select the d and se0 TX interface.\nIf 0, select the dp and dn TX interface.\nThis directly controls the output pin of the same name.\nIt is intended to be used to enable the use of a variety of external transceivers, to select an encoding that matches the transceiver."]
         #[inline(always)]
-        pub fn tx_use_d_se0(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 1)) | (u32::from(val) << 1))
+        pub const fn tx_use_d_se0(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 1)) | (val as u32) << 1)
         }
         #[doc = "Recognize a single SE0 bit as an end of packet, otherwise two successive bits are required."]
         #[inline(always)]
-        pub fn eop_single_bit(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 2)) | (u32::from(val) << 2))
+        pub const fn eop_single_bit(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 2)) | (val as u32) << 2)
         }
         #[doc = "Flip the D+/D- pins.\nParticularly useful if D+/D- are mapped to SBU1/SBU2 pins of USB-C.\n"]
         #[inline(always)]
-        pub fn pinflip(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 5)) | (u32::from(val) << 5))
+        pub const fn pinflip(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 5)) | (val as u32) << 5)
         }
         #[doc = "0: Enable reference signal generation for clock synchronization, 1: disable it by forcing the associated signals to zero.\n"]
         #[inline(always)]
-        pub fn usb_ref_disable(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 6)) | (u32::from(val) << 6))
+        pub const fn usb_ref_disable(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 6)) | (val as u32) << 6)
         }
         #[doc = "Disable (0) or enable (1) oscillator test mode.\nIf enabled, the device constantly transmits a J/K pattern, which is useful for testing the USB clock.\nNote that while in oscillator test mode, the device no longer receives SOFs and consequently does not generate the reference signal for clock synchronization.\nThe clock might drift off.\n"]
         #[inline(always)]
-        pub fn tx_osc_test_mode(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 7)) | (u32::from(val) << 7))
+        pub const fn tx_osc_test_mode(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 7)) | (val as u32) << 7)
         }
     }
     impl From<u32> for PhyConfigWriteVal {
@@ -2737,51 +3136,51 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct PhyPinsDriveReadVal(u32);
+    pub struct PhyPinsDriveReadVal(pub u32);
     impl PhyPinsDriveReadVal {
         #[doc = "USB transmit D+ output, used with dn_o."]
         #[inline(always)]
-        pub fn dp_o(&self) -> bool {
+        pub const fn dp_o(&self) -> bool {
             ((self.0 >> 0) & 1) != 0
         }
         #[doc = "USB transmit D- output, used with dp_o."]
         #[inline(always)]
-        pub fn dn_o(&self) -> bool {
+        pub const fn dn_o(&self) -> bool {
             ((self.0 >> 1) & 1) != 0
         }
         #[doc = "USB transmit data output, encoding K and J when se0_o is 0."]
         #[inline(always)]
-        pub fn d_o(&self) -> bool {
+        pub const fn d_o(&self) -> bool {
             ((self.0 >> 2) & 1) != 0
         }
         #[doc = "USB single-ended zero output."]
         #[inline(always)]
-        pub fn se0_o(&self) -> bool {
+        pub const fn se0_o(&self) -> bool {
             ((self.0 >> 3) & 1) != 0
         }
         #[doc = "USB OE output."]
         #[inline(always)]
-        pub fn oe_o(&self) -> bool {
+        pub const fn oe_o(&self) -> bool {
             ((self.0 >> 4) & 1) != 0
         }
         #[doc = "Enable differential receiver."]
         #[inline(always)]
-        pub fn rx_enable_o(&self) -> bool {
+        pub const fn rx_enable_o(&self) -> bool {
             ((self.0 >> 5) & 1) != 0
         }
         #[doc = "USB D+ pullup enable output."]
         #[inline(always)]
-        pub fn dp_pullup_en_o(&self) -> bool {
+        pub const fn dp_pullup_en_o(&self) -> bool {
             ((self.0 >> 6) & 1) != 0
         }
         #[doc = "USB D- pullup enable output."]
         #[inline(always)]
-        pub fn dn_pullup_en_o(&self) -> bool {
+        pub const fn dn_pullup_en_o(&self) -> bool {
             ((self.0 >> 7) & 1) != 0
         }
         #[doc = "0: Outputs are controlled by the hardware block.\n1: Outputs are controlled with this register."]
         #[inline(always)]
-        pub fn en(&self) -> bool {
+        pub const fn en(&self) -> bool {
             ((self.0 >> 16) & 1) != 0
         }
         #[doc = r" Construct a WriteVal that can be used to modify the contents of this register value."]
@@ -2803,52 +3202,52 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct PhyPinsDriveWriteVal(u32);
+    pub struct PhyPinsDriveWriteVal(pub u32);
     impl PhyPinsDriveWriteVal {
         #[doc = "USB transmit D+ output, used with dn_o."]
         #[inline(always)]
-        pub fn dp_o(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 0)) | (u32::from(val) << 0))
+        pub const fn dp_o(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 0)) | (val as u32) << 0)
         }
         #[doc = "USB transmit D- output, used with dp_o."]
         #[inline(always)]
-        pub fn dn_o(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 1)) | (u32::from(val) << 1))
+        pub const fn dn_o(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 1)) | (val as u32) << 1)
         }
         #[doc = "USB transmit data output, encoding K and J when se0_o is 0."]
         #[inline(always)]
-        pub fn d_o(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 2)) | (u32::from(val) << 2))
+        pub const fn d_o(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 2)) | (val as u32) << 2)
         }
         #[doc = "USB single-ended zero output."]
         #[inline(always)]
-        pub fn se0_o(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 3)) | (u32::from(val) << 3))
+        pub const fn se0_o(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 3)) | (val as u32) << 3)
         }
         #[doc = "USB OE output."]
         #[inline(always)]
-        pub fn oe_o(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 4)) | (u32::from(val) << 4))
+        pub const fn oe_o(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 4)) | (val as u32) << 4)
         }
         #[doc = "Enable differential receiver."]
         #[inline(always)]
-        pub fn rx_enable_o(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 5)) | (u32::from(val) << 5))
+        pub const fn rx_enable_o(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 5)) | (val as u32) << 5)
         }
         #[doc = "USB D+ pullup enable output."]
         #[inline(always)]
-        pub fn dp_pullup_en_o(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 6)) | (u32::from(val) << 6))
+        pub const fn dp_pullup_en_o(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 6)) | (val as u32) << 6)
         }
         #[doc = "USB D- pullup enable output."]
         #[inline(always)]
-        pub fn dn_pullup_en_o(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 7)) | (u32::from(val) << 7))
+        pub const fn dn_pullup_en_o(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 7)) | (val as u32) << 7)
         }
         #[doc = "0: Outputs are controlled by the hardware block.\n1: Outputs are controlled with this register."]
         #[inline(always)]
-        pub fn en(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 16)) | (u32::from(val) << 16))
+        pub const fn en(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 16)) | (val as u32) << 16)
         }
     }
     impl From<u32> for PhyPinsDriveWriteVal {
@@ -2864,51 +3263,51 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct PhyPinsSenseReadVal(u32);
+    pub struct PhyPinsSenseReadVal(pub u32);
     impl PhyPinsSenseReadVal {
         #[doc = "USB D+ input."]
         #[inline(always)]
-        pub fn rx_dp_i(&self) -> bool {
+        pub const fn rx_dp_i(&self) -> bool {
             ((self.0 >> 0) & 1) != 0
         }
         #[doc = "USB D- input."]
         #[inline(always)]
-        pub fn rx_dn_i(&self) -> bool {
+        pub const fn rx_dn_i(&self) -> bool {
             ((self.0 >> 1) & 1) != 0
         }
         #[doc = "USB data input from an external differential receiver, if available."]
         #[inline(always)]
-        pub fn rx_d_i(&self) -> bool {
+        pub const fn rx_d_i(&self) -> bool {
             ((self.0 >> 2) & 1) != 0
         }
         #[doc = "USB transmit D+ output (readback)."]
         #[inline(always)]
-        pub fn tx_dp_o(&self) -> bool {
+        pub const fn tx_dp_o(&self) -> bool {
             ((self.0 >> 8) & 1) != 0
         }
         #[doc = "USB transmit D- output (readback)."]
         #[inline(always)]
-        pub fn tx_dn_o(&self) -> bool {
+        pub const fn tx_dn_o(&self) -> bool {
             ((self.0 >> 9) & 1) != 0
         }
         #[doc = "USB transmit data value (readback)."]
         #[inline(always)]
-        pub fn tx_d_o(&self) -> bool {
+        pub const fn tx_d_o(&self) -> bool {
             ((self.0 >> 10) & 1) != 0
         }
         #[doc = "USB single-ended zero output (readback)."]
         #[inline(always)]
-        pub fn tx_se0_o(&self) -> bool {
+        pub const fn tx_se0_o(&self) -> bool {
             ((self.0 >> 11) & 1) != 0
         }
         #[doc = "USB OE output (readback)."]
         #[inline(always)]
-        pub fn tx_oe_o(&self) -> bool {
+        pub const fn tx_oe_o(&self) -> bool {
             ((self.0 >> 12) & 1) != 0
         }
         #[doc = "USB power sense signal."]
         #[inline(always)]
-        pub fn pwr_sense(&self) -> bool {
+        pub const fn pwr_sense(&self) -> bool {
             ((self.0 >> 16) & 1) != 0
         }
     }
@@ -2925,66 +3324,66 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct RxenableOut0ReadVal(u32);
+    pub struct RxenableOut0ReadVal(pub u32);
     impl RxenableOut0ReadVal {
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out0(&self) -> bool {
+        pub const fn out0(&self) -> bool {
             ((self.0 >> 0) & 1) != 0
         }
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out1(&self) -> bool {
+        pub const fn out1(&self) -> bool {
             ((self.0 >> 1) & 1) != 0
         }
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out2(&self) -> bool {
+        pub const fn out2(&self) -> bool {
             ((self.0 >> 2) & 1) != 0
         }
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out3(&self) -> bool {
+        pub const fn out3(&self) -> bool {
             ((self.0 >> 3) & 1) != 0
         }
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out4(&self) -> bool {
+        pub const fn out4(&self) -> bool {
             ((self.0 >> 4) & 1) != 0
         }
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out5(&self) -> bool {
+        pub const fn out5(&self) -> bool {
             ((self.0 >> 5) & 1) != 0
         }
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out6(&self) -> bool {
+        pub const fn out6(&self) -> bool {
             ((self.0 >> 6) & 1) != 0
         }
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out7(&self) -> bool {
+        pub const fn out7(&self) -> bool {
             ((self.0 >> 7) & 1) != 0
         }
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out8(&self) -> bool {
+        pub const fn out8(&self) -> bool {
             ((self.0 >> 8) & 1) != 0
         }
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out9(&self) -> bool {
+        pub const fn out9(&self) -> bool {
             ((self.0 >> 9) & 1) != 0
         }
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out10(&self) -> bool {
+        pub const fn out10(&self) -> bool {
             ((self.0 >> 10) & 1) != 0
         }
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out11(&self) -> bool {
+        pub const fn out11(&self) -> bool {
             ((self.0 >> 11) & 1) != 0
         }
         #[doc = r" Construct a WriteVal that can be used to modify the contents of this register value."]
@@ -3006,67 +3405,67 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct RxenableOut0WriteVal(u32);
+    pub struct RxenableOut0WriteVal(pub u32);
     impl RxenableOut0WriteVal {
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out0(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 0)) | (u32::from(val) << 0))
+        pub const fn out0(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 0)) | (val as u32) << 0)
         }
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out1(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 1)) | (u32::from(val) << 1))
+        pub const fn out1(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 1)) | (val as u32) << 1)
         }
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out2(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 2)) | (u32::from(val) << 2))
+        pub const fn out2(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 2)) | (val as u32) << 2)
         }
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out3(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 3)) | (u32::from(val) << 3))
+        pub const fn out3(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 3)) | (val as u32) << 3)
         }
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out4(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 4)) | (u32::from(val) << 4))
+        pub const fn out4(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 4)) | (val as u32) << 4)
         }
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out5(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 5)) | (u32::from(val) << 5))
+        pub const fn out5(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 5)) | (val as u32) << 5)
         }
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out6(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 6)) | (u32::from(val) << 6))
+        pub const fn out6(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 6)) | (val as u32) << 6)
         }
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out7(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 7)) | (u32::from(val) << 7))
+        pub const fn out7(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 7)) | (val as u32) << 7)
         }
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out8(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 8)) | (u32::from(val) << 8))
+        pub const fn out8(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 8)) | (val as u32) << 8)
         }
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out9(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 9)) | (u32::from(val) << 9))
+        pub const fn out9(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 9)) | (val as u32) << 9)
         }
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out10(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 10)) | (u32::from(val) << 10))
+        pub const fn out10(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 10)) | (val as u32) << 10)
         }
         #[doc = "This bit must be set to enable OUT transactions to be received on the endpoint.\nIf the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled.\nIf set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint.\nSoftware must set this bit again to receive the next OUT transaction.\nUntil that happens, hardware will continue to NAK any OUT transaction to this endpoint."]
         #[inline(always)]
-        pub fn out11(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 11)) | (u32::from(val) << 11))
+        pub const fn out11(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 11)) | (val as u32) << 11)
         }
     }
     impl From<u32> for RxenableOut0WriteVal {
@@ -3082,66 +3481,66 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct RxenableSetup0ReadVal(u32);
+    pub struct RxenableSetup0ReadVal(pub u32);
     impl RxenableSetup0ReadVal {
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup0(&self) -> bool {
+        pub const fn setup0(&self) -> bool {
             ((self.0 >> 0) & 1) != 0
         }
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup1(&self) -> bool {
+        pub const fn setup1(&self) -> bool {
             ((self.0 >> 1) & 1) != 0
         }
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup2(&self) -> bool {
+        pub const fn setup2(&self) -> bool {
             ((self.0 >> 2) & 1) != 0
         }
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup3(&self) -> bool {
+        pub const fn setup3(&self) -> bool {
             ((self.0 >> 3) & 1) != 0
         }
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup4(&self) -> bool {
+        pub const fn setup4(&self) -> bool {
             ((self.0 >> 4) & 1) != 0
         }
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup5(&self) -> bool {
+        pub const fn setup5(&self) -> bool {
             ((self.0 >> 5) & 1) != 0
         }
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup6(&self) -> bool {
+        pub const fn setup6(&self) -> bool {
             ((self.0 >> 6) & 1) != 0
         }
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup7(&self) -> bool {
+        pub const fn setup7(&self) -> bool {
             ((self.0 >> 7) & 1) != 0
         }
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup8(&self) -> bool {
+        pub const fn setup8(&self) -> bool {
             ((self.0 >> 8) & 1) != 0
         }
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup9(&self) -> bool {
+        pub const fn setup9(&self) -> bool {
             ((self.0 >> 9) & 1) != 0
         }
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup10(&self) -> bool {
+        pub const fn setup10(&self) -> bool {
             ((self.0 >> 10) & 1) != 0
         }
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup11(&self) -> bool {
+        pub const fn setup11(&self) -> bool {
             ((self.0 >> 11) & 1) != 0
         }
         #[doc = r" Construct a WriteVal that can be used to modify the contents of this register value."]
@@ -3163,67 +3562,67 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct RxenableSetup0WriteVal(u32);
+    pub struct RxenableSetup0WriteVal(pub u32);
     impl RxenableSetup0WriteVal {
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup0(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 0)) | (u32::from(val) << 0))
+        pub const fn setup0(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 0)) | (val as u32) << 0)
         }
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup1(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 1)) | (u32::from(val) << 1))
+        pub const fn setup1(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 1)) | (val as u32) << 1)
         }
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup2(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 2)) | (u32::from(val) << 2))
+        pub const fn setup2(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 2)) | (val as u32) << 2)
         }
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup3(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 3)) | (u32::from(val) << 3))
+        pub const fn setup3(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 3)) | (val as u32) << 3)
         }
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup4(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 4)) | (u32::from(val) << 4))
+        pub const fn setup4(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 4)) | (val as u32) << 4)
         }
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup5(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 5)) | (u32::from(val) << 5))
+        pub const fn setup5(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 5)) | (val as u32) << 5)
         }
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup6(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 6)) | (u32::from(val) << 6))
+        pub const fn setup6(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 6)) | (val as u32) << 6)
         }
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup7(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 7)) | (u32::from(val) << 7))
+        pub const fn setup7(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 7)) | (val as u32) << 7)
         }
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup8(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 8)) | (u32::from(val) << 8))
+        pub const fn setup8(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 8)) | (val as u32) << 8)
         }
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup9(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 9)) | (u32::from(val) << 9))
+        pub const fn setup9(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 9)) | (val as u32) << 9)
         }
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup10(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 10)) | (u32::from(val) << 10))
+        pub const fn setup10(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 10)) | (val as u32) << 10)
         }
         #[doc = "This bit must be set to enable SETUP transactions to be\nreceived on the endpoint. If the bit is clear then a\nSETUP packet will be ignored. The bit should be set for\ncontrol endpoints (and only control endpoints)."]
         #[inline(always)]
-        pub fn setup11(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 11)) | (u32::from(val) << 11))
+        pub const fn setup11(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 11)) | (val as u32) << 11)
         }
     }
     impl From<u32> for RxenableSetup0WriteVal {
@@ -3239,26 +3638,26 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct RxfifoReadVal(u32);
+    pub struct RxfifoReadVal(pub u32);
     impl RxfifoReadVal {
         #[doc = "This field contains the buffer ID that data was received into.\nOn read the buffer ID is popped from the Received Buffer FIFO and returned to software."]
         #[inline(always)]
-        pub fn buffer(&self) -> u32 {
+        pub const fn buffer(&self) -> u32 {
             (self.0 >> 0) & 0x1f
         }
         #[doc = "This field contains the data length in bytes of the packet written to the buffer."]
         #[inline(always)]
-        pub fn size(&self) -> u32 {
+        pub const fn size(&self) -> u32 {
             (self.0 >> 8) & 0x7f
         }
         #[doc = "This bit indicates if the received transaction is of type SETUP (1) or OUT (0)."]
         #[inline(always)]
-        pub fn setup(&self) -> bool {
+        pub const fn setup(&self) -> bool {
             ((self.0 >> 19) & 1) != 0
         }
         #[doc = "This field contains the endpoint ID to which the packet was directed."]
         #[inline(always)]
-        pub fn ep(&self) -> u32 {
+        pub const fn ep(&self) -> u32 {
             (self.0 >> 20) & 0xf
         }
     }
@@ -3275,66 +3674,66 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct SetNakOut0ReadVal(u32);
+    pub struct SetNakOut0ReadVal(pub u32);
     impl SetNakOut0ReadVal {
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable0(&self) -> bool {
+        pub const fn enable0(&self) -> bool {
             ((self.0 >> 0) & 1) != 0
         }
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable1(&self) -> bool {
+        pub const fn enable1(&self) -> bool {
             ((self.0 >> 1) & 1) != 0
         }
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable2(&self) -> bool {
+        pub const fn enable2(&self) -> bool {
             ((self.0 >> 2) & 1) != 0
         }
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable3(&self) -> bool {
+        pub const fn enable3(&self) -> bool {
             ((self.0 >> 3) & 1) != 0
         }
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable4(&self) -> bool {
+        pub const fn enable4(&self) -> bool {
             ((self.0 >> 4) & 1) != 0
         }
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable5(&self) -> bool {
+        pub const fn enable5(&self) -> bool {
             ((self.0 >> 5) & 1) != 0
         }
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable6(&self) -> bool {
+        pub const fn enable6(&self) -> bool {
             ((self.0 >> 6) & 1) != 0
         }
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable7(&self) -> bool {
+        pub const fn enable7(&self) -> bool {
             ((self.0 >> 7) & 1) != 0
         }
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable8(&self) -> bool {
+        pub const fn enable8(&self) -> bool {
             ((self.0 >> 8) & 1) != 0
         }
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable9(&self) -> bool {
+        pub const fn enable9(&self) -> bool {
             ((self.0 >> 9) & 1) != 0
         }
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable10(&self) -> bool {
+        pub const fn enable10(&self) -> bool {
             ((self.0 >> 10) & 1) != 0
         }
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable11(&self) -> bool {
+        pub const fn enable11(&self) -> bool {
             ((self.0 >> 11) & 1) != 0
         }
         #[doc = r" Construct a WriteVal that can be used to modify the contents of this register value."]
@@ -3356,67 +3755,67 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct SetNakOut0WriteVal(u32);
+    pub struct SetNakOut0WriteVal(pub u32);
     impl SetNakOut0WriteVal {
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable0(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 0)) | (u32::from(val) << 0))
+        pub const fn enable0(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 0)) | (val as u32) << 0)
         }
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable1(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 1)) | (u32::from(val) << 1))
+        pub const fn enable1(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 1)) | (val as u32) << 1)
         }
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable2(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 2)) | (u32::from(val) << 2))
+        pub const fn enable2(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 2)) | (val as u32) << 2)
         }
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable3(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 3)) | (u32::from(val) << 3))
+        pub const fn enable3(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 3)) | (val as u32) << 3)
         }
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable4(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 4)) | (u32::from(val) << 4))
+        pub const fn enable4(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 4)) | (val as u32) << 4)
         }
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable5(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 5)) | (u32::from(val) << 5))
+        pub const fn enable5(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 5)) | (val as u32) << 5)
         }
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable6(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 6)) | (u32::from(val) << 6))
+        pub const fn enable6(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 6)) | (val as u32) << 6)
         }
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable7(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 7)) | (u32::from(val) << 7))
+        pub const fn enable7(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 7)) | (val as u32) << 7)
         }
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable8(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 8)) | (u32::from(val) << 8))
+        pub const fn enable8(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 8)) | (val as u32) << 8)
         }
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable9(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 9)) | (u32::from(val) << 9))
+        pub const fn enable9(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 9)) | (val as u32) << 9)
         }
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable10(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 10)) | (u32::from(val) << 10))
+        pub const fn enable10(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 10)) | (val as u32) << 10)
         }
         #[doc = "When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint.\nThis bit should not be changed while the endpoint is active."]
         #[inline(always)]
-        pub fn enable11(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 11)) | (u32::from(val) << 11))
+        pub const fn enable11(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 11)) | (val as u32) << 11)
         }
     }
     impl From<u32> for SetNakOut0WriteVal {
@@ -3432,16 +3831,16 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct UsbctrlReadVal(u32);
+    pub struct UsbctrlReadVal(pub u32);
     impl UsbctrlReadVal {
         #[doc = "Set to connect the USB interface (i.e. assert the pullup)."]
         #[inline(always)]
-        pub fn enable(&self) -> bool {
+        pub const fn enable(&self) -> bool {
             ((self.0 >> 0) & 1) != 0
         }
         #[doc = "Device address set by host (this should be copied from\nthe Set Device ID SETUP packet).\n\nThis will be zeroed by the hardware when the link resets."]
         #[inline(always)]
-        pub fn device_address(&self) -> u32 {
+        pub const fn device_address(&self) -> u32 {
             (self.0 >> 16) & 0x7f
         }
         #[doc = r" Construct a WriteVal that can be used to modify the contents of this register value."]
@@ -3463,21 +3862,21 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct UsbctrlWriteVal(u32);
+    pub struct UsbctrlWriteVal(pub u32);
     impl UsbctrlWriteVal {
         #[doc = "Set to connect the USB interface (i.e. assert the pullup)."]
         #[inline(always)]
-        pub fn enable(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 0)) | (u32::from(val) << 0))
+        pub const fn enable(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 0)) | (val as u32) << 0)
         }
         #[doc = "Write a 1 to this bit to instruct usbdev to jump to the LinkResuming state.\nThe write will only have an effect when the device is in the LinkPowered state.\nIts intention is to handle a resume-from-suspend event after the IP has been powered down."]
         #[inline(always)]
-        pub fn resume_link_active(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 1)) | (u32::from(val) << 1))
+        pub const fn resume_link_active(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 1)) | (val as u32) << 1)
         }
         #[doc = "Device address set by host (this should be copied from\nthe Set Device ID SETUP packet).\n\nThis will be zeroed by the hardware when the link resets."]
         #[inline(always)]
-        pub fn device_address(self, val: u32) -> Self {
+        pub const fn device_address(self, val: u32) -> Self {
             Self((self.0 & !(0x7f << 16)) | ((val & 0x7f) << 16))
         }
     }
@@ -3494,56 +3893,56 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct UsbstatReadVal(u32);
+    pub struct UsbstatReadVal(pub u32);
     impl UsbstatReadVal {
         #[doc = "Frame index received from host. On an active link, this will increment every milisecond."]
         #[inline(always)]
-        pub fn frame(&self) -> u32 {
+        pub const fn frame(&self) -> u32 {
             (self.0 >> 0) & 0x7ff
         }
         #[doc = "Start of frame not received from host for 4.096 ms and the line is active."]
         #[inline(always)]
-        pub fn host_lost(&self) -> bool {
+        pub const fn host_lost(&self) -> bool {
             ((self.0 >> 11) & 1) != 0
         }
         #[doc = "State of USB link, decoded from line."]
         #[inline(always)]
-        pub fn link_state(&self) -> super::enums::LinkState {
-            super::enums::LinkState::try_from((self.0 >> 12) & 7).unwrap()
+        pub const fn link_state(&self) -> super::enums::LinkState {
+            super::enums::LinkState::from_raw((self.0 >> 12) & 7).unwrap()
         }
         #[doc = "Reflects the state of the sense pin.\n1 indicates that the host is providing VBUS.\nNote that this bit always shows the state of the actual pin and does not take account of the override control."]
         #[inline(always)]
-        pub fn sense(&self) -> bool {
+        pub const fn sense(&self) -> bool {
             ((self.0 >> 15) & 1) != 0
         }
         #[doc = "Number of buffers in the Available OUT Buffer FIFO.\n\nThese buffers are available for receiving OUT DATA packets."]
         #[inline(always)]
-        pub fn av_out_depth(&self) -> u32 {
+        pub const fn av_out_depth(&self) -> u32 {
             (self.0 >> 16) & 0xf
         }
         #[doc = "Number of buffers in the Available SETUP Buffer FIFO.\n\nThese buffers are available for receiving SETUP DATA packets."]
         #[inline(always)]
-        pub fn av_setup_depth(&self) -> u32 {
+        pub const fn av_setup_depth(&self) -> u32 {
             (self.0 >> 20) & 7
         }
         #[doc = "Available OUT Buffer FIFO is full."]
         #[inline(always)]
-        pub fn av_out_full(&self) -> bool {
+        pub const fn av_out_full(&self) -> bool {
             ((self.0 >> 23) & 1) != 0
         }
         #[doc = "Number of buffers in the Received Buffer FIFO.\n\nThese buffers have packets that have been received and\nshould be popped from the FIFO and processed."]
         #[inline(always)]
-        pub fn rx_depth(&self) -> u32 {
+        pub const fn rx_depth(&self) -> u32 {
             (self.0 >> 24) & 0xf
         }
         #[doc = "Available SETUP Buffer FIFO is full."]
         #[inline(always)]
-        pub fn av_setup_full(&self) -> bool {
+        pub const fn av_setup_full(&self) -> bool {
             ((self.0 >> 30) & 1) != 0
         }
         #[doc = "Received Buffer FIFO is empty."]
         #[inline(always)]
-        pub fn rx_empty(&self) -> bool {
+        pub const fn rx_empty(&self) -> bool {
             ((self.0 >> 31) & 1) != 0
         }
     }
@@ -3560,17 +3959,17 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct WakeControlWriteVal(u32);
+    pub struct WakeControlWriteVal(pub u32);
     impl WakeControlWriteVal {
         #[doc = "Suspend request to the wake detection module.\n\nTrigger the wake detection module to begin monitoring for wake-from-suspend events.\nWhen written with a 1, the wake detection module will activate.\nActivation may not happen immediately, and its status can be verified by checking wake_events.module_active."]
         #[inline(always)]
-        pub fn suspend_req(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 0)) | (u32::from(val) << 0))
+        pub const fn suspend_req(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 0)) | (val as u32) << 0)
         }
         #[doc = "Wake acknowledgement.\n\nSignal to the wake detection module that it may release control of the pull-ups back to the main block and return to an inactive state.\nThe release back to normal state may not happen immediately.\nThe status can be confirmed via wake_events.module_active.\n\nNote that this bit can also be used without powering down, such as when usbdev detects resume signaling before transitions to low power states have begun."]
         #[inline(always)]
-        pub fn wake_ack(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 1)) | (u32::from(val) << 1))
+        pub const fn wake_ack(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 1)) | (val as u32) << 1)
         }
     }
     impl From<u32> for WakeControlWriteVal {
@@ -3586,26 +3985,26 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
-    pub struct WakeEventsReadVal(u32);
+    pub struct WakeEventsReadVal(pub u32);
     impl WakeEventsReadVal {
         #[doc = "USB aon wake module is active, monitoring events and controlling the pull-ups."]
         #[inline(always)]
-        pub fn module_active(&self) -> bool {
+        pub const fn module_active(&self) -> bool {
             ((self.0 >> 0) & 1) != 0
         }
         #[doc = "USB aon wake module detected VBUS was interrupted while monitoring events."]
         #[inline(always)]
-        pub fn disconnected(&self) -> bool {
+        pub const fn disconnected(&self) -> bool {
             ((self.0 >> 8) & 1) != 0
         }
         #[doc = "USB aon wake module detected a bus reset while monitoring events."]
         #[inline(always)]
-        pub fn bus_reset(&self) -> bool {
+        pub const fn bus_reset(&self) -> bool {
             ((self.0 >> 9) & 1) != 0
         }
         #[doc = "USB aon wake module detected a non-idle bus while monitoring events."]
         #[inline(always)]
-        pub fn bus_not_idle(&self) -> bool {
+        pub const fn bus_not_idle(&self) -> bool {
             ((self.0 >> 10) & 1) != 0
         }
     }
@@ -3665,16 +4064,19 @@ pub mod enums {
         pub fn resuming(&self) -> bool {
             *self == Self::Resuming
         }
+        pub const fn from_raw(val: u32) -> Option<LinkState> {
+            if val < 8 {
+                Some(unsafe { core::mem::transmute::<u32, LinkState>(val) })
+            } else {
+                None
+            }
+        }
     }
     impl TryFrom<u32> for LinkState {
         type Error = ();
         #[inline(always)]
         fn try_from(val: u32) -> Result<LinkState, ()> {
-            if val < 8 {
-                Ok(unsafe { core::mem::transmute::<u32, LinkState>(val) })
-            } else {
-                Err(())
-            }
+            LinkState::from_raw(val).ok_or(())
         }
     }
     impl From<LinkState> for u32 {
diff --git a/target/earlgrey/tests/usbdev/BUILD.bazel b/target/earlgrey/tests/usbdev/BUILD.bazel
new file mode 100644
index 00000000..6e1955d4
--- /dev/null
+++ b/target/earlgrey/tests/usbdev/BUILD.bazel
@@ -0,0 +1,139 @@
+# Licensed under the Apache-2.0 license
+# SPDX-License-Identifier: Apache-2.0
+
+load("@pigweed//pw_kernel/tooling:app_package.bzl", "app_package")
+load("@pigweed//pw_kernel/tooling:system_image.bzl", "system_image")
+load("@pigweed//pw_kernel/tooling:target_codegen.bzl", "target_codegen")
+load("@pigweed//pw_kernel/tooling:target_linker_script.bzl", "target_linker_script")
+load("@rules_rust//rust:defs.bzl", "rust_binary")
+load("//target/earlgrey:defs.bzl", "TARGET_COMPATIBLE_WITH")
+load("//target/earlgrey/signing/keys:defs.bzl", "FPGA_ECDSA_KEY", "SILICON_ECDSA_KEY")
+load("//target/earlgrey/tooling:opentitan_runner.bzl", "opentitan_test")
+
+rust_binary(
+    name = "test_usb",
+    srcs = [
+        "test_usb.rs",
+    ],
+    crate_features = ["trace"],
+    edition = "2024",
+    tags = ["kernel"],
+    visibility = ["//visibility:public"],
+    deps = [
+        ":app_test_usb",
+        "//hal/blocking/usb:hal_usb",
+        "//protocol/usb/stack",
+        "//target/earlgrey/drivers:usb_driver",
+        "//target/earlgrey/registers:pinmux",
+        "//target/earlgrey/registers:top_earlgrey",
+        "//target/earlgrey/registers:usbdev",
+        "//util/console",
+        "//util/error",
+        "@pigweed//pw_kernel/userspace",
+        "@pigweed//pw_log/rust:pw_log",
+        "@pigweed//pw_status/rust:pw_status",
+        "@rust_crates//:aligned",
+    ],
+)
+
+app_package(
+    name = "app_test_usb",
+    app_name = "test_usb",
+    edition = "2024",
+    system_config = "@pigweed//pw_kernel/target:system_config_file",
+    tags = ["kernel"],
+)
+
+system_image(
+    name = "usb",
+    apps = [
+        ":test_usb",
+    ],
+    kernel = ":target",
+    platform = "//target/earlgrey",
+    system_config = ":system_config",
+    tags = ["kernel"],
+)
+
+target_linker_script(
+    name = "linker_script",
+    system_config = ":system_config",
+    tags = ["kernel"],
+    template = "//target/earlgrey:linker_script_template",
+)
+
+filegroup(
+    name = "system_config",
+    srcs = ["system.json5"],
+)
+
+target_codegen(
+    name = "codegen",
+    arch = "@pigweed//pw_kernel/arch/riscv:arch_riscv",
+    system_config = ":system_config",
+)
+
+rust_binary(
+    name = "target",
+    srcs = [
+        "target.rs",
+    ],
+    edition = "2024",
+    tags = ["kernel"],
+    target_compatible_with = TARGET_COMPATIBLE_WITH,
+    deps = [
+        ":codegen",
+        ":linker_script",
+        "//target/earlgrey:entry",
+        "@pigweed//pw_kernel/arch/riscv:arch_riscv",
+        "@pigweed//pw_kernel/kernel",
+        "@pigweed//pw_kernel/subsys/console:console_backend",
+        "@pigweed//pw_kernel/target:target_common",
+        "@pigweed//pw_kernel/userspace",
+        "@pigweed//pw_log/rust:pw_log",
+    ],
+)
+
+opentitan_test(
+    name = "usb_verilator_test",
+    timeout = "eternal",
+    interface = "verilator",
+    tags = [
+        "nightly_test",
+        "verilator",
+    ],
+    target = ":usb",
+)
+
+opentitan_test(
+    name = "usb_hyper310_test",
+    ecdsa_key = FPGA_ECDSA_KEY,
+    interface = "hyper310",
+    tags = [
+        "hardware",
+        "hyper310",
+    ],
+    target = ":usb",
+)
+
+opentitan_test(
+    name = "usb_hyper340_test",
+    ecdsa_key = FPGA_ECDSA_KEY,
+    interface = "hyper340",
+    tags = [
+        "hardware",
+        "hyper340",
+    ],
+    target = ":usb",
+)
+
+opentitan_test(
+    name = "usb_silicon_test",
+    ecdsa_key = SILICON_ECDSA_KEY,
+    interface = "teacup",
+    tags = [
+        "earlgrey_silicon",
+        "hardware",
+    ],
+    target = ":usb",
+)
diff --git a/target/earlgrey/tests/usbdev/system.json5 b/target/earlgrey/tests/usbdev/system.json5
new file mode 100644
index 00000000..e6dccb91
--- /dev/null
+++ b/target/earlgrey/tests/usbdev/system.json5
@@ -0,0 +1,77 @@
+// Licensed under the Apache-2.0 license
+// SPDX-License-Identifier: Apache-2.0
+{
+  arch: {
+    type: "riscv",
+  },
+  kernel: {
+    flash_start_address: 0xA0010000,
+    flash_size_bytes: 65536,
+    ram_start_address: 0x10000000,
+    ram_size_bytes: 32768,
+    interrupt_table: {
+      table: {}
+    },
+  },
+  apps: [
+    {
+      name: "test_usb",
+      flash_size_bytes: 16384,
+      ram_size_bytes: 4096,
+      process: {
+        name: "test_uart_listener process",
+        objects: [
+          {
+            name: "usbdev_interrupts",
+            type: "interrupt",
+            irqs: [
+                { name: "usbdev_pkt_received", number: 135 },
+                { name: "usbdev_pkt_sent", number: 136 },
+                { name: "usbdev_disconnected", number: 137 },
+                { name: "usbdev_host_lost", number: 138 },
+
+                { name: "usbdev_link_reset", number: 139 },
+                { name: "usbdev_link_suspend", number: 140 },
+                { name: "usbdev_link_resume", number: 141 },
+                { name: "usbdev_av_out_empty", number: 142 },
+
+                { name: "usbdev_rx_full", number: 143 },
+                { name: "usbdev_av_overflow", number: 144 },
+                //{ name: "usbdev_link_in_err", number: 145 },
+                { name: "usbdev_rx_crc_err", number: 146 },
+
+                { name: "usbdev_rx_pid_err", number: 147 },
+                { name: "usbdev_rx_bitstuff_err", number: 148 },
+                { name: "usbdev_frame", number: 149 },
+                //{ name: "usbdev_powered", number: 150 },
+
+                //{ name: "usbdev_link_out_err", number: 151 },
+                { name: "usbdev_av_setup_empty", number: 152 },
+            ],
+          },
+        ],
+        memory_mappings: [
+          {
+            name: "usbdev",
+            type: "device",
+            start_address: 0x40320000,
+            size_bytes: 0x1000,
+          },
+          {
+            name: "pinmux",
+            type: "device",
+            start_address: 0x40460000,
+            size_bytes: 0x1000,
+          }
+
+        ],
+        threads: [
+          {
+            name: "usb thread",
+            stack_size_bytes: 2048,
+          },
+        ],
+      },
+    },
+  ],
+}
diff --git a/target/earlgrey/tests/usbdev/target.rs b/target/earlgrey/tests/usbdev/target.rs
new file mode 100644
index 00000000..2e253d37
--- /dev/null
+++ b/target/earlgrey/tests/usbdev/target.rs
@@ -0,0 +1,29 @@
+// Licensed under the Apache-2.0 license
+// SPDX-License-Identifier: Apache-2.0
+
+#![no_std]
+#![no_main]
+use target_common::{declare_target, TargetInterface};
+use {console_backend as _, entry as _};
+
+pub struct Target {}
+
+impl TargetInterface for Target {
+    const NAME: &'static str = "Earlgrey Userspace UART";
+
+    fn main() -> ! {
+        codegen::start();
+        loop {}
+    }
+
+    fn shutdown(code: u32) -> ! {
+        pw_log::info!("Shutting down with code {}", code as u32);
+        match code {
+            0 => pw_log::info!("PASS"),
+            _ => pw_log::info!("FAIL: {}", code as u32),
+        };
+        loop {}
+    }
+}
+
+declare_target!(Target);
diff --git a/target/earlgrey/tests/usbdev/test_usb.rs b/target/earlgrey/tests/usbdev/test_usb.rs
new file mode 100644
index 00000000..490a46c0
--- /dev/null
+++ b/target/earlgrey/tests/usbdev/test_usb.rs
@@ -0,0 +1,225 @@
+// Licensed under the Apache-2.0 license
+// SPDX-License-Identifier: Apache-2.0
+
+#![no_std]
+#![no_main]
+use app_test_usb::{handle, signals};
+use util_error::{ErrorCode, KERNEL_ERROR_UNKNOWN};
+//use userspace::syscall::Signals;
+use userspace::time::Instant;
+use userspace::{entry, syscall};
+
+use aligned::{Aligned, A4};
+use hal_usb::driver::{UsbDriver, UsbEvent, UsbPacket};
+use hal_usb::{Direction, StringDescriptorRef, USB_CLASS_VENDOR};
+use usb_driver::{EpIn, EpOut, UsbConfig};
+use usb_stack::{
+    //UsbActionRun,
+    DescriptorSource,
+    UsbAction,
+};
+
+const USB_VENDOR_HANDLE: hal_usb::StringHandle = hal_usb::StringHandle(1);
+const USB_PRODUCT_HANDLE: hal_usb::StringHandle = hal_usb::StringHandle(2);
+const USB_SERIAL_HANDLE: hal_usb::StringHandle = hal_usb::StringHandle(3);
+const USB_TEST_HANDLE: hal_usb::StringHandle = hal_usb::StringHandle(4);
+
+static DEVICE_DESC: hal_usb::DeviceDescriptor = hal_usb::DeviceDescriptor {
+    device_class: hal_usb::DeviceClass::SPECIFIED_BY_INTERFACE,
+    device_sub_class: 0x00,
+    device_protocol: 0x00,
+    max_packet_size: 64,
+    vendor_id: 0x18d1,
+    product_id: 0x023b,
+    device_release_num: 0x0100,
+    manufacturer: USB_VENDOR_HANDLE,
+    product: USB_PRODUCT_HANDLE,
+    serial_num: USB_SERIAL_HANDLE,
+};
+const CONFIG_DESC: hal_usb::ConfigDescriptor = hal_usb::ConfigDescriptor {
+    configuration_value: 1,
+    max_power: 250,
+    self_powered: false,
+    remote_wakeup: false,
+    interfaces: &[hal_usb::InterfaceDescriptor {
+        name: USB_TEST_HANDLE,
+        interface_number: 1,
+        alternate_setting: 0,
+        interface_class: USB_CLASS_VENDOR,
+        interface_sub_class: 0xFF,
+        interface_protocol: 1,
+        func_descs: &[],
+        endpoints: &[
+            hal_usb::EndpointDescriptor {
+                direction: Direction::DeviceToHost,
+                endpoint_num: 1,
+                interval: 0,
+                max_packet_size: 64,
+                transfer_type: hal_usb::TransferType::Bulk,
+            },
+            hal_usb::EndpointDescriptor {
+                direction: Direction::HostToDevice,
+                endpoint_num: 2,
+                interval: 0,
+                max_packet_size: 64,
+                transfer_type: hal_usb::TransferType::Bulk,
+            },
+        ],
+    }],
+};
+
+const STRING_DESC_0: hal_usb::StringDescriptor0 = hal_usb::StringDescriptor0 {
+    langs: &[
+        // English - United States
+        0x0409,
+    ],
+};
+
+const VENDOR_ID: hal_usb::StringDescriptorRef = hal_usb::string_descriptor!("Google Inc.").as_ref();
+const PRODUCT_ID_DEFAULT: hal_usb::StringDescriptorRef =
+    hal_usb::string_descriptor!("Earlgrey").as_ref();
+const USB_TEST: hal_usb::StringDescriptorRef =
+    hal_usb::string_descriptor!("USB Test Interface").as_ref();
+
+struct MyDescriptors<'a> {
+    serial_desc_bytes: StringDescriptorRef<'a>,
+    product_desc_bytes: StringDescriptorRef<'a>,
+}
+
+impl DescriptorSource for MyDescriptors<'_> {
+    const DEVICE_DESC_BYTES: &'static Aligned<A4, [u8]> = &Aligned(DEVICE_DESC.serialize());
+    const CONFIG_DESC_BYTES: &'static Aligned<A4, [u8]> =
+        &Aligned(CONFIG_DESC.serialize::<{ CONFIG_DESC.total_size() }>());
+    const STRING_DESC_0_BYTES: &'static Aligned<A4, [u8]> =
+        &Aligned(STRING_DESC_0.serialize::<{ STRING_DESC_0.total_size() }>());
+
+    fn get_string(
+        &self,
+        handle: hal_usb::StringHandle,
+        _lang: u16,
+    ) -> Option<hal_usb::StringDescriptorRef<'_>> {
+        match handle {
+            USB_VENDOR_HANDLE => Some(VENDOR_ID),
+            USB_PRODUCT_HANDLE => Some(self.product_desc_bytes),
+            USB_SERIAL_HANDLE => Some(self.serial_desc_bytes),
+            USB_TEST_HANDLE => Some(USB_TEST),
+            _ => None,
+        }
+    }
+}
+
+const CONTROL_EP_OUT_NUM: u8 = 0;
+
+fn handle_usb() -> Result<(), ErrorCode> {
+    let mut serial_num_buffer = Aligned::<A4, _>([0_u8; 130]);
+    // TODO
+    //let mut product_desc_buffer = Aligned::<A4, _>([0_u8; 100]);
+    let descriptors = MyDescriptors {
+        serial_desc_bytes: hal_usb::hex_utf16_descriptor_aligned(&mut serial_num_buffer, b"12345")
+            .unwrap(),
+        product_desc_bytes: PRODUCT_ID_DEFAULT,
+    };
+    const USB_EP_IN: EpIn = EpIn {
+        num: 1,
+        buf_pool_size: 8,
+    };
+    const USB_EP_OUT: EpOut = EpOut {
+        num: 2,
+        set_nak: true,
+    };
+
+    const USB_CONFIG: UsbConfig = UsbConfig::new(&[USB_EP_IN], &[USB_EP_OUT]);
+    let mut usb = usb_driver::Usb::new(unsafe { usbdev::Usbdev::new() }, USB_CONFIG);
+    let mut ep0 = usb_stack::SimpleEp0::new();
+    let mut ep0_action: UsbAction<'_> = UsbAction::None;
+
+    loop {
+        let wait_return = syscall::object_wait(
+            handle::USBDEV_INTERRUPTS,
+            signals::USBDEV_PKT_RECEIVED
+                | signals::USBDEV_PKT_SENT
+                | signals::USBDEV_DISCONNECTED
+                | signals::USBDEV_HOST_LOST
+                | signals::USBDEV_LINK_RESET
+                | signals::USBDEV_LINK_SUSPEND
+                | signals::USBDEV_LINK_RESUME
+                | signals::USBDEV_AV_OUT_EMPTY
+                | signals::USBDEV_RX_FULL
+                | signals::USBDEV_AV_OVERFLOW
+                //| signals::USBDEV_LINK_IN_ERR
+                | signals::USBDEV_RX_CRC_ERR
+                | signals::USBDEV_RX_PID_ERR
+                | signals::USBDEV_RX_BITSTUFF_ERR
+                | signals::USBDEV_FRAME
+                //| signals::USBDEV_POWERED
+                //| signals::USBDEV_LINK_OUT_ERR
+                | signals::USBDEV_AV_SETUP_EMPTY,
+            Instant::MAX,
+        )?;
+
+        if wait_return.user_data != 0 {
+            pw_log::error!("Incorrect WaitReturn values");
+            return Err(KERNEL_ERROR_UNKNOWN);
+        }
+        while let Some(event) = usb.poll() {
+            match event {
+                UsbEvent::SetupPacket { pkt, endpoint } => {
+                    if endpoint == 0 {
+                        console::println!("SETUP: {:?}", pkt);
+                        ep0_action = ep0.handle_event(event, &descriptors);
+                    } else {
+                        console::println!("Setup on bad EP {:?}", endpoint);
+                    }
+                }
+
+                UsbEvent::DataOutPacket(pkt) => match u8::try_from(pkt.endpoint_index()).unwrap() {
+                    CONTROL_EP_OUT_NUM => {
+                        console::println!("OUT on control ep");
+                    }
+                    ep => {
+                        console::println!("Unhandled OUT on EP {} len={}", ep, pkt.len());
+                    }
+                },
+                UsbEvent::UsbReset => {
+                    console::println!("USB reset");
+                }
+                _ => {
+                    ep0_action.merge(ep0.handle_event(event, &descriptors));
+                }
+            }
+            ep0_action.run(&mut usb);
+        }
+    }
+}
+
+fn usb_setup_pinmux() {
+    use top_earlgrey::{PinmuxInsel, PinmuxPeripheralIn};
+    let mut pinmux = unsafe { pinmux::PinmuxAon::new() };
+
+    pinmux
+        .regs_mut()
+        .mio_periph_insel()
+        .at(PinmuxPeripheralIn::UsbdevSense as usize)
+        .modify(|_| (PinmuxInsel::ConstantOne as u32).into());
+}
+
+#[entry]
+fn entry() -> ! {
+    // Since this is written as a test, shut down with the return status from `main()`.
+    usb_setup_pinmux();
+    let ret = match handle_usb() {
+        Ok(()) => Ok(()),
+        Err(e) => {
+            pw_log::error!("Error {:x}", e.0.get());
+            Err(pw_status::Error::Unknown)
+        }
+    };
+    let _ = syscall::debug_shutdown(ret);
+    loop {}
+}
+
+#[panic_handler]
+fn panic(_info: &core::panic::PanicInfo) -> ! {
+    pw_log::error!("FAIL: panic in {}", module_path!() as &str);
+    loop {}
+}
diff --git a/third_party/crates_io/Cargo.lock b/third_party/crates_io/Cargo.lock
index 5e69e671..e32757ef 100644
--- a/third_party/crates_io/Cargo.lock
+++ b/third_party/crates_io/Cargo.lock
@@ -43,6 +43,15 @@ dependencies = [
  "subtle",
 ]
 
+[[package]]
+name = "aligned"
+version = "0.4.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ee4508988c62edf04abd8d92897fca0c2995d907ce1dfeaf369dac3716a40685"
+dependencies = [
+ "as-slice",
+]
+
 [[package]]
 name = "anstream"
 version = "0.6.21"
@@ -99,6 +108,15 @@ version = "1.0.102"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "7f202df86484c868dbad7eaa557ef785d5c66295e41b460ef922eca0723b842c"
 
+[[package]]
+name = "as-slice"
+version = "0.2.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "516b6b4f0e40d50dcda9365d53964ec74560ad4284da2e7fc97122cd83174516"
+dependencies = [
+ "stable_deref_trait",
+]
+
 [[package]]
 name = "bare-metal"
 version = "0.2.5"
@@ -128,7 +146,7 @@ checksum = "d3ca019570363e800b05ad4fd890734f28ac7b72f563ad8a35079efb793616f8"
 dependencies = [
  "proc-macro2",
  "quote",
- "syn",
+ "syn 2.0.116",
 ]
 
 [[package]]
@@ -199,7 +217,7 @@ dependencies = [
  "heck",
  "proc-macro2",
  "quote",
- "syn",
+ "syn 2.0.116",
 ]
 
 [[package]]
@@ -718,7 +736,7 @@ dependencies = [
  "pest_meta",
  "proc-macro2",
  "quote",
- "syn",
+ "syn 2.0.116",
 ]
 
 [[package]]
@@ -836,7 +854,7 @@ checksum = "f265be5d634272320a7de94cea15c22a3bfdd4eb42eb43edc528415f066a1f25"
 dependencies = [
  "proc-macro2",
  "quote",
- "syn",
+ "syn 2.0.116",
 ]
 
 [[package]]
@@ -847,7 +865,7 @@ checksum = "e8c4aa1ea1af6dcc83a61be12e8189f9b293c3ba5a487778a4cd89fb060fdbbc"
 dependencies = [
  "proc-macro2",
  "quote",
- "syn",
+ "syn 2.0.116",
 ]
 
 [[package]]
@@ -874,7 +892,7 @@ checksum = "30f19a85fe107b65031e0ba8ec60c34c2494069fe910d6c297f5e7cb5a6f76d0"
 dependencies = [
  "proc-macro2",
  "quote",
- "syn",
+ "syn 2.0.116",
 ]
 
 [[package]]
@@ -893,6 +911,7 @@ version = "0.1.0"
 dependencies = [
  "aes",
  "aes-gcm",
+ "aligned",
  "anyhow",
  "bitfield-struct",
  "bitflags",
@@ -930,8 +949,9 @@ dependencies = [
  "sha2",
  "sha3",
  "subtle",
- "syn",
+ "syn 2.0.116",
  "toml",
+ "ufmt",
  "zerocopy",
  "zeroize",
 ]
@@ -1021,7 +1041,7 @@ checksum = "d540f220d3187173da220f885ab66608367b6574e925011a9353e4badda91d79"
 dependencies = [
  "proc-macro2",
  "quote",
- "syn",
+ "syn 2.0.116",
 ]
 
 [[package]]
@@ -1099,6 +1119,17 @@ version = "2.6.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "13c2bddecc57b384dee18652358fb23172facb8a2c51ccc10d74c157bdea3292"
 
+[[package]]
+name = "syn"
+version = "1.0.109"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "72b64191b275b66ffe2469e8af2c1cfe3bafa67b529ead792a6d0160888b4237"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "unicode-ident",
+]
+
 [[package]]
 name = "syn"
 version = "2.0.116"
@@ -1169,6 +1200,33 @@ version = "0.1.7"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "2896d95c02a80c6d6a5d6e953d479f5ddf2dfdb6a244441010e373ac0fb88971"
 
+[[package]]
+name = "ufmt"
+version = "0.2.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "1a64846ec02b57e9108d6469d98d1648782ad6bb150a95a9baac26900bbeab9d"
+dependencies = [
+ "ufmt-macros",
+ "ufmt-write",
+]
+
+[[package]]
+name = "ufmt-macros"
+version = "0.3.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d337d3be617449165cb4633c8dece429afd83f84051024079f97ad32a9663716"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn 1.0.109",
+]
+
+[[package]]
+name = "ufmt-write"
+version = "0.1.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "e87a2ed6b42ec5e28cc3b94c09982969e9227600b2e3dcbc1db927a84c06bd69"
+
 [[package]]
 name = "unicode-ident"
 version = "1.0.24"
@@ -1259,7 +1317,7 @@ checksum = "4122cd3169e94605190e77839c9a40d40ed048d305bfdc146e7df40ab0f3e517"
 dependencies = [
  "proc-macro2",
  "quote",
- "syn",
+ "syn 2.0.116",
 ]
 
 [[package]]
@@ -1279,5 +1337,5 @@ checksum = "85a5b4158499876c763cb03bc4e49185d3cccbabb15b33c627f7884f43db852e"
 dependencies = [
  "proc-macro2",
  "quote",
- "syn",
+ "syn 2.0.116",
 ]
diff --git a/third_party/crates_io/Cargo.toml b/third_party/crates_io/Cargo.toml
index a585102c..a579a90f 100644
--- a/third_party/crates_io/Cargo.toml
+++ b/third_party/crates_io/Cargo.toml
@@ -11,6 +11,7 @@ license = "Apache-2.0"
 path = "fake.rs"
 
 [dependencies]
+aligned = "0.4.3"
 anyhow = "1.0.98"
 bitfield-struct = "0.11.0"
 bitflags = "2.9.1"
@@ -34,6 +35,7 @@ serde = { version = "1.0.219", features = ["derive"] }
 serde_json5 = "0.2.1"
 syn = { version = "2.0.104", features = ["full", "extra-traits"] }
 toml = "0.8.23"
+ufmt = "0.2.0"
 
 cortex-m = "0.7.7"
 embedded-hal = "1.0"
diff --git a/util/console/BUILD.bazel b/util/console/BUILD.bazel
new file mode 100644
index 00000000..36d299eb
--- /dev/null
+++ b/util/console/BUILD.bazel
@@ -0,0 +1,46 @@
+# Licensed under the Apache-2.0 license
+# SPDX-License-Identifier: Apache-2.0
+
+load("@rules_rust//rust:defs.bzl", "rust_doc", "rust_library")
+
+package(default_visibility = ["//visibility:public"])
+
+rust_library(
+    name = "console",
+    srcs = [
+        "lib.rs",
+    ],
+    edition = "2024",
+    deps = [
+        "@rust_crates//:ufmt",
+    ] + select({
+        "@platforms//os:none": [":pigweed"],
+        "//conditions:default": [":stdout"],
+    }),
+)
+
+rust_doc(
+    name = "console_doc",
+    crate = ":console",
+)
+
+rust_library(
+    name = "stdout",
+    srcs = [
+        "stdout.rs",
+    ],
+    crate_name = "console_stdout",
+    edition = "2024",
+)
+
+rust_library(
+    name = "pigweed",
+    srcs = [
+        "pigweed.rs",
+    ],
+    crate_name = "console_pigweed",
+    edition = "2024",
+    deps = [
+        "@pigweed//pw_kernel/userspace",
+    ],
+)
diff --git a/util/console/lib.rs b/util/console/lib.rs
new file mode 100644
index 00000000..5f112b8c
--- /dev/null
+++ b/util/console/lib.rs
@@ -0,0 +1,70 @@
+// Licensed under the Apache-2.0 license
+// SPDX-License-Identifier: Apache-2.0
+
+//! Console
+//!
+//! This crate provides basic console functionality.
+
+#![no_std]
+
+use core::convert::Infallible;
+
+pub use ufmt;
+use ufmt::uWrite;
+pub use ufmt::{uwrite, uwriteln};
+
+pub struct Console;
+
+#[cfg(target_os = "none")]
+use console_pigweed::system_lowlevel_console_write;
+#[cfg(not(target_os = "none"))]
+use console_stdout::system_lowlevel_console_write;
+
+//unsafe extern "Rust" {
+//    fn system_lowlevel_console_write(bytes: &[u8]);
+//}
+
+impl uWrite for Console {
+    type Error = Infallible;
+
+    fn write_str(&mut self, s: &str) -> Result<(), Infallible> {
+        system_lowlevel_console_write(s.as_bytes());
+        Ok(())
+    }
+}
+
+#[macro_export]
+macro_rules! print {
+    ($($arg:tt)*) => {{
+        use $crate::ufmt;
+        $crate::uwrite!(&mut $crate::Console, $($arg)*).unwrap();
+    }};
+}
+
+#[macro_export]
+macro_rules! println {
+    ($($arg:tt)*) => {{
+        use $crate::ufmt;
+        $crate::ufmt::uwriteln!(&mut $crate::Console, $($arg)*).unwrap();
+    }};
+}
+
+#[macro_export]
+macro_rules! trace {
+    ($($arg:tt)*) => {
+        if cfg!(feature = "trace") {
+            use $crate::ufmt;
+            $crate::uwrite!(&mut $crate::Console, $($arg)*).unwrap();
+        }
+    };
+}
+
+#[macro_export]
+macro_rules! traceln {
+    ($($arg:tt)*) => {
+        if cfg!(feature = "trace") {
+            use $crate::ufmt;
+            $crate::uwriteln!(&mut $crate::Console, $($arg)*).unwrap();
+        }
+    };
+}
diff --git a/util/console/pigweed.rs b/util/console/pigweed.rs
new file mode 100644
index 00000000..50db03c6
--- /dev/null
+++ b/util/console/pigweed.rs
@@ -0,0 +1,11 @@
+// Licensed under the Apache-2.0 license
+// SPDX-License-Identifier: Apache-2.0
+
+#![no_std]
+
+use userspace::syscall;
+
+#[unsafe(no_mangle)]
+pub fn system_lowlevel_console_write(bytes: &[u8]) {
+    let _ = syscall::debug_log(bytes);
+}
diff --git a/util/console/stdout.rs b/util/console/stdout.rs
new file mode 100644
index 00000000..cfa54959
--- /dev/null
+++ b/util/console/stdout.rs
@@ -0,0 +1,10 @@
+// Licensed under the Apache-2.0 license
+// SPDX-License-Identifier: Apache-2.0
+
+use std::io::Write;
+
+#[unsafe(no_mangle)]
+extern "Rust" fn system_lowlevel_console_write(bytes: &[u8]) {
+    let _ = std::io::stdout().write_all(bytes);
+    let _ = std::io::stdout().flush();
+}
diff --git a/util/error/BUILD.bazel b/util/error/BUILD.bazel
new file mode 100644
index 00000000..af2e6dec
--- /dev/null
+++ b/util/error/BUILD.bazel
@@ -0,0 +1,24 @@
+# Licensed under the Apache-2.0 license
+# SPDX-License-Identifier: Apache-2.0
+
+load("@rules_rust//rust:defs.bzl", "rust_doc", "rust_library")
+
+package(default_visibility = ["//visibility:public"])
+
+rust_library(
+    name = "error",
+    srcs = [
+        "lib.rs",
+    ],
+    crate_name = "util_error",
+    edition = "2024",
+    deps = [
+        "@pigweed//pw_status/rust:pw_status",
+        "@rust_crates//:ufmt",
+    ],
+)
+
+rust_doc(
+    name = "error_doc",
+    crate = ":error",
+)
diff --git a/util/error/lib.rs b/util/error/lib.rs
new file mode 100644
index 00000000..a13ca774
--- /dev/null
+++ b/util/error/lib.rs
@@ -0,0 +1,90 @@
+#![no_std]
+
+use core::num::NonZero;
+
+use ufmt::{uDebug, uDisplay, uwrite};
+
+#[derive(Clone, Copy, PartialEq, Eq)]
+#[repr(transparent)]
+pub struct ErrorModule(pub NonZero<u16>);
+
+impl ErrorModule {
+    pub const fn new(val: u16) -> Self {
+        match NonZero::new(val) {
+            Some(val) => Self(val),
+            None => panic!("ErrorModule must be non-zero"),
+        }
+    }
+
+    pub const fn error(self, code: u16) -> ErrorCode {
+        ErrorCode::new(((self.0.get() as u32) << 16) | (code as u32))
+    }
+}
+
+#[derive(Clone, Copy, PartialEq, Eq)]
+#[repr(transparent)]
+pub struct ErrorCode(pub NonZero<u32>);
+impl ErrorCode {
+    pub const fn new(val: u32) -> Self {
+        match NonZero::new(val) {
+            Some(val) => Self(val),
+            None => panic!("ErrorCode must be non-zero"),
+        }
+    }
+}
+
+impl uDisplay for ErrorCode {
+    fn fmt<W>(&self, f: &mut ufmt::Formatter<'_, W>) -> Result<(), W::Error>
+    where
+        W: ufmt::uWrite + ?Sized,
+    {
+        uwrite!(f, "0x{:x}", self.0.get())
+    }
+}
+
+impl uDebug for ErrorCode {
+    fn fmt<W>(&self, f: &mut ufmt::Formatter<'_, W>) -> Result<(), W::Error>
+    where
+        W: ufmt::uWrite + ?Sized,
+    {
+        uDisplay::fmt(self, f)
+    }
+}
+
+impl core::fmt::Display for ErrorCode {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "0x{:x}", self.0.get())
+    }
+}
+
+impl core::fmt::Debug for ErrorCode {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Display::fmt(self, f)
+    }
+}
+
+impl core::error::Error for ErrorCode {}
+
+pub const KERNEL_ERROR: ErrorModule = ErrorModule::new(0x4b45); // ascii `KE`
+pub const KERNEL_ERROR_CANCELLED: ErrorCode = KERNEL_ERROR.error(1);
+pub const KERNEL_ERROR_UNKNOWN: ErrorCode = KERNEL_ERROR.error(2);
+pub const KERNEL_ERROR_INVALID_ARGUMENT: ErrorCode = KERNEL_ERROR.error(3);
+pub const KERNEL_ERROR_DEADLINE_EXCEEDED: ErrorCode = KERNEL_ERROR.error(4);
+pub const KERNEL_ERROR_NOT_FOUND: ErrorCode = KERNEL_ERROR.error(5);
+pub const KERNEL_ERROR_ALREADY_EXISTS: ErrorCode = KERNEL_ERROR.error(6);
+pub const KERNEL_ERROR_PERMISSION_DENIED: ErrorCode = KERNEL_ERROR.error(7);
+pub const KERNEL_ERROR_RESOURCE_EXHAUSTED: ErrorCode = KERNEL_ERROR.error(8);
+pub const KERNEL_ERROR_FAILED_PRECONDITION: ErrorCode = KERNEL_ERROR.error(9);
+pub const KERNEL_ERROR_ABORTED: ErrorCode = KERNEL_ERROR.error(10);
+pub const KERNEL_ERROR_OUT_OF_RANGE: ErrorCode = KERNEL_ERROR.error(11);
+pub const KERNEL_ERROR_UNIMPLEMENTED: ErrorCode = KERNEL_ERROR.error(12);
+pub const KERNEL_ERROR_INTERNAL: ErrorCode = KERNEL_ERROR.error(13);
+pub const KERNEL_ERROR_UNAVAILABLE: ErrorCode = KERNEL_ERROR.error(14);
+pub const KERNEL_ERROR_DATA_LOSS: ErrorCode = KERNEL_ERROR.error(15);
+pub const KERNEL_ERROR_UNAUTHENTICATED: ErrorCode = KERNEL_ERROR.error(16);
+
+impl From<pw_status::Error> for ErrorCode {
+    fn from(err: pw_status::Error) -> Self {
+        KERNEL_ERROR.error(err as u16)
+    }
+}
diff --git a/util/regcpy/BUILD.bazel b/util/regcpy/BUILD.bazel
new file mode 100644
index 00000000..cb51c2e9
--- /dev/null
+++ b/util/regcpy/BUILD.bazel
@@ -0,0 +1,26 @@
+load("@rules_rust//rust:defs.bzl", "rust_library", "rust_test")
+
+rust_library(
+    name = "regcpy",
+    srcs = [
+        "regcpy.rs",
+    ],
+    crate_name = "util_regcpy",
+    edition = "2024",
+    visibility = ["//visibility:public"],
+    deps = [
+        "@rust_crates//:aligned",
+        "@rust_crates//:zerocopy",
+        "@ureg",
+    ],
+)
+
+rust_test(
+    name = "regcpy_test",
+    crate = ":regcpy",
+    edition = "2024",
+    rustc_flags = [
+        "-C",
+        "debug-assertions",
+    ],
+)
diff --git a/util/regcpy/regcpy.rs b/util/regcpy/regcpy.rs
new file mode 100644
index 00000000..2f8be1e2
--- /dev/null
+++ b/util/regcpy/regcpy.rs
@@ -0,0 +1,740 @@
+#![cfg_attr(not(test), no_std)]
+
+// TODO: should this be upstreamed into ureg?
+
+use aligned::Aligned;
+use aligned::A4;
+use core::cmp::min;
+use zerocopy::FromBytes;
+use zerocopy::Unalign;
+
+#[inline(never)]
+pub fn copy_to_reg_unaligned(
+    reg: &ureg::RegRef<
+        impl ureg::WritableReg<WriteVal = u32, Raw = u32> + ureg::ResettableReg<Raw = u32>,
+        impl ureg::MmioMut + Copy,
+    >,
+    src: &[u8],
+) {
+    let (words, rem_bytes): (&[Unalign<u32>], &[u8]) = FromBytes::ref_from_prefix(src).unwrap();
+
+    for word in words {
+        reg.write(|_| word.get());
+    }
+    if let Some(last_word) = last_word(rem_bytes) {
+        reg.write(|_| last_word);
+    }
+}
+
+#[inline(never)]
+pub fn copy_to_reg(
+    reg: &ureg::RegRef<
+        impl ureg::WritableReg<WriteVal = u32, Raw = u32> + ureg::ResettableReg<Raw = u32>,
+        impl ureg::MmioMut + Copy,
+    >,
+    src: &Aligned<A4, [u8]>,
+) {
+    // Convert to regular slice; optimizer should be smart enough to realize it's still aligned.
+    let (words, rem_bytes): (&[u32], &[u8]) = FromBytes::ref_from_prefix(src.as_ref()).unwrap();
+
+    for word in words {
+        reg.write(|_| *word);
+    }
+    if let Some(last_word) = last_word(rem_bytes) {
+        reg.write(|_| last_word);
+    }
+}
+
+#[inline(never)]
+pub fn copy_to_reg_array<const LEN: usize>(
+    array: &ureg::Array<
+        LEN,
+        ureg::RegRef<
+            impl ureg::WritableReg<WriteVal = u32, Raw = u32> + ureg::ResettableReg<Raw = u32>,
+            impl ureg::MmioMut + Copy,
+        >,
+    >,
+    src: &Aligned<A4, [u8]>,
+) {
+    // Convert to regular slice; optimizer should be smart enough to realize it's still aligned.
+    let (words, rem_bytes): (&[u32], &[u8]) = FromBytes::ref_from_prefix(src.as_ref()).unwrap();
+
+    let words_to_copy = min(LEN, words.len());
+
+    #[allow(clippy::needless_range_loop)] // optimizes better
+    for i in 0..words_to_copy {
+        array.at(i).write(|_| words[i]);
+    }
+    let Some(reg) = array.get(words.len()) else {
+        return;
+    };
+    let Some(last_word) = last_word(rem_bytes) else {
+        return;
+    };
+    reg.write(|_| last_word);
+}
+
+#[inline(never)]
+pub fn copy_from_reg<const LEN: usize>(
+    dest: &mut Aligned<A4, [u8]>,
+    reg: &ureg::RegRef<impl ureg::ReadableReg<ReadVal = u32, Raw = u32>, impl ureg::Mmio + Copy>,
+) {
+    let (words, rem_bytes): (&mut [u32], &mut [u8]) = FromBytes::mut_from_prefix(dest).unwrap();
+    let words_to_copy = min(LEN, words.len());
+
+    #[allow(clippy::needless_range_loop)]
+    for i in 0..words_to_copy {
+        words[i] = reg.read();
+    }
+
+    if words_to_copy < LEN {
+        set_rem_bytes(rem_bytes, || reg.read());
+    }
+}
+
+#[inline(never)]
+pub fn copy_from_reg_array<const LEN: usize>(
+    dest: &mut Aligned<A4, [u8]>,
+    array: &ureg::Array<
+        LEN,
+        ureg::RegRef<impl ureg::ReadableReg<ReadVal = u32, Raw = u32>, impl ureg::Mmio + Copy>,
+    >,
+) {
+    let (words, rem_bytes): (&mut [u32], &mut [u8]) = FromBytes::mut_from_prefix(dest).unwrap();
+    let words_to_copy = min(LEN, words.len());
+
+    #[allow(clippy::needless_range_loop)]
+    for i in 0..words_to_copy {
+        words[i] = array.at(i).read();
+    }
+
+    if words_to_copy < LEN {
+        set_rem_bytes(rem_bytes, || array.at(words_to_copy).read());
+    }
+}
+
+#[inline(never)]
+pub fn copy_from_reg_unaligned(
+    dest: &mut [u8],
+    reg: &ureg::RegRef<impl ureg::ReadableReg<ReadVal = u32, Raw = u32>, impl ureg::MmioMut + Copy>,
+) {
+    let (words, rem_bytes): (&mut [Unalign<u32>], &mut [u8]) =
+        FromBytes::mut_from_prefix(dest).unwrap();
+
+    for word in words {
+        word.set(reg.read())
+    }
+    set_rem_bytes(rem_bytes, || reg.read());
+}
+
+#[inline(always)]
+fn last_word(rem_bytes: &[u8]) -> Option<u32> {
+    if rem_bytes.is_empty() {
+        None
+    } else {
+        Some(u32::from_le_bytes([
+            rem_bytes[0],
+            rem_bytes.get(1).copied().unwrap_or_default(),
+            rem_bytes.get(2).copied().unwrap_or_default(),
+            0,
+        ]))
+    }
+}
+
+#[inline(always)]
+fn set_rem_bytes(rem_bytes: &mut [u8], get_word: impl FnOnce() -> u32) {
+    if rem_bytes.is_empty() {
+        return;
+    }
+    let word = get_word();
+    rem_bytes[0] = word as u8;
+    if rem_bytes.len() == 1 {
+        return;
+    }
+    rem_bytes[1] = (word >> 8) as u8;
+    if rem_bytes.len() == 2 {
+        return;
+    }
+    rem_bytes[2] = (word >> 16) as u8;
+}
+
+#[cfg(test)]
+mod test {
+    use super::*;
+
+    use core::cell::RefCell;
+    use core::mem::transmute_copy;
+    use std::collections::HashMap;
+    use std::collections::VecDeque;
+    use std::rc::Rc;
+
+    use ureg::Mmio;
+    use ureg::MmioMut;
+    use ureg::ReadWriteReg32;
+    use ureg::RegRef;
+    use ureg::UintType;
+
+    fn uint_val<T: ureg::Uint>(val: T) -> u64 {
+        unsafe {
+            match T::TYPE {
+                ureg::UintType::U8 => core::mem::transmute_copy::<T, u8>(&val).into(),
+                ureg::UintType::U16 => core::mem::transmute_copy::<T, u16>(&val).into(),
+                ureg::UintType::U32 => core::mem::transmute_copy::<T, u32>(&val).into(),
+                ureg::UintType::U64 => core::mem::transmute_copy::<T, u64>(&val),
+            }
+        }
+    }
+
+    #[derive(Clone, Default)]
+    struct FakeMmio {
+        fifos: Rc<RefCell<HashMap<usize, VecDeque<u32>>>>,
+        write_log: Rc<RefCell<Vec<(usize, u64)>>>,
+    }
+    impl FakeMmio {
+        fn fifo_push(&self, addr: usize, val: u32) {
+            self.fifos
+                .borrow_mut()
+                .entry(addr)
+                .or_default()
+                .push_back(val);
+        }
+        fn take_log(&self) -> Vec<(usize, u64)> {
+            core::mem::take(&mut *self.write_log.borrow_mut())
+        }
+        fn log(&self) -> Vec<(usize, u64)> {
+            self.write_log.borrow().clone()
+        }
+    }
+    impl Mmio for FakeMmio {
+        unsafe fn read_volatile<T: ureg::Uint>(&self, src: *const T) -> T {
+            let addr = src as usize;
+            let Some(val) = self.fifos.borrow_mut().entry(addr).or_default().pop_front() else {
+                panic!("Unexpected read from addr 0x{addr:x}")
+            };
+            if T::TYPE != UintType::U32 {
+                panic!("Read must be of type u32");
+            }
+            unsafe { transmute_copy::<u32, T>(&val) }
+        }
+    }
+    impl MmioMut for FakeMmio {
+        unsafe fn write_volatile<T: ureg::Uint>(&self, dst: *mut T, src: T) {
+            self.write_log
+                .borrow_mut()
+                .push((dst as usize, uint_val(src)));
+        }
+    }
+
+    #[test]
+    #[should_panic(expected = "Unexpected read from addr 0x40404040")]
+    pub fn test_fake_mmio_read_unexpected_addr() {
+        let mmio = FakeMmio::default();
+        let fifo_reg = unsafe {
+            RegRef::<ReadWriteReg32<0, u32, u32>, _>::new_with_mmio(0x4040_4040 as *mut _, &mmio)
+        };
+        fifo_reg.read();
+    }
+
+    #[test]
+    #[should_panic(expected = "Read must be of type u32")]
+    pub fn test_fake_mmio_read_unexpected_type() {
+        let addr: usize = 0x4040;
+        let mmio = FakeMmio::default();
+        mmio.fifo_push(addr, 42);
+        unsafe { mmio.read_volatile(addr as *const u64) };
+    }
+
+    #[test]
+    pub fn test_fake_mmio_read() {
+        let addr = 0x4040_4040;
+        let mmio = FakeMmio::default();
+        let fifo_reg = unsafe {
+            RegRef::<ReadWriteReg32<0, u32, u32>, _>::new_with_mmio(addr as *mut _, &mmio)
+        };
+        mmio.fifo_push(addr, 0xba5e_ba11);
+        mmio.fifo_push(addr, 0x1234_5678);
+        assert_eq!(fifo_reg.read(), 0xba5e_ba11);
+        assert_eq!(fifo_reg.read(), 0x1234_5678);
+    }
+
+    #[test]
+    #[should_panic(expected = "Unexpected read from addr 0x40404040")]
+    pub fn test_fake_mmio_read_fifo_exhausted() {
+        let addr = 0x4040_4040;
+        let mmio = FakeMmio::default();
+        let fifo_reg = unsafe {
+            RegRef::<ReadWriteReg32<0, u32, u32>, _>::new_with_mmio(addr as *mut _, &mmio)
+        };
+        mmio.fifo_push(addr, 0xba5e_ba11);
+        mmio.fifo_push(addr, 0x1234_5678);
+        assert_eq!(fifo_reg.read(), 0xba5e_ba11);
+        assert_eq!(fifo_reg.read(), 0x1234_5678);
+        fifo_reg.read();
+    }
+
+    #[test]
+    #[rustfmt::skip]
+    pub fn test_fake_mmio_write() {
+        let mmio = FakeMmio::default();
+        let fifo_reg = unsafe {
+            RegRef::<ReadWriteReg32<0, u32, u32>, _>::new_with_mmio(0x4040_4040 as *mut _, &mmio)
+        };
+        let fifo_reg2 = unsafe {
+            RegRef::<ReadWriteReg32<0, u32, u32>, _>::new_with_mmio(0x5050_5050 as *mut _, &mmio)
+        };
+
+        assert_eq!(
+            mmio.log(),
+            vec![],
+        );
+        fifo_reg.write(|_| 0xba5e_ba11);
+        assert_eq!(
+            mmio.log(),
+            vec![
+                (0x4040_4040, 0xba5e_ba11),
+            ],
+        );
+        fifo_reg.write(|_| 0xabba_abba);
+        assert_eq!(
+            mmio.log(),
+            vec![
+                (0x4040_4040, 0xba5e_ba11),
+                (0x4040_4040, 0xabba_abba),
+            ],
+        );
+        fifo_reg2.write(|_| 0x1234_5678);
+        assert_eq!(
+            mmio.log(),
+            vec![
+                (0x4040_4040, 0xba5e_ba11),
+                (0x4040_4040, 0xabba_abba),
+                (0x5050_5050, 0x1234_5678),
+            ],
+        );
+    }
+
+    #[test]
+    #[rustfmt::skip]
+    pub fn test_copy_to_reg_unaligned() {
+        let mmio = FakeMmio::default();
+        let fifo_reg = unsafe {
+            RegRef::<ReadWriteReg32<0, u32, u32>, &FakeMmio>::new_with_mmio(
+                0x4040_4040 as *mut _,
+                &mmio,
+            )
+        };
+
+        copy_to_reg_unaligned(&fifo_reg, &[]);
+        assert_eq!(
+            mmio.take_log(),
+            vec![],
+        );
+        copy_to_reg_unaligned(&fifo_reg, &[0x12]);
+        assert_eq!(
+            mmio.take_log(),
+            vec![(0x4040_4040, 0x0000_0012)],
+        );
+
+        copy_to_reg_unaligned(&fifo_reg, &[0x12, 0x34]);
+        assert_eq!(
+            mmio.take_log(),
+            vec![(0x4040_4040, 0x0000_3412)],
+        );
+
+        copy_to_reg_unaligned(&fifo_reg, &[0x12, 0x34, 0x56]);
+        assert_eq!(
+            mmio.take_log(),
+            vec![(0x4040_4040, 0x0056_3412)],
+        );
+        copy_to_reg_unaligned(&fifo_reg, &[0x12, 0x34, 0x56, 0x78]);
+        assert_eq!(
+            mmio.take_log(),
+            vec![(0x4040_4040, 0x7856_3412)],
+        );
+        copy_to_reg_unaligned(&fifo_reg, &[0x12, 0x34, 0x56, 0x78, 0x9a]);
+        assert_eq!(
+            mmio.take_log(),
+            vec![
+                (0x4040_4040, 0x7856_3412),
+                (0x4040_4040, 0x0000_009a),
+            ],
+        );
+        copy_to_reg_unaligned(&fifo_reg, &[0x12, 0x34, 0x56, 0x78, 0x9a, 0xbc]);
+        assert_eq!(
+            mmio.take_log(),
+            vec![
+                (0x4040_4040, 0x7856_3412),
+                (0x4040_4040, 0x0000_bc9a),
+            ],
+        );
+        copy_to_reg_unaligned(&fifo_reg, &[0x12, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0xde, 0xf0]);
+        assert_eq!(
+            mmio.take_log(),
+            vec![
+                (0x4040_4040, 0x7856_3412),
+                (0x4040_4040, 0xf0de_bc9a),
+            ],
+        );
+        copy_to_reg_unaligned(&fifo_reg, &[0x12, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0xde, 0xf0, 0xdd]);
+        assert_eq!(
+            mmio.take_log(),
+            vec![
+                (0x4040_4040, 0x7856_3412),
+                (0x4040_4040, 0xf0de_bc9a),
+                (0x4040_4040, 0x0000_00dd),
+            ],
+        );
+    }
+
+    #[test]
+    #[rustfmt::skip]
+    pub fn test_copy_to_reg() {
+        let mmio = FakeMmio::default();
+        let fifo_reg = unsafe {
+            RegRef::<ReadWriteReg32<0, u32, u32>, &FakeMmio>::new_with_mmio(
+                0x4040_4040 as *mut _,
+                &mmio,
+            )
+        };
+
+        copy_to_reg(&fifo_reg, &Aligned([]));
+        assert_eq!(
+            mmio.take_log(),
+            vec![],
+        );
+        copy_to_reg(&fifo_reg, &Aligned([0x12]));
+        assert_eq!(
+            mmio.take_log(),
+            vec![(0x4040_4040, 0x0000_0012)],
+        );
+        copy_to_reg(&fifo_reg, &Aligned([0x12, 0x34]));
+        assert_eq!(
+            mmio.take_log(),
+            vec![(0x4040_4040, 0x0000_3412)],
+        );
+        copy_to_reg(&fifo_reg, &Aligned([0x12, 0x34, 0x56]));
+        assert_eq!(
+            mmio.take_log(),
+            vec![(0x4040_4040, 0x0056_3412)],
+        );
+        copy_to_reg(&fifo_reg, &Aligned([0x12, 0x34, 0x56, 0x78]));
+        assert_eq!(
+            mmio.take_log(),
+            vec![(0x4040_4040, 0x7856_3412)],
+        );
+        copy_to_reg(&fifo_reg, &Aligned([0x12, 0x34, 0x56, 0x78, 0x9a]));
+        assert_eq!(
+            mmio.take_log(),
+            vec![
+                (0x4040_4040, 0x7856_3412),
+                (0x4040_4040, 0x0000_009a),
+            ],
+        );
+        copy_to_reg(&fifo_reg, &Aligned([0x12, 0x34, 0x56, 0x78, 0x9a, 0xbc]));
+        assert_eq!(
+            mmio.take_log(),
+            vec![
+                (0x4040_4040, 0x7856_3412),
+                (0x4040_4040, 0x0000_bc9a),
+            ],
+        );
+        copy_to_reg(&fifo_reg, &Aligned([0x12, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0xde, 0xf0]));
+        assert_eq!(
+            mmio.take_log(),
+            vec![
+                (0x4040_4040, 0x7856_3412),
+                (0x4040_4040, 0xf0de_bc9a),
+            ],
+        );
+        copy_to_reg(&fifo_reg, &Aligned([0x12, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0xde, 0xf0, 0xdd]));
+        assert_eq!(
+            mmio.take_log(),
+            vec![
+                (0x4040_4040, 0x7856_3412),
+                (0x4040_4040, 0xf0de_bc9a),
+                (0x4040_4040, 0x0000_00dd),
+            ],
+        );
+    }
+
+    #[test]
+    #[rustfmt::skip]
+    pub fn test_copy_to_reg_array() {
+        let mmio = FakeMmio::default();
+        let reg_array = unsafe {
+            ureg::Array::<3, RegRef<ReadWriteReg32<0, u32, u32>, &FakeMmio>>::new_with_mmio(
+                0x4040_4040 as *mut _,
+                &mmio,
+            )
+        };
+
+        copy_to_reg_array(&reg_array, &Aligned([]));
+        assert_eq!(
+            mmio.take_log(),
+            vec![],
+        );
+
+        copy_to_reg_array(&reg_array, &Aligned([0x12]));
+        assert_eq!(
+            mmio.take_log(),
+            vec![(0x4040_4040, 0x0000_0012)],
+        );
+
+        copy_to_reg_array(&reg_array, &Aligned([0x12, 0x34]));
+        assert_eq!(
+            mmio.take_log(),
+            vec![(0x4040_4040, 0x0000_3412)],
+        );
+
+        copy_to_reg_array(&reg_array, &Aligned([0x12, 0x34, 0x56]));
+        assert_eq!(
+            mmio.take_log(),
+            vec![(0x4040_4040, 0x0056_3412)],
+        );
+
+        copy_to_reg_array(&reg_array, &Aligned([0x12, 0x34, 0x56, 0x78]));
+        assert_eq!(
+            mmio.take_log(),
+            vec![(0x4040_4040, 0x7856_3412)],
+        );
+
+        copy_to_reg_array(&reg_array, &Aligned([0x12, 0x34, 0x56, 0x78, 0x9a]));
+        assert_eq!(
+            mmio.take_log(),
+            vec![
+                (0x4040_4040, 0x7856_3412),
+                (0x4040_4044, 0x0000_009a),
+            ],
+        );
+
+        copy_to_reg_array(&reg_array, &Aligned([0x12, 0x34, 0x56, 0x78, 0x9a, 0xbc]));
+        assert_eq!(
+            mmio.take_log(),
+            vec![
+                (0x4040_4040, 0x7856_3412),
+                (0x4040_4044, 0x0000_bc9a),
+            ],
+        );
+
+        copy_to_reg_array(&reg_array, &Aligned([0x12, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0xde, 0xf0]));
+        assert_eq!(
+            mmio.take_log(),
+            vec![
+                (0x4040_4040, 0x7856_3412),
+                (0x4040_4044, 0xf0de_bc9a),
+            ],
+        );
+
+        copy_to_reg_array(&reg_array, &Aligned([0x12, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0xde, 0xf0, 0xdd]));
+        assert_eq!(
+            mmio.take_log(),
+            vec![
+                (0x4040_4040, 0x7856_3412),
+                (0x4040_4044, 0xf0de_bc9a),
+                (0x4040_4048, 0x0000_00dd),
+            ],
+        );
+    }
+
+    #[test]
+    #[rustfmt::skip]
+    pub fn test_copy_from_reg() {
+        let mmio = FakeMmio::default();
+        let fifo_reg = unsafe {
+            RegRef::<ReadWriteReg32<0, u32, u32>, &FakeMmio>::new_with_mmio(
+                0x4040_4040 as *mut _,
+                &mmio,
+            )
+        };
+
+        copy_from_reg::<10>(&mut Aligned([]), &fifo_reg);
+        assert_eq!(
+            mmio.take_log(),
+            vec![],
+        );
+
+        mmio.fifo_push(0x4040_4040, 0x0000_0012);
+        let mut result = Aligned::<A4, _>([0_u8; 1]);
+        copy_from_reg::<10>(&mut result, &fifo_reg);
+        assert_eq!(&result, &Aligned([0x12]));
+
+        mmio.fifo_push(0x4040_4040, 0x0000_3412);
+        let mut result = Aligned::<A4, _>([0_u8; 2]);
+        copy_from_reg::<10>(&mut result, &fifo_reg);
+        assert_eq!(&result, &Aligned([0x12, 0x34]));
+
+        mmio.fifo_push(0x4040_4040, 0x0056_3412);
+        let mut result = Aligned::<A4, _>([0_u8; 3]);
+        copy_from_reg::<10>(&mut result, &fifo_reg);
+        assert_eq!(&result, &Aligned([0x12, 0x34, 0x56]));
+
+        mmio.fifo_push(0x4040_4040, 0x78563412);
+        let mut result = Aligned::<A4, _>([0_u8; 4]);
+        copy_from_reg::<10>(&mut result, &fifo_reg);
+        assert_eq!(&result, &Aligned([0x12, 0x34, 0x56, 0x78]));
+
+        mmio.fifo_push(0x4040_4040, 0x78563412);
+        mmio.fifo_push(0x4040_4040, 0x0000_009A);
+        let mut result = Aligned::<A4, _>([0_u8; 5]);
+        copy_from_reg::<10>(&mut result, &fifo_reg);
+        assert_eq!(&result, &Aligned([0x12, 0x34, 0x56, 0x78, 0x9A]));
+
+        mmio.fifo_push(0x4040_4040, 0x78563412);
+        mmio.fifo_push(0x4040_4040, 0x0000_BC9A);
+        let mut result = Aligned::<A4, _>([0_u8; 6]);
+        copy_from_reg::<10>(&mut result, &fifo_reg);
+        assert_eq!(&result, &Aligned([0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC]));
+
+        mmio.fifo_push(0x4040_4040, 0x78563412);
+        mmio.fifo_push(0x4040_4040, 0x00DE_BC9A);
+        let mut result = Aligned::<A4, _>([0_u8; 7]);
+        copy_from_reg::<10>(&mut result, &fifo_reg);
+        assert_eq!(&result, &Aligned([0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE]));
+
+        mmio.fifo_push(0x4040_4040, 0x78563412);
+        mmio.fifo_push(0x4040_4040, 0xF0DE_BC9A);
+        let mut result = Aligned::<A4, _>([0_u8; 8]);
+        copy_from_reg::<10>(&mut result, &fifo_reg);
+        assert_eq!(&result, &Aligned([0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0]));
+
+        mmio.fifo_push(0x4040_4040, 0x78563412);
+        mmio.fifo_push(0x4040_4040, 0xF0DE_BC9A);
+        mmio.fifo_push(0x4040_4040, 0x0000_00DD);
+        let mut result = Aligned::<A4, _>([0_u8; 9]);
+        copy_from_reg::<10>(&mut result, &fifo_reg);
+        assert_eq!(&result, &Aligned([0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0, 0xDD]));
+    }
+
+    #[test]
+    #[rustfmt::skip]
+    pub fn test_copy_from_reg_array() {
+        let mmio = FakeMmio::default();
+        let reg_array = unsafe {
+            ureg::Array::<3, RegRef<ReadWriteReg32<0, u32, u32>, &FakeMmio>>::new_with_mmio(
+                0x4040_4040 as *mut _,
+                &mmio,
+            )
+        };
+
+        copy_from_reg_array(&mut Aligned([]), &reg_array);
+        assert_eq!(
+            mmio.take_log(),
+            vec![],
+        );
+
+        mmio.fifo_push(0x4040_4040, 0x0000_0012);
+        let mut result = Aligned::<A4, _>([0_u8; 1]);
+        copy_from_reg_array(&mut result, &reg_array);
+        assert_eq!(&result, &Aligned([0x12]));
+
+        mmio.fifo_push(0x4040_4040, 0x0000_3412);
+        let mut result = Aligned::<A4, _>([0_u8; 2]);
+        copy_from_reg_array(&mut result, &reg_array);
+        assert_eq!(&result, &Aligned([0x12, 0x34]));
+
+        mmio.fifo_push(0x4040_4040, 0x0056_3412);
+        let mut result = Aligned::<A4, _>([0_u8; 3]);
+        copy_from_reg_array(&mut result, &reg_array);
+        assert_eq!(&result, &Aligned([0x12, 0x34, 0x56]));
+
+        mmio.fifo_push(0x4040_4040, 0x78563412);
+        let mut result = Aligned::<A4, _>([0_u8; 4]);
+        copy_from_reg_array(&mut result, &reg_array);
+        assert_eq!(&result, &Aligned([0x12, 0x34, 0x56, 0x78]));
+
+        mmio.fifo_push(0x4040_4040, 0x78563412);
+        mmio.fifo_push(0x4040_4044, 0x0000_009A);
+        let mut result = Aligned::<A4, _>([0_u8; 5]);
+        copy_from_reg_array(&mut result, &reg_array);
+        assert_eq!(&result, &Aligned([0x12, 0x34, 0x56, 0x78, 0x9A]));
+
+        mmio.fifo_push(0x4040_4040, 0x78563412);
+        mmio.fifo_push(0x4040_4044, 0x0000_BC9A);
+        let mut result = Aligned::<A4, _>([0_u8; 6]);
+        copy_from_reg_array(&mut result, &reg_array);
+        assert_eq!(&result, &Aligned([0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC]));
+
+        mmio.fifo_push(0x4040_4040, 0x78563412);
+        mmio.fifo_push(0x4040_4044, 0x00DE_BC9A);
+        let mut result = Aligned::<A4, _>([0_u8; 7]);
+        copy_from_reg_array(&mut result, &reg_array);
+        assert_eq!(&result, &Aligned([0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE]));
+
+        mmio.fifo_push(0x4040_4040, 0x78563412);
+        mmio.fifo_push(0x4040_4044, 0xF0DE_BC9A);
+        let mut result = Aligned::<A4, _>([0_u8; 8]);
+        copy_from_reg_array(&mut result, &reg_array);
+        assert_eq!(&result, &Aligned([0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0]));
+
+        mmio.fifo_push(0x4040_4040, 0x78563412);
+        mmio.fifo_push(0x4040_4044, 0xF0DE_BC9A);
+        mmio.fifo_push(0x4040_4048, 0x0000_00DD);
+        let mut result = Aligned::<A4, _>([0_u8; 9]);
+        copy_from_reg_array(&mut result, &reg_array);
+        assert_eq!(&result, &Aligned([0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0, 0xDD]));
+    }
+
+    #[test]
+    pub fn test_copy_from_reg_unaligned() {
+        let addr: usize = 0x4040_4040;
+        let mmio = FakeMmio::default();
+        let fifo_reg = unsafe {
+            RegRef::<ReadWriteReg32<0, u32, u32>, &FakeMmio>::new_with_mmio(addr as *mut _, &mmio)
+        };
+        copy_from_reg_unaligned(&mut [], &fifo_reg);
+
+        mmio.fifo_push(addr, 0x7856_3412);
+        let mut result = [0_u8; 1];
+        copy_from_reg_unaligned(&mut result, &fifo_reg);
+        assert_eq!(result, [0x12]);
+
+        mmio.fifo_push(addr, 0x7856_3412);
+        let mut result = [0_u8; 2];
+        copy_from_reg_unaligned(&mut result, &fifo_reg);
+        assert_eq!(result, [0x12, 0x34]);
+
+        mmio.fifo_push(addr, 0x7856_3412);
+        let mut result = [0_u8; 3];
+        copy_from_reg_unaligned(&mut result, &fifo_reg);
+        assert_eq!(result, [0x12, 0x34, 0x56]);
+
+        mmio.fifo_push(addr, 0x7856_3412);
+        let mut result = [0_u8; 4];
+        copy_from_reg_unaligned(&mut result, &fifo_reg);
+        assert_eq!(result, [0x12, 0x34, 0x56, 0x78]);
+
+        mmio.fifo_push(addr, 0x7856_3412);
+        mmio.fifo_push(addr, 0xf0de_bc9a);
+        let mut result = [0_u8; 5];
+        copy_from_reg_unaligned(&mut result, &fifo_reg);
+        assert_eq!(result, [0x12, 0x34, 0x56, 0x78, 0x9a]);
+
+        mmio.fifo_push(addr, 0x7856_3412);
+        mmio.fifo_push(addr, 0xf0de_bc9a);
+        let mut result = [0_u8; 6];
+        copy_from_reg_unaligned(&mut result, &fifo_reg);
+        assert_eq!(result, [0x12, 0x34, 0x56, 0x78, 0x9a, 0xbc]);
+
+        mmio.fifo_push(addr, 0x7856_3412);
+        mmio.fifo_push(addr, 0xf0de_bc9a);
+        let mut result = [0_u8; 7];
+        copy_from_reg_unaligned(&mut result, &fifo_reg);
+        assert_eq!(result, [0x12, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0xde]);
+
+        mmio.fifo_push(addr, 0x7856_3412);
+        mmio.fifo_push(addr, 0xf0de_bc9a);
+        let mut result = [0_u8; 8];
+        copy_from_reg_unaligned(&mut result, &fifo_reg);
+        assert_eq!(result, [0x12, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0xde, 0xf0]);
+
+        mmio.fifo_push(addr, 0x7856_3412);
+        mmio.fifo_push(addr, 0xf0de_bc9a);
+        mmio.fifo_push(addr, 0x2c);
+        let mut result = [0_u8; 9];
+        copy_from_reg_unaligned(&mut result, &fifo_reg);
+        assert_eq!(
+            result,
+            [0x12, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0xde, 0xf0, 0x2c]
+        );
+    }
+}