feat(river_hdl): adding interrupts

RossComputerGuy · RossComputerGuy · commit d4b7e64c86d8 · 2025-12-25T14:47:23.000-08:00
diff --git a/packages/river_hdl/lib/river_hdl.dart b/packages/river_hdl/lib/river_hdl.dart
@@ -5,5 +5,6 @@ export 'src/core/decoder.dart';
 export 'src/core/exec.dart';
 export 'src/core/fetcher.dart';
 export 'src/core/pipeline.dart';
+export 'src/core/int.dart';
 export 'src/core.dart';
 export 'src/memory/port.dart';
diff --git a/packages/river_hdl/lib/src/core.dart b/packages/river_hdl/lib/src/core.dart
@@ -1,10 +1,13 @@
+import 'dart:math' show max;
+
 import 'package:rohd/rohd.dart';
 import 'package:rohd_hcl/rohd_hcl.dart';
 import 'package:riscv/riscv.dart';
 import 'package:river/river.dart';
 
 import 'core/csr.dart';
 import 'core/pipeline.dart';
+import 'core/int.dart';
 
 class RiverCoreHDL extends Module {
   final RiverCore config;
@@ -20,6 +23,7 @@ class RiverCoreHDL extends Module {
     DataPortInterface memFetchRead,
     DataPortInterface memExecRead,
     DataPortInterface memWrite, {
+    Map<String, Logic> srcIrqs = const {},
     super.name = 'river_core',
   }) {
     clk = addInput('clk', clk);
@@ -34,6 +38,7 @@ class RiverCoreHDL extends Module {
         inputTags: {DataPortGroup.data, DataPortGroup.integrity},
         uniquify: (og) => 'memFetchRead_$og',
       );
+
     memExecRead = memExecRead.clone()
       ..connectIO(
         this,
@@ -42,6 +47,7 @@ class RiverCoreHDL extends Module {
         inputTags: {DataPortGroup.data, DataPortGroup.integrity},
         uniquify: (og) => 'memExecRead_$og',
       );
+
     memWrite = memWrite.clone()
       ..connectIO(
         this,
@@ -61,6 +67,70 @@ class RiverCoreHDL extends Module {
     final rs2Read = DataPortInterface(config.mxlen.size, 5);
     final rdWrite = DataPortInterface(config.mxlen.size, 5);
 
+    regs = RegisterFile(
+      clk,
+      reset,
+      [rdWrite],
+      [rs1Read, rs2Read],
+      numEntries: 32,
+      name: 'riscv_regfile',
+    );
+
+    int computeNumIrqs(InterruptController ic) {
+      final irqs = ic.lines.map((l) => l.irq).toList();
+      if (irqs.isEmpty) return 1;
+      final maxIrq = irqs.reduce((a, b) => a > b ? a : b);
+      return max(1, maxIrq + 1);
+    }
+
+    final interruptBundles =
+        <
+          ({
+            InterruptController cfg,
+            Logic srcIrq,
+            InterruptPortInterface ipi,
+            RiscVInterruptController ctrl,
+          })
+        >[];
+
+    for (final ic in config.interrupts) {
+      final numIrqs = computeNumIrqs(ic);
+
+      final isExternal = srcIrqs.containsKey(ic.name);
+      final srcIrq = isExternal
+          ? addInput(
+              'srcIrqLevel_${interruptBundles.length}',
+              srcIrqs[ic.name]!,
+              width: numIrqs,
+            )
+          : Logic(
+              name: 'srcIrqLevel_${interruptBundles.length}',
+              width: numIrqs,
+            );
+
+      final ipi = InterruptPortInterface(config.mxlen.size, config.mxlen.size);
+
+      final ctrl = RiscVInterruptController(ic, clk, reset, srcIrq, ipi);
+
+      ipi.en <= Const(0);
+      ipi.write <= Const(0);
+      ipi.addr <= Const(0, width: ipi.addr.width);
+      ipi.wdata <= Const(0, width: ipi.wdata.width);
+      ipi.wstrb <= Const(0, width: ipi.wstrb.width);
+
+      interruptBundles.add((cfg: ic, srcIrq: srcIrq, ipi: ipi, ctrl: ctrl));
+    }
+
+    Logic externalPending = Const(0);
+    for (final b in interruptBundles) {
+      final v = b.ctrl.irqToTargets;
+      Logic anyFromThis = Const(0);
+      for (var i = 0; i < v.width; i++) {
+        anyFromThis = anyFromThis | v[i];
+      }
+      externalPending = externalPending | anyFromThis;
+    }
+
     final csrRead = DataPortInterface(config.mxlen.size, 12);
     final csrWrite = DataPortInterface(config.mxlen.size, 12);
 
@@ -81,22 +151,14 @@ class RiverCoreHDL extends Module {
             marchid: config.archId,
             mimpid: config.impId,
             mhartid: config.hartId,
+            externalPending: externalPending,
             hasSupervisor: config.hasSupervisor,
             hasUser: config.hasUser,
             csrRead: csrRead,
             csrWrite: csrWrite,
           )
         : null;
 
-    regs = RegisterFile(
-      clk,
-      reset,
-      [rdWrite],
-      [rs1Read, rs2Read],
-      numEntries: 32,
-      name: 'riscv_regfile',
-    );
-
     pipeline = RiverPipeline(
       clk,
       reset,
@@ -135,6 +197,11 @@ class RiverCoreHDL extends Module {
           interruptHold < 0,
         ],
         orElse: [
+          If(
+            interruptHold & externalPending,
+            then: [interruptHold < 0, pipelineEnable < 1],
+          ),
+
           If(
             enable & ~interruptHold,
             then: [
@@ -150,12 +217,8 @@ class RiverCoreHDL extends Module {
                 orElse: [pipelineEnable < 1],
               ),
             ],
-            orElse: [
-              pipelineEnable < 0,
-              // TODO: if interrupt hold & interrupt is fired, re-enable pipeline.
-            ],
+            orElse: [pipelineEnable < 0],
           ),
-          // TODO: trap handling circuitry
         ],
       ),
     ]);
diff --git a/packages/river_hdl/lib/src/core/csr.dart b/packages/river_hdl/lib/src/core/csr.dart
@@ -85,6 +85,7 @@ class RiscVCsrFile extends Module {
     int marchid = 0,
     int mimpid = 0,
     int mhartid = 0,
+    Logic? externalPending,
     this.hasSupervisor = false,
     this.hasUser = false,
     required DataPortInterface csrRead,
@@ -99,6 +100,16 @@ class RiscVCsrFile extends Module {
     this.reset = addInput('reset', reset);
     this.mode = addInput('mode', mode, width: 3);
 
+    if (externalPending != null)
+      externalPending = addInput(
+        'externalPending',
+        externalPending!,
+        width: externalPending!.width,
+      );
+
+    addOutput('mstatus', width: mxlen.size);
+    addOutput('mie', width: mxlen.size);
+    addOutput('mip', width: mxlen.size);
     addOutput('mideleg', width: mxlen.size);
     addOutput('medeleg', width: mxlen.size);
     addOutput('mtvec', width: mxlen.size);
@@ -170,6 +181,10 @@ class RiscVCsrFile extends Module {
     _bindBackdoorForCounters();
     _wireCounters();
 
+    mstatus <=
+        _csrTop.getBackdoorPortsByAddr(0, CsrAddress.mstatus.address).rdData!;
+    mie <= _csrTop.getBackdoorPortsByAddr(0, CsrAddress.mie.address).rdData!;
+    mip <= _csrTop.getBackdoorPortsByAddr(0, CsrAddress.mip.address).rdData!;
     mideleg <=
         _csrTop.getBackdoorPortsByAddr(0, CsrAddress.mideleg.address).rdData!;
     medeleg <=
@@ -179,6 +194,12 @@ class RiscVCsrFile extends Module {
     if (hasSupervisor)
       stvec! <=
           _csrTop.getBackdoorPortsByAddr(0, CsrAddress.stvec.address).rdData!;
+
+    if (externalPending != null) {
+      final mip = _csrTop.getBackdoorPortsByAddr(0, CsrAddress.mip.address);
+      mip.wrEn! <= Const(1);
+      mip.wrData! <= this.mip.withSet(11, externalPending);
+    }
   }
 
   CsrTopConfig _buildConfig(Mxlen mxlen) {
@@ -241,6 +262,7 @@ class RiscVCsrFile extends Module {
         addr: CsrAddress.mip.address,
         resetValue: 0,
         width: mxlen.size,
+        isBackdoorWritable: true,
       ),
       CsrInstanceConfig(
         arch: SimpleRwCsr('mtvec'),
@@ -618,12 +640,9 @@ class RiscVCsrFile extends Module {
   Logic get misa =>
       _csrTop.getBackdoorPortsByAddr(0, CsrAddress.misa.address).rdData!;
 
-  Logic get mstatus =>
-      _csrTop.getBackdoorPortsByAddr(0, CsrAddress.mstatus.address).rdData!;
-  Logic get mie =>
-      _csrTop.getBackdoorPortsByAddr(0, CsrAddress.mie.address).rdData!;
-  Logic get mip =>
-      _csrTop.getBackdoorPortsByAddr(0, CsrAddress.mip.address).rdData!;
+  Logic get mstatus => output('mstatus');
+  Logic get mie => output('mie');
+  Logic get mip => output('mip');
   Logic get mtvec => output('mtvec');
   Logic get mscratch =>
       _csrTop.getBackdoorPortsByAddr(0, CsrAddress.mscratch.address).rdData!;
diff --git a/packages/river_hdl/lib/src/core/int.dart b/packages/river_hdl/lib/src/core/int.dart
