feat(river_hdl): adding devices

Author: RossComputerGuy

packages/river/lib/src/dev.dart

@@ -113,6 +113,10 @@ class Device {
   final BusClientPort? clientPort;
   final ClockConfig? clock;
 
+  String get module => (runtimeType.toString() == 'Device')
+      ? compatible.replaceAll(',', '_')
+      : runtimeType.toString();
+
   const Device({
     required this.name,
     required this.compatible,
@@ -133,6 +137,7 @@ class Device {
     Map<int, DeviceField>? fields,
     DeviceAccessorType type = DeviceAccessorType.memory,
     ClockConfig? clock,
+    List<DevicePort> ports = const [],
   }) {
     path ??= '/$name';
     final accessor = fields != null
@@ -154,6 +159,7 @@ class Device {
       accessor: accessor,
       clientPort: clientPort,
       clock: clock,
+      ports: ports,
     );
   }
 

packages/river/lib/src/impl/devices/uart.dart

@@ -27,6 +27,7 @@ class RiverUart extends Device {
            6: DeviceField('msr', 1),
            7: DeviceField('scr', 1),
          }, type: DeviceAccessorType.io),
+         ports: [DevicePort('rx', 1), DevicePort('tx', 1, isOutput: true)],
        );
 
   static const lcr = BitStruct({

packages/river/lib/src/impl/soc/stream/v1.dart

@@ -126,7 +126,10 @@ class StreamV1SoC extends RiverSoC {
   ];
 
   @override
-  List<RiverPortMap> get ports => [];
+  List<RiverPortMap> get ports => [
+    const RiverPortMap('uart_rx', [4], {'uart0': 'rx'}),
+    const RiverPortMap('uart_tx', [6], {'uart0': 'tx'}, isOutput: true),
+  ];
 
   List<MemoryBlock> get mmap =>
       devices.map((dev) => dev.mmap).nonNulls.toList();

packages/river/lib/src/river_base.dart

@@ -192,15 +192,15 @@ class RiverCore {
 class RiverPortMap {
   final String name;
   final List<int> pins;
-  final List<String> devices;
+  final Map<String, String> devices;
   final bool isOutput;
 
   int get width => pins.length.bitLength;
 
   const RiverPortMap(
-    this.name, {
-    this.pins = const [],
-    this.devices = const [],
+    this.name,
+    this.pins,
+    this.devices, {
     this.isOutput = false,
   });
 

packages/river_hdl/bin/river_hdlgen.dart

@@ -1,6 +1,7 @@
 import 'dart:io' show Platform, File;
 
 import 'package:args/args.dart';
+import 'package:logging/logging.dart';
 import 'package:path/path.dart' as path;
 import 'package:river/river.dart';
 import 'package:river_hdl/river_hdl.dart';
@@ -25,11 +26,23 @@ Future<void> main(List<String> arguments) async {
     allowed: RiverPlatformChoice.values.map((v) => v.name).toList(),
   );
 
+  parser.addMultiOption(
+    'device-option',
+    help: 'Adds an option when configuring a device',
+    splitCommas: false,
+  );
+
   parser.addOption(
     'output',
     help: 'Sets the output path to generate the SystemVerilog to',
   );
 
+  parser.addOption(
+    'log',
+    help: 'Sets the log level',
+    allowed: Level.LEVELS.map((v) => v.name.toLowerCase()).toList(),
+  );
+
   parser.addFlag('help', help: 'Prints the usage');
 
   final args = parser.parse(arguments);
@@ -42,6 +55,17 @@ Future<void> main(List<String> arguments) async {
     return;
   }
 
+  Logger.root.onRecord.listen((record) {
+    print('${record.level.name}: ${record.time}: ${record.message}');
+  });
+
+  if (args.option('log') != null) {
+    Logger.root.level = Level.LEVELS.firstWhere(
+      (v) => v.name.toLowerCase() == args.option('log'),
+    );
+    Logger.root.finest('Logging set to ${Logger.root.level}');
+  }
+
   RiverPlatformChoice? platformChoice;
   RiverSoCChoice? socChoice;
 
@@ -97,7 +121,53 @@ Future<void> main(List<String> arguments) async {
       }) ??
       (throw 'Invalid platform configuration');
 
-  final ip = RiverSoCIP(socConfig);
+  Logger.root.finest('River SoC configured: $socConfig');
 
-  await ip.buildAndGenerateRTL(outputPath: args.option('output') ?? 'output');
+  final ip = RiverSoCIP(
+    socConfig,
+    deviceOptions: Map.fromEntries(
+      args
+          .multiOption('device-option')
+          .map((option) {
+            final i = option.indexOf('.');
+            assert(i > 0);
+            return option.substring(0, i);
+          })
+          .map(
+            (key) => MapEntry(
+              key,
+              Map.fromEntries(
+                args
+                    .multiOption('device-option')
+                    .where((option) {
+                      final i = option.indexOf('.');
+                      assert(i > 0);
+                      return option.substring(0, i) == key;
+                    })
+                    .map((option) {
+                      final i = option.indexOf('.');
+                      assert(i > 0);
+
+                      final entry = option.substring(i + 1);
+
+                      final x = entry.indexOf('=');
+                      assert(x > 0);
+
+                      return MapEntry(
+                        entry.substring(0, x),
+                        entry.substring(x + 1),
+                      );
+                    }),
+              ),
+            ),
+          ),
+    ),
+  );
+
+  Logger.root.finest('River SoC module created: $ip');
+
+  await ip.buildAndGenerateRTL(
+    logger: Logger.root,
+    outputPath: args.option('output') ?? 'output',
+  );
 }

packages/river_hdl/lib/river_hdl.dart

@@ -9,5 +9,6 @@ export 'src/core/mmu.dart';
 export 'src/core/pipeline.dart';
 export 'src/core.dart';
 export 'src/dev.dart';
+export 'src/devices.dart';
 export 'src/memory/port.dart';
 export 'src/soc.dart';