@black-pigeon @lone-boy When building antsdr_uhd FPGA build, I get critical timing closure warnings with `Timing constraints are not met`. Attached report. [antsdr_e200_timing_summary_routed.txt](https://github.com/user-attachments/files/23004223/antsdr_e200_timing_summary_routed.txt)
@black-pigeon @lone-boy
When building antsdr_uhd FPGA build, I get critical timing closure warnings with
Timing constraints are not met. Attached report.antsdr_e200_timing_summary_routed.txt