diff --git a/.github/workflows/clk_divider.yml b/.github/workflows/clk_divider.yml new file mode 100644 index 0000000..51e9abe --- /dev/null +++ b/.github/workflows/clk_divider.yml @@ -0,0 +1,29 @@ +name: ClkDivider Test + +on: [push, pull_request] + +jobs: + test: + runs-on: ubuntu-latest + + steps: + - name: Checkout do código + uses: actions/checkout@v4 + + - name: Instalar Icarus Verilog (iverilog) + run: sudo apt update && sudo apt install -y iverilog + + - name: Criar diretório de build + run: mkdir -p build + + - name: Compilar o testbench + run: iverilog -o build/ClkDivider_tb -s ClkDivider_tb -g2005-sv -Irtl/core testbenchs/clk_divider_tb.sv rtl/clk_divider.sv + + - name: Executar o testbench + run: vvp build/ClkDivider_tb + + - name: Salvar VCD como artefato + uses: actions/upload-artifact@v4 + with: + name: fifo_waveform + path: build/ClkDivider_tb.vcd diff --git a/.github/workflows/fifo.yml b/.github/workflows/fifo.yml new file mode 100644 index 0000000..44bb7e3 --- /dev/null +++ b/.github/workflows/fifo.yml @@ -0,0 +1,29 @@ +name: FIFO Test + +on: [push, pull_request] + +jobs: + test: + runs-on: ubuntu-latest + + steps: + - name: Checkout do código + uses: actions/checkout@v4 + + - name: Instalar Icarus Verilog (iverilog) + run: sudo apt update && sudo apt install -y iverilog + + - name: Criar diretório de build + run: mkdir -p build + + - name: Compilar o testbench + run: iverilog -o build/fifo_tb -s fifo_tb -g2005-sv -Irtl/core testbenchs/fifo_tb.sv rtl/fifo.sv + + - name: Executar o testbench + run: vvp build/fifo_tb + + - name: Salvar VCD como artefato + uses: actions/upload-artifact@v4 + with: + name: fifo_waveform + path: build/fifo_tb.vcd diff --git a/.gitignore b/.gitignore index 123e2bf..771ee80 100644 --- a/.gitignore +++ b/.gitignore @@ -19,3 +19,6 @@ webtalk*.log webtalk*.jou fpga/digilent_arty/usage_statistics_webtalk.xml fpga/digilent_arty/usage_statistics_webtalk.html +fpga/nexys4_ddr/clockInfo.txt +fpga/nexys4_ddr/usage_statistics_webtalk.html +fpga/nexys4_ddr/usage_statistics_webtalk.xml diff --git a/.gitmodules b/.gitmodules index fc1dceb..116233c 100644 --- a/.gitmodules +++ b/.gitmodules @@ -3,7 +3,4 @@ url = https://github.com/Unicamp-Odhin/SPI-Slave [submodule "modules/UART"] path = modules/UART - url = https://github.com/ben-marshall/uart -[submodule "modules/Risco-5"] - path = modules/Risco-5 - url = https://github.com/JN513/Risco-5 + url = https://github.com/ben-marshall/uart \ No newline at end of file diff --git a/Risco-5 b/Risco-5 deleted file mode 160000 index ac0bca8..0000000 --- a/Risco-5 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit ac0bca8e5cab9ead7c236481a8346b49f05260ea diff --git a/examples/Grande-Risco-5.sv b/examples/Grande-Risco-5.sv new file mode 100644 index 0000000..6f706dc --- /dev/null +++ b/examples/Grande-Risco-5.sv @@ -0,0 +1,103 @@ +module top ( + input logic clk, + input logic CPU_RESETN, + + input logic rx, + output logic tx, + + input logic mosi, + output logic miso, + input logic sck, + input logic cs +); + +logic clk_o; +logic clk_core, rst_core; + +// Fios do barramento entre Controller e Processor +logic core_cyc; +logic core_stb; +logic core_we; +logic [31:0] core_addr; +logic [31:0] core_data_out; +logic [31:0] core_data_in; +logic core_ack; + +Controller #( + .CLK_FREQ (50000000), + .BIT_RATE (BIT_RATE), + .PAYLOAD_BITS (8), + .BUFFER_SIZE (8), + .PULSE_CONTROL_BITS (32), + .BUS_WIDTH (32), + .WORD_SIZE_BY (4), + .ID (32'h7700006A), + .RESET_CLK_CYCLES (20), + .MEMORY_FILE (""), + .MEMORY_SIZE (4096) +) u_Controller ( + .clk (clk), + .rst_n (CPU_RESETN), + + // SPI signals + .sck_i (sck), + .cs_i (cs), + .mosi_i (mosi), + .miso_o (miso), + + // SPI callback signals + .rw_i (), + .intr_o (), + + // UART signals + .rx (rx), + .tx (tx), + + // Clock, reset, and bus signals + .clk_core_o (clk_core), + .rst_core_o (rst_core), + + // Barramento padrão (não AXI4-Lite) + .core_cyc_i (core_cyc), + .core_stb_i (core_stb), + .core_we_i (core_we), + .core_addr_i (core_addr), + .core_data_i (core_data_out), + .core_data_o (core_data_in), + .core_ack_o (core_ack) +); + +Grande_Risco5 #( + .BOOT_ADDRESS (32'h00000000), + .I_CACHE_SIZE (256), + .D_CACHE_SIZE (256), + .DATA_WIDTH (32), + .ADDR_WIDTH (32), + .BRANCH_PREDICTION_SIZE (128) +) Processor ( + .clk (clk_core), + .rst_n (~rst_core), + .halt (1'b0), + + .cyc_o (core_cyc), + .stb_o (core_stb), + .we_o (core_we), + + .addr_o (core_addr), + .data_o (core_data_out), + + .ack_i (core_ack), + .data_i (core_data_in), + + .interruption (1'b0) +); + +always_ff @(posedge clk) begin : CLOCK_DIVIDER + if (!CPU_RESETN) begin + clk_o <= 1'b0; + end else begin + clk_o <= ~clk_o; + end +end + +endmodule diff --git a/fpga/nexys4_ddr/.gitignore b/fpga/nexys4_ddr/.gitignore index 8ab51c2..c6fdf6a 100644 --- a/fpga/nexys4_ddr/.gitignore +++ b/fpga/nexys4_ddr/.gitignore @@ -3,4 +3,5 @@ digilent_arty.hw/ digilent_arty.ip_user_files/ .Xil/ report/ -vivado_*.backup.* \ No newline at end of file +vivado_*.backup.* +reports \ No newline at end of file diff --git a/fpga/nexys4_ddr/Makefile b/fpga/nexys4_ddr/Makefile index 1d1e539..77102bb 100644 --- a/fpga/nexys4_ddr/Makefile +++ b/fpga/nexys4_ddr/Makefile @@ -1,15 +1,27 @@ +ifndef VIVADO_PATH + VIVADO=vivado +else + VIVADO=$(VIVADO_PATH)/vivado +endif + all: ./build/out.bit ./build/out.bit: buildFolder - vivado -mode batch -nolog -nojournal -source run.tcl + $(VIVADO) -mode batch -nolog -nojournal -source run.tcl buildFolder: mkdir -p build + mkdir -p reports clean: rm -rf build - rm clockInfo.txt + rm -rf clockInfo.txt + rm -rf .Xil + rm -rf reports -flash: +load: openFPGALoader -b nexys_a7_100 ./build/out.bit -run_all: ./build/out.bit flash \ No newline at end of file +flash: + openFPGALoader -b nexys_a7_100 -f ./build/out.bit + +run_all: ./build/out.bit load diff --git a/fpga/nexys4_ddr/main.sv b/fpga/nexys4_ddr/main.sv new file mode 100644 index 0000000..4cdd457 --- /dev/null +++ b/fpga/nexys4_ddr/main.sv @@ -0,0 +1,99 @@ +module top ( + input logic clk, + input logic CPU_RESETN, + + input logic rx, + output logic tx, + + output logic [15:0]LED, + + input logic mosi, + output logic miso, + input logic sck, + input logic cs, + + input logic [15:0] SW, + + output logic [3:0] VGA_R, + output logic [3:0] VGA_G, + output logic [3:0] VGA_B, + output logic VGA_HS, + output logic VGA_VS, + + output logic M_CLK, // Clock do microfone + output logic M_LRSEL, // Left/Right Select (Escolha do canal) + + input logic M_DATA // Dados do microfone +); + + +logic clk_o; + +logic clk_core, rst_core; + + +Controller #( + .CLK_FREQ (50000000), + .BIT_RATE (115200), + .PAYLOAD_BITS (8), + .BUFFER_SIZE (8), + .PULSE_CONTROL_BITS (32), + .BUS_WIDTH (32), + .WORD_SIZE_BY (4), + .ID (32'h7700006A), + .RESET_CLK_CYCLES (20), + .MEMORY_FILE (""), + .MEMORY_SIZE (4096) +) u_Controller ( + .clk (clk_o), + .rst_n (CPU_RESETN), + + // SPI signals + .sck_i (sck), + .cs_i (cs), + .mosi_i (mosi), + .miso_o (miso), + + // SPI callback signals + .rw_i (), + .intr_o (), + + // UART signals + .rx (rx), + .tx (tx), + + // Clock, reset, and bus signals + .clk_core_o (clk_core), + .rst_core_o (rst_core), + + // Barramento padrão (não AXI4-Lite) + .core_cyc_i (), + .core_stb_i (), + .core_we_i (), + .core_addr_i (), + .core_data_i (), + .core_data_o (), + .core_ack_o () + + `ifdef ENABLE_SECOND_MEMORY + , + // Segunda memória - memória de dados + .data_mem_cyc_i (data_mem_cyc_i), + .data_mem_stb_i (data_mem_stb_i), + .data_mem_we_i (data_mem_we_i), + .data_mem_addr_i (data_mem_addr_i), + .data_mem_data_i (data_mem_data_i), + .data_mem_data_o (data_mem_data_o), + .data_mem_ack_o (data_mem_ack_o) + `endif +); + + +always_ff @(posedge clk) begin + if(!CPU_RESETN) + clk_o <= 1'b0; + else + clk_o <= ~clk_o; +end + +endmodule diff --git a/fpga/nexys4_ddr/main.v b/fpga/nexys4_ddr/main.v deleted file mode 100644 index 7d1f192..0000000 --- a/fpga/nexys4_ddr/main.v +++ /dev/null @@ -1,60 +0,0 @@ -module top ( - input wire clk, - input wire CPU_RESETN, - input wire rx, - output wire tx, - output wire [7:0]LED, - input wire [7:0]gpio -); - -reg clk_o; - -initial begin - clk_o = 1'b0; // 50mhz -end - -wire clk_core, reset_core, core_memory_response, reset_o; - - -ResetBootSystem #( - .CYCLES(20) -) ResetBootSystem( - .clk(clk_o), - .reset_o(reset_o) -); - -Controller #( - .CLK_FREQ(50000000), - .BIT_RATE(115200), - .PAYLOAD_BITS(8), - .BUFFER_SIZE(8), - .PULSE_CONTROL_BITS(32), - .BUS_WIDTH(32), - .WORD_SIZE_BY(4), - .ID(32'h7700006A), - .RESET_CLK_CYCLES(20), - .MEMORY_FILE(""), - .MEMORY_SIZE(4096) -) Controller( - .clk(clk_o), - .reset(reset_o), - - .tx(tx), - .rx(rx), - - .clk_core(clk_core), - .reset_core(reset_core), - - .core_memory_response(core_memory_response), - .core_read_memory(), - .core_write_memory(), - .core_address_memory(), - .core_write_data_memory(), - .core_read_data_memory() -); - -always @(posedge clk) begin - clk_o = ~clk_o; -end - -endmodule diff --git a/fpga/nexys4_ddr/pinout.xdc b/fpga/nexys4_ddr/pinout.xdc new file mode 100644 index 0000000..29d0380 --- /dev/null +++ b/fpga/nexys4_ddr/pinout.xdc @@ -0,0 +1,269 @@ +## This file is a general .xdc for the Nexys4 DDR Rev. C +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]; + + +##Switches + +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] +set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] +set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] +set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] +set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] +set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] +set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] +set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8] +set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9] +set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] +set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] +set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12] +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] +set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] +set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] + + +## LEDs + +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] +set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] +set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] + +#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b +#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g +#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r +#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b +#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r + + +##7 segment display + +#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca +#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc +#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd +#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce +#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf +#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg + +#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp + +#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] +#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] +#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] +#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] +#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6] +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] + + +##Buttons + +set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn + +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu +#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl +#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd + + +##Pmod Headers + + +##Pmod Header JA + +#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] +#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] +#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] + +set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { mosi }]; #IO_L20N_T3_A19_15 Sch=ja[1] +set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { miso }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] +set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { sck }]; #IO_L21P_T3_DQS_15 Sch=ja[3] +set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { cs }]; #IO_L18N_T2_A23_15 Sch=ja[4] + + +##Pmod Header JB + +#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] +#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] +#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] +#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] +#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] +#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9] +#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] + + +##Pmod Header JC + +#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1] +#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] +#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3] +#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4] +#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7] +#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8] +#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] +#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] + + +##Pmod Header JD + +#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] +#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2] +#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3] +#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4] +#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] +#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8] +#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] +#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] + + +##Pmod Header JXADC + +#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] +#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] +#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] +#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] +#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] +#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] + + +##VGA Connector + +set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] +set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] +set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] +set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] + +set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] +set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] +set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] +set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] + +set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] +set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] +set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] +set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] + +set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs +set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs + + +##Micro SD Connector + +#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset +#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd +#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck +#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd +#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] +#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] +#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] +#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] + + +##Accelerometer + +#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso +#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi +#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk +#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn +#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] +#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] + + +##Temperature Sensor + +#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl +#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda +#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int +#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct + +##Omnidirectional Microphone + +set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk +set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data +set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel + + +##PWM Audio Amplifier + +#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm +#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd + + +##USB-RS232 Interface + +set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { rx }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in +set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { tx }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out +#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts +#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts + +##USB HID (PS/2) + +#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk +#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data + + +##SMSC Ethernet PHY + +#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc +#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio +#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn +#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv +#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr +#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] +#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] +#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen +#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] +#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] +#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk +#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn + + +##Quad SPI Flash + +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] +#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] +#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn + + + + + + + + + + + + diff --git a/fpga/nexys4_ddr/run.tcl b/fpga/nexys4_ddr/run.tcl index 883a741..cc066fc 100644 --- a/fpga/nexys4_ddr/run.tcl +++ b/fpga/nexys4_ddr/run.tcl @@ -1,17 +1,18 @@ -read_verilog "main.v" -read_verilog ../../modules/uart.v +read_verilog -sv main.sv +read_verilog -sv ../../modules/uart.sv read_verilog ../../modules/UART/rtl/uart_rx.v read_verilog ../../modules/UART/rtl/uart_tx.v -read_verilog ../../src/fifo.v -read_verilog ../../src/reset.v -read_verilog ../../src/clk_divider.v -read_verilog ../../src/memory.v -read_verilog ../../src/interpreter.v -read_verilog ../../src/controller.v +read_verilog -sv ../../rtl/fifo.sv +read_verilog -sv ../../rtl/reset.sv +read_verilog -sv ../../rtl/clk_divider.sv +read_verilog -sv ../../rtl/memory.sv +read_verilog -sv ../../rtl/interpreter.sv +read_verilog -sv ../../rtl/controller.sv +set_param general.maxThreads 16 -read_xdc "digilent_nexys4_ddr.xdc" -set_property PROCESSING_ORDER EARLY [get_files digilent_nexys4_ddr.xdc] +read_xdc "pinout.xdc" +set_property PROCESSING_ORDER EARLY [get_files pinout.xdc] # synth synth_design -top "top" -part "xc7a100tcsg324-1" @@ -20,19 +21,21 @@ synth_design -top "top" -part "xc7a100tcsg324-1" opt_design place_design -report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt -report_utilization -file digilent_nexys4ddr_utilization_place.rpt -report_io -file digilent_nexys4ddr_io.rpt -report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt -report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt +report_utilization -hierarchical -file reports/utilization_hierarchical_place.rpt +report_utilization -file reports/utilization_place.rpt +report_io -file reports/io.rpt +report_control_sets -verbose -file reports/control_sets.rpt +report_clock_utilization -file reports/clock_utilization.rpt + route_design report_timing_summary -no_header -no_detailed_paths -report_route_status -file digilent_nexys4ddr_route_status.rpt -report_drc -file digilent_nexys4ddr_drc.rpt -report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt -report_power -file digilent_nexys4ddr_power.rpt +report_route_status -file reports/route_status.rpt +report_drc -file reports/drc.rpt +report_timing_summary -datasheet -max_paths 10 -file reports/timing.rpt +report_power -file reports/power.rpt + # write bitstream -write_bitstream -force "./build/out.bit" \ No newline at end of file +write_bitstream -force "./build/out.bit" diff --git a/modules/Risco-5 b/modules/Risco-5 deleted file mode 160000 index ac0bca8..0000000 --- a/modules/Risco-5 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit ac0bca8e5cab9ead7c236481a8346b49f05260ea diff --git a/modules/uart.sv b/modules/uart.sv new file mode 100644 index 0000000..b7b8735 --- /dev/null +++ b/modules/uart.sv @@ -0,0 +1,286 @@ +module UART #( + parameter CLK_FREQ = 25000000, + parameter BIT_RATE = 9600, + parameter PAYLOAD_BITS = 8, + parameter BUFFER_SIZE = 8, + parameter WORD_SIZE_BY = 4 +) ( + input logic clk, + input logic rst_n, + + output logic uart_rx_empty, + output logic uart_tx_empty, + + input logic rx, + output logic tx, + + input logic read, + input logic write, + output logic read_response, + output logic write_response, + + input logic [31:0] write_data, + output logic [31:0] read_data +); + +logic uart_rx_valid, uart_rx_break, uart_tx_busy, tx_fifo_empty, + rx_fifo_empty, tx_fifo_full, rx_fifo_full; +logic uart_tx_en, tx_fifo_read, tx_fifo_write, rx_fifo_read, + rx_fifo_write; +logic [PAYLOAD_BITS-1:0] uart_rx_data, tx_fifo_data_out, + rx_fifo_data_out; +logic [PAYLOAD_BITS-1:0] uart_tx_data, tx_fifo_data_in, + rx_fifo_data_in; + +logic [31:0] write_data_buffer; + +logic [2:0] counter_write, counter_read; +logic [3:0] state_read, state_write; + +assign uart_rx_empty = rx_fifo_empty; +assign uart_tx_empty = tx_fifo_empty; + +localparam IDLE = 4'b0000; +localparam READ = 4'b0001; +localparam WRITE = 4'b0101; +localparam WB = 4'b0010; +localparam FINISH = 4'b0011; +localparam COPY_WRITE_BUFFER = 4'b0100; +localparam COPY_READ_BUFFER = 4'b0100; + +/* +Read state machine: + IDLE -> READ -> WB -> FINISH +*/ + +always_ff @(posedge clk ) begin + rx_fifo_read <= 1'b0; + read_response <= 1'b0; + + if(!rst_n) begin + state_read <= IDLE; + rx_fifo_read <= 1'b0; + read_data <= 32'h00000000; + counter_read <= 3'b000; + end else begin + unique case (state_read) + IDLE: begin + counter_read <= 3'b000; + if(read) begin + read_data <= 32'h00000000; + state_read <= READ; + end else begin + state_read <= IDLE; + end + end + + READ: begin + if(counter_read < (WORD_SIZE_BY)) begin + if(!rx_fifo_empty) begin + read_data <= {read_data[23:0], rx_fifo_data_out}; + counter_read <= counter_read + 1'b1; + rx_fifo_read <= 1'b1; + state_read <= COPY_READ_BUFFER; + end + end else begin + read_data <= {read_data[23:0], rx_fifo_data_out}; + state_read <= WB; + end + end + + COPY_READ_BUFFER: begin + state_read <= READ; + end + + WB: begin + state_read <= FINISH; + end + + FINISH: begin + read_response <= 1'b1; + state_read <= IDLE; + end + + default: state_read <= IDLE; + endcase + end +end + +/* +Write state machine: + IDLE -> COPY_WRITE_BUFFER -> WRITE -> WB -> FINISH +*/ + +always_ff @(posedge clk ) begin + write_response <= 1'b0; + tx_fifo_write <= 1'b0; + + if(!rst_n) begin + state_write <= IDLE; + tx_fifo_write <= 1'b0; + tx_fifo_data_in <= 8'h00; + write_data_buffer <= 32'h00000000; + counter_write <= 3'b000; + end else begin + unique case (state_write) + IDLE: begin + counter_write <= 3'b000; + if(write) begin + state_write <= COPY_WRITE_BUFFER; + end else begin + state_write <= IDLE; + end + end + + COPY_WRITE_BUFFER: begin + write_data_buffer <= write_data; + state_write <= WRITE; + end + + WRITE: begin + if(counter_write < WORD_SIZE_BY) begin + if(tx_fifo_full == 1'b0) begin + tx_fifo_data_in <= write_data_buffer[31:24]; + write_data_buffer <= {write_data_buffer[23:0], 8'h00}; + counter_write <= counter_write + 1'b1; + tx_fifo_write <= 1'b1; + end + end else begin + state_write <= WB; + end + end + + WB: begin + write_response <= 1'b1; + state_write <= FINISH; + end + + FINISH: begin + write_response <= 1'b1; + state_write <= IDLE; + end + + default: state_write <= IDLE; + endcase + end +end + + +always_ff @(posedge clk) begin + rx_fifo_write <= 1'b0; + + if(!rst_n) begin + rx_fifo_data_in <= 8'h00; + rx_fifo_write <= 1'b0; + end else begin + if(rx_fifo_full == 1'b0 && uart_rx_valid == 1'b1) begin + rx_fifo_data_in <= uart_rx_data; + rx_fifo_write <= 1'b1; + end + end +end + +typedef enum logic [1:0] { + TX_FIFO_IDLE, + TX_FIFO_READ_FIFO, + TX_FIFO_WRITE_TX, + TX_FIFO_WAIT +} tx_read_fifo_state_t; + +tx_read_fifo_state_t tx_read_fifo_state; + +always_ff @(posedge clk) begin : UART_TX_READ_FROM_FIFO + uart_tx_en <= 1'b0; + tx_fifo_read <= 1'b0; + + if(!rst_n) begin + uart_tx_data <= 8'h00; + end else begin + unique case (tx_read_fifo_state) + TX_FIFO_IDLE: begin + if(!tx_fifo_empty && !uart_tx_busy) begin + tx_read_fifo_state <= TX_FIFO_READ_FIFO; + tx_fifo_read <= 1'b1; + end + end + TX_FIFO_READ_FIFO: begin + tx_read_fifo_state <= TX_FIFO_WRITE_TX; + end + TX_FIFO_WRITE_TX: begin + uart_tx_data <= tx_fifo_data_out; + uart_tx_en <= 1'b1; + tx_read_fifo_state <= TX_FIFO_WAIT; + end + TX_FIFO_WAIT: begin + tx_read_fifo_state <= TX_FIFO_IDLE; + end + default: tx_read_fifo_state <= TX_FIFO_IDLE; + endcase + end +end + +FIFO #( + .DEPTH (BUFFER_SIZE), + .WIDTH (PAYLOAD_BITS) +) tx_fifo ( + .clk (clk), + .rst_n (rst_n), + + .wr_en_i (tx_fifo_write), + .rd_en_i (tx_fifo_read), + + .write_data_i (tx_fifo_data_in), + .full_o (tx_fifo_full), + .empty_o (tx_fifo_empty), + .read_data_o (tx_fifo_data_out) +); + +FIFO #( + .DEPTH (BUFFER_SIZE), + .WIDTH (PAYLOAD_BITS) +) rx_fifo ( + .clk (clk), + .rst_n (rst_n), + + .wr_en_i (rx_fifo_write), + .rd_en_i (rx_fifo_read), + + .write_data_i (rx_fifo_data_in), + .full_o (rx_fifo_full), + .empty_o (rx_fifo_empty), + .read_data_o (rx_fifo_data_out) +); + + +// UART RX +uart_rx #( + .BIT_RATE (BIT_RATE), + .PAYLOAD_BITS (PAYLOAD_BITS), + .CLK_HZ (CLK_FREQ) +) i_uart_rx( + .clk (clk ), // Top level system clock input. + .resetn (rst_n ), // Asynchronous active low reset. + .uart_rxd (rx ), // UART Recieve pin. + .uart_rx_en (1'b1 ), // Recieve enable + .uart_rx_break(uart_rx_break), // Did we get a BREAK message? + .uart_rx_valid(uart_rx_valid), // Valid data recieved and available. + .uart_rx_data (uart_rx_data ) // The recieved data. +); + +// +// UART Transmitter module. +// +uart_tx #( + .BIT_RATE (BIT_RATE), + .PAYLOAD_BITS (PAYLOAD_BITS), + .CLK_HZ (CLK_FREQ) +) i_uart_tx( + .clk (clk ), + .resetn (rst_n ), + .uart_txd (tx ), // serial_tx + .uart_tx_en (uart_tx_en ), + .uart_tx_busy (uart_tx_busy), + .uart_tx_data (uart_tx_data) +); + +endmodule diff --git a/modules/uart.v b/modules/uart.v deleted file mode 100644 index 0994153..0000000 --- a/modules/uart.v +++ /dev/null @@ -1,299 +0,0 @@ -module UART #( - parameter CLK_FREQ = 25000000, - parameter BIT_RATE = 9600, - parameter PAYLOAD_BITS = 8, - parameter BUFFER_SIZE = 8, - parameter WORD_SIZE_BY = 1 -) ( - input wire clk, - input wire reset, - - output wire uart_rx_empty, - output wire uart_tx_empty, - - input wire rx, - output wire tx, - - input wire read, - input wire write, - output reg read_response, - output reg write_response, - - input wire [31:0] write_data, - output reg [31:0] read_data -); - -wire uart_rx_valid, uart_rx_break, uart_tx_busy, tx_fifo_empty, - rx_fifo_empty, tx_fifo_full, rx_fifo_full; -reg uart_tx_en, tx_fifo_read, tx_fifo_write, rx_fifo_read, - rx_fifo_write; -wire [PAYLOAD_BITS-1:0] uart_rx_data, tx_fifo_read_data, - rx_fifo_read_data; -reg [PAYLOAD_BITS-1:0] uart_tx_data, tx_fifo_write_data, - rx_fifo_write_data; - -reg [31:0] write_data_buffer; - -reg [2:0] counter_write, counter_read; -reg [3:0] state_read, state_write; - -assign uart_rx_empty = rx_fifo_empty; -assign uart_tx_empty = tx_fifo_empty; - -initial begin - read_response = 1'b0; - write_response = 1'b0; - uart_tx_en = 1'b0; - tx_fifo_read = 1'b0; - tx_fifo_write = 1'b0; - rx_fifo_read = 1'b0; - rx_fifo_write = 1'b0; - counter_read = 2'b00; - state_read = 3'b00; - counter_write = 2'b00; - state_write = 3'b00; - uart_tx_data = 8'h00; - tx_fifo_write_data = 8'h00; - rx_fifo_write_data = 8'h00; - read_data = 32'h00000000; -end - -localparam IDLE = 4'b0000; -localparam READ = 4'b0001; -localparam WRITE = 4'b0001; -localparam WB = 4'b0010; -localparam FINISH = 4'b0011; -localparam COPY_WRITE_BUFFER = 4'b0100; -localparam COPY_READ_BUFFER = 4'b0100; - -/* -Read state machine: - IDLE -> READ -> WB -> FINISH -*/ - -always @(posedge clk ) begin - rx_fifo_read <= 1'b0; - read_response <= 1'b0; - - if(reset == 1'b1) begin - state_read <= IDLE; - rx_fifo_read <= 1'b0; - read_data <= 32'h00000000; - counter_read <= 3'b000; - end else begin - case (state_read) - IDLE: begin - counter_read <= 3'b000; - if(read) begin - state_read <= READ; - end else begin - state_read <= IDLE; - end - end - - READ: begin - if(counter_read < (WORD_SIZE_BY)) begin - if(rx_fifo_empty == 1'b0) begin - read_data <= {read_data[23:0], rx_fifo_read_data}; - counter_read <= counter_read + 1'b1; - rx_fifo_read <= 1'b1; - state_read <= COPY_READ_BUFFER; - end - end else begin - read_data <= {read_data[23:0], rx_fifo_read_data}; - state_read <= WB; - end - end - - COPY_READ_BUFFER: begin - state_read <= READ; - end - - WB: begin - read_response <= 1'b1; - state_read <= FINISH; - end - - FINISH: begin - read_response <= 1'b1; - state_read <= IDLE; - end - - default: state_read <= IDLE; - endcase - end -end - -/* -Write state machine: - IDLE -> COPY_WRITE_BUFFER -> WRITE -> WB -> FINISH -*/ - -always @(posedge clk ) begin - write_response <= 1'b0; - tx_fifo_write <= 1'b0; - - if(reset == 1'b1) begin - state_write <= IDLE; - tx_fifo_write <= 1'b0; - tx_fifo_write_data <= 8'h00; - write_data_buffer <= 32'h00000000; - counter_write <= 3'b000; - end else begin - case (state_write) - IDLE: begin - counter_write <= 3'b000; - if(write) begin - state_write <= COPY_WRITE_BUFFER; - end else begin - state_write <= IDLE; - end - end - - COPY_WRITE_BUFFER: begin - write_data_buffer <= write_data; - state_write <= WRITE; - end - - WRITE: begin - if(counter_write < WORD_SIZE_BY) begin - if(tx_fifo_full == 1'b0) begin - tx_fifo_write_data <= write_data_buffer[31:24]; - write_data_buffer <= {write_data_buffer[23:0], 8'h00}; - counter_write <= counter_write + 1'b1; - tx_fifo_write <= 1'b1; - end - end else begin - state_write <= WB; - end - end - - WB: begin - write_response <= 1'b1; - state_write <= FINISH; - end - - FINISH: begin - write_response <= 1'b1; - state_write <= IDLE; - end - - default: state_write <= IDLE; - endcase - end -end - - -always @(posedge clk) begin - rx_fifo_write <= 1'b0; - - if(reset == 1'b1) begin - rx_fifo_write_data <= 8'h00; - rx_fifo_write <= 1'b0; - end else begin - if(rx_fifo_full == 1'b0 && uart_rx_valid == 1'b1) begin - rx_fifo_write_data <= uart_rx_data; - rx_fifo_write <= 1'b1; - end - end -end - -reg [1:0] tx_fifo_read_state; - -always @(posedge clk ) begin - uart_tx_en <= 1'b0; - tx_fifo_read <= 1'b0; - - if(reset == 1'b1) begin - uart_tx_en <= 1'b0; - tx_fifo_read <= 1'b0; - uart_tx_data <= 8'h00; - tx_fifo_read_state <= 2'b00; - end else begin - case (tx_fifo_read_state) - 2'b00: begin - if(uart_tx_busy == 1'b0 && tx_fifo_empty == 1'b0) begin - tx_fifo_read <= 1'b1; - tx_fifo_read_state <= 2'b01; - end - end - - 2'b01: begin - tx_fifo_read_state <= 2'b10; // estado para transição dos dados - end - - 2'b10: begin - uart_tx_en <= 1'b1; - uart_tx_data <= tx_fifo_read_data; - tx_fifo_read_state <= 2'b11; - end - - 2'b11: begin - tx_fifo_read_state <= 2'b00; // estado para transição dos dados - end - - default: tx_fifo_read_state <= 2'b00; - endcase - end -end - -FIFO #( - .DEPTH(BUFFER_SIZE), - .WIDTH(PAYLOAD_BITS) -) TX_FIFO ( - .clk(clk), - .reset(reset), - .write(tx_fifo_write), - .read(tx_fifo_read), - .write_data(tx_fifo_write_data), - .full(tx_fifo_full), - .empty(tx_fifo_empty), - .read_data(tx_fifo_read_data) -); - -FIFO #( - .DEPTH(BUFFER_SIZE), - .WIDTH(PAYLOAD_BITS) -) RX_FIFO ( - .clk(clk), - .reset(reset), - .write(rx_fifo_write), - .read(rx_fifo_read), - .write_data(rx_fifo_write_data), - .full(rx_fifo_full), - .empty(rx_fifo_empty), - .read_data(rx_fifo_read_data) -); - -// UART RX -uart_rx #( - .BIT_RATE(BIT_RATE), - .PAYLOAD_BITS(PAYLOAD_BITS), - .CLK_HZ(CLK_FREQ) -) i_uart_rx( - .clk (clk ), // Top level system clock input. - .resetn (~reset ), // Asynchronous active low reset. - .uart_rxd (rx ), // UART Recieve pin. - .uart_rx_en (1'b1 ), // Recieve enable - .uart_rx_break(uart_rx_break), // Did we get a BREAK message? - .uart_rx_valid(uart_rx_valid), // Valid data recieved and available. - .uart_rx_data (uart_rx_data ) // The recieved data. -); - -// -// UART Transmitter module. -// -uart_tx #( - .BIT_RATE(BIT_RATE), - .PAYLOAD_BITS(PAYLOAD_BITS), - .CLK_HZ(CLK_FREQ) -) i_uart_tx( - .clk (clk ), - .resetn (~reset ), - .uart_txd (tx ), // serial_tx - .uart_tx_en (uart_tx_en ), - .uart_tx_busy (uart_tx_busy ), - .uart_tx_data (uart_tx_data ) -); - -endmodule diff --git a/rtl/axi4lite_to_wishbone.sv b/rtl/axi4lite_to_wishbone.sv new file mode 100644 index 0000000..88b664c --- /dev/null +++ b/rtl/axi4lite_to_wishbone.sv @@ -0,0 +1,123 @@ +module AXI4Lite_to_Wishbone #( + parameter ADDR_WIDTH = 32, + parameter DATA_WIDTH = 32 +)( + input logic ACLK, + input logic ARESETN, + + // AXI4-Lite Slave Interface + input logic [ADDR_WIDTH-1:0] AWADDR, + input logic [2:0] AWPROT, + input logic AWVALID, + output logic AWREADY, + + input logic [DATA_WIDTH-1:0] WDATA, + input logic [(DATA_WIDTH/8)-1:0] WSTRB, + input logic WVALID, + output logic WREADY, + + output logic [1:0] BRESP, + output logic BVALID, + input logic BREADY, + + input logic [ADDR_WIDTH-1:0] ARADDR, + input logic [2:0] ARPROT, + input logic ARVALID, + output logic ARREADY, + + output logic [DATA_WIDTH-1:0] RDATA, + output logic [1:0] RRESP, + output logic RVALID, + input logic RREADY, + + // Wishbone Master Interface + output logic [ADDR_WIDTH-1:0] wb_adr_o, + output logic [DATA_WIDTH-1:0] wb_dat_o, + output logic wb_we_o, + output logic wb_stb_o, + output logic wb_cyc_o, + output logic [(DATA_WIDTH/8)-1:0] wb_sel_o, + input logic [DATA_WIDTH-1:0] wb_dat_i, + input logic wb_ack_i, + input logic wb_err_i +); + + // Estado interno + typedef enum logic [1:0] { + IDLE, + WRITE, + READ + } state_t; + + state_t state; + + always_ff @(posedge ACLK or negedge ARESETN) begin + if (!ARESETN) begin + state <= IDLE; + AWREADY <= 0; + WREADY <= 0; + BVALID <= 0; + ARREADY <= 0; + RVALID <= 0; + wb_cyc_o <= 0; + wb_stb_o <= 0; + wb_we_o <= 0; + end else begin + unique case (state) + IDLE: begin + AWREADY <= 1; + ARREADY <= 1; + BVALID <= 0; + RVALID <= 0; + + if (AWVALID && AWREADY) begin + wb_adr_o <= AWADDR; + wb_we_o <= 1; + wb_dat_o <= WDATA; + wb_sel_o <= WSTRB; + wb_cyc_o <= 1; + wb_stb_o <= 1; + AWREADY <= 0; + WREADY <= 1; + state <= WRITE; + end + else if (ARVALID && ARREADY) begin + wb_adr_o <= ARADDR; + wb_we_o <= 0; + wb_cyc_o <= 1; + wb_stb_o <= 1; + ARREADY <= 0; + state <= READ; + end + end + + WRITE: begin + if (WVALID && WREADY) begin + WREADY <= 0; + end + + if (wb_ack_i) begin + wb_cyc_o <= 0; + wb_stb_o <= 0; + BVALID <= 1; + BRESP <= (wb_err_i) ? 2'b10 : 2'b00; // 2'b10 = SLVERR, 2'b00 = OKAY + state <= IDLE; + end + end + + READ: begin + if (wb_ack_i) begin + wb_cyc_o <= 0; + wb_stb_o <= 0; + RDATA <= wb_dat_i; + RRESP <= (wb_err_i) ? 2'b10 : 2'b00; // 2'b10 = SLVERR, 2'b00 = OKAY + RVALID <= 1; + state <= IDLE; + end + end + + default: state <= IDLE; + endcase + end + end +endmodule diff --git a/rtl/clk_divider.sv b/rtl/clk_divider.sv new file mode 100644 index 0000000..543355f --- /dev/null +++ b/rtl/clk_divider.sv @@ -0,0 +1,63 @@ +module ClkDivider #( + parameter COUNTER_BITS = 32, + parameter PULSE_CONTROL_BITS = 32 +)( + input logic clk, + input logic rst_n, + input logic write_pulse, + input logic option, // 0 - pulse, 1 - auto + input logic out_enable, // 0 - no, 1 - yes + input logic [COUNTER_BITS-1:0] divider, + input logic [PULSE_CONTROL_BITS-1:0] pulse, + + output logic clk_o +); + +logic clk_o_pulse; +logic clk_o_auto; +logic [COUNTER_BITS - 1 : 0] clk_counter; +logic [PULSE_CONTROL_BITS - 1 : 0] pulse_counter; + +// Multiplexador da saída +assign clk_o = (!option) ? clk_o_pulse : (out_enable) ? clk_o_auto : 1'b0; + +// Liga a saída ao clock enquanto o contador de pulsos for maior do que 0 +assign clk_o_pulse = (|pulse_counter) ? clk : 1'b0; + +always_ff @(posedge clk or negedge rst_n) begin : CLK_DIVIDER + if (!rst_n) begin + clk_counter <= 0; + clk_o_auto <= 1'b0; + end else begin + if (~|clk_counter) begin + clk_o_auto <= 1'b1; + clk_counter <= clk_counter + 1; + end else if (clk_counter == {1'b0, divider[COUNTER_BITS-1:1]}) begin + clk_o_auto <= 1'b0; + clk_counter <= clk_counter + 1; + end else begin + clk_counter <= clk_counter + 1; + end + + if (clk_counter >= divider - 1) begin + clk_counter <= 0; + end + end +end + +always_ff @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + pulse_counter <= 0; + end else begin + if (out_enable) begin + if (pulse_counter > 0) begin + pulse_counter <= pulse_counter - 1; + end + end + if (write_pulse) begin + pulse_counter <= pulse; + end + end +end + +endmodule \ No newline at end of file diff --git a/rtl/controller.sv b/rtl/controller.sv new file mode 100644 index 0000000..2b0917b --- /dev/null +++ b/rtl/controller.sv @@ -0,0 +1,300 @@ +module Controller #( + parameter CLK_FREQ = 100_000_000, + parameter BIT_RATE = 9600, + parameter PAYLOAD_BITS = 8, + parameter BUFFER_SIZE = 8, + parameter PULSE_CONTROL_BITS = 12, + parameter BUS_WIDTH = 32, + parameter WORD_SIZE_BY = 4, + parameter ID = 32'h00000001, + parameter RESET_CLK_CYCLES = 20, + parameter MEMORY_FILE = "", + parameter MEMORY_SIZE = 4096 +) ( + input logic clk, + input logic rst_n, + + // SPI signals + input logic sck_i, + input logic cs_i, + input logic mosi_i, + input logic miso_o, + + // SPI callback signals + input logic rw_i, + output logic intr_o, + + // UART signals + input logic rx, + output logic tx, + + //saída de clock para o core, reset, endereço de memória, + //barramento de leitura e escrita entre outros. + output logic clk_core_o, + output logic rst_core_o, + + `ifndef BUS_TYPE_AXI4_LITE + + input logic core_cyc_i, // Indica uma transação ativa + input logic core_stb_i, // Indica uma solicitação ativa + input logic core_we_i, // 1 = Write, 0 = Read + + input logic [31:0] core_addr_i, // Endereço + input logic [31:0] core_data_i, // Dados de entrada (para escrita) + output logic [31:0] core_data_o, // Dados de saída (para leitura) + + output logic core_ack_o // Confirmação da transação + + `else + // Write Address Channel + input logic [ADDR_WIDTH-1:0] AWADDR, + input logic [2:0] AWPROT, + input logic AWVALID, + output logic AWREADY, + + // Write Data Channel + input logic [DATA_WIDTH-1:0] WDATA, + input logic [(DATA_WIDTH/8)-1:0] WSTRB, + input logic WVALID, + output logic WREADY, + + // Write Response Channel + output logic [1:0] BRESP, + output logic BVALID, + input logic BREADY, + + // Read Address Channel + input logic [ADDR_WIDTH-1:0] ARADDR, + input logic [2:0] ARPROT, + input logic ARVALID, + output logic ARREADY, + + // Read Data Channel + output logic [DATA_WIDTH-1:0] RDATA, + output logic [1:0] RRESP, + output logic RVALID, + input logic RREADY + `endif + + `ifdef ENABLE_SECOND_MEMORY + , + // Second memory - data memory + input logic data_mem_cyc_i, // Indica uma transação ativa + input logic data_mem_stb_i, // Indica uma solicitação ativa + input logic data_mem_we_i, // 1 = Write, 0 = Read + + input logic [31:0] data_mem_addr_i, // Endereço + input logic [31:0] data_mem_data_i, // Dados de entrada (para escrita) + output logic [31:0] data_mem_data_o, // Dados de saída (para leitura) + + output logic data_mem_ack_o // Confirmação da transação + `endif +); + +// UART logics +logic communication_read, communication_write, communication_read_response, communication_write_response, + communication_rx_empty, communication_tx_empty; +logic [31:0] communication_read_data, communication_write_data; + +// Clock Divider logics +logic write_pulse, clk_enable; +logic [PULSE_CONTROL_BITS-1:0] num_pulses; + +// Memory logics + +// Interpreter +logic interpreter_memory_read, interpreter_memory_write, interpreter_memory_response, memory_mux_selector; +logic [31:0] interpreter_memory_read_data, interpreter_memory_write_data, interpreter_memory_address; +logic interpreter_we, interpreter_stb, interpreter_cyc; + +assign interpreter_cyc = interpreter_memory_write | interpreter_memory_read; +assign interpreter_we = interpreter_memory_write; +assign interpreter_stb = interpreter_memory_write | interpreter_memory_read; + +// Primary Memory +logic memory_cyc, memory_stb, memory_ack, memory_we; +logic [31:0] memory_read_data, memory_address, memory_write_data; + +// Data Memory +logic data_memory_cyc, data_memory_stb, data_memory_ack, data_memory_we; +logic [31:0] data_memory_read_data, data_memory_address, data_memory_write_data; + +// Bus Logic - Primary Memory +assign memory_cyc = (memory_mux_selector) ? core_cyc_i : (!interpreter_memory_address[31]) ? interpreter_cyc : 1'b0; +assign memory_stb = (memory_mux_selector) ? core_stb_i : (!interpreter_memory_address[31]) ? interpreter_stb : 1'b0; +assign memory_we = (memory_mux_selector) ? core_we_i : (!interpreter_memory_address[31]) ? interpreter_we : 1'b0; +assign memory_address = (memory_mux_selector) ? core_addr_i : interpreter_memory_address; +assign memory_write_data = (memory_mux_selector) ? core_data_i : interpreter_memory_write_data; + +`ifdef ENABLE_SECOND_MEMORY +// Bus logic - Data Memory +assign data_memory_cyc = (memory_mux_selector) ? data_mem_cyc_i : (interpreter_memory_address[31]) ? interpreter_cyc : 1'b0; +assign data_memory_stb = (memory_mux_selector) ? data_mem_stb_i : (interpreter_memory_address[31]) ? interpreter_stb : 1'b0; +assign data_memory_we = (memory_mux_selector) ? data_mem_we_i : (interpreter_memory_address[31]) ? interpreter_we : 1'b0; +assign data_memory_address = (memory_mux_selector) ? data_mem_addr_i : interpreter_memory_address; +assign data_memory_write_data = (memory_mux_selector) ? data_mem_data_i : interpreter_memory_write_data; +`endif + +// Bus Logic - Core +assign core_ack_o = (memory_mux_selector) ? memory_ack : 1'b0; +assign core_data_o = (memory_mux_selector) ? memory_read_data : 32'h00000000; +`ifdef ENABLE_SECOND_MEMORY +assign data_mem_ack_o = (memory_mux_selector) ? data_memory_ack : 1'b0; +assign data_mem_data_o = (memory_mux_selector) ? data_memory_read_data : 32'h00000000; +`endif + +// Bus Logic - Interpreter +// Interpreter memory response +assign interpreter_memory_response = (!memory_mux_selector) ? (interpreter_memory_address[31]) ? data_memory_ack : memory_ack : 1'b0; +assign interpreter_memory_read_data = (!memory_mux_selector) ? (interpreter_memory_address[31]) ? data_memory_read_data : memory_read_data : 32'h00000000; + +// Bus internal +logic finish_execution; +logic reset_bus, bus_mode; +logic [23:0] memory_page_number; +logic [31:0] end_position; + + +always_ff @(posedge clk ) begin + if(reset_bus) + finish_execution <= 1'b0; + else begin + if(bus_mode) begin + if(core_addr_i[5:0] == end_position[5:0]) + finish_execution <= 1'b1; + end else begin + if(core_addr_i == end_position + `ifdef ENABLE_SECOND_MEMORY + || data_mem_addr_i == end_position + `endif + ) + finish_execution <= 1'b1; + end + end +end + +ClkDivider #( + .COUNTER_BITS (32), + .PULSE_CONTROL_BITS (PULSE_CONTROL_BITS) +) ClkDivider( + .clk (clk), + .rst_n (rst_n), + .write_pulse (write_pulse), + .option (1'b0), // 0 - pulse, 1 - auto + .out_enable (clk_enable), // 0 not, 1 - yes + .divider (), + .pulse (num_pulses), + .clk_o (clk_core_o) +); + +Interpreter #( + .CLK_FREQ (CLK_FREQ), + .PULSE_CONTROL_BITS (PULSE_CONTROL_BITS), + .BUS_WIDTH (BUS_WIDTH), + .ID (ID), + .RESET_CLK_CYCLES (RESET_CLK_CYCLES) +) Interpreter( + .clk (clk), + .rst_n (rst_n), + + // uart buffer signal + .communication_rx_empty (communication_rx_empty), + .communication_tx_empty (communication_tx_empty), + + // uart control signal + .communication_read (communication_read), + .communication_write (communication_write), + .communication_read_response (communication_read_response), + .communication_write_response (communication_write_response), + + // uart data signal + .communication_read_data (communication_read_data), + .communication_write_data (communication_write_data), + + // core signals + .core_clk_enable (clk_enable), + .core_reset (rst_core_o), + .num_of_cycles_to_pulse (num_pulses), + .write_pulse (write_pulse), + + // BUS signals + .finish_execution (finish_execution), + .reset_bus (reset_bus), + .bus_mode (bus_mode), + .memory_page_size (), + .end_position (end_position), + + // memory bus signal + .memory_response (interpreter_memory_response), + .memory_read (interpreter_memory_read), + .memory_write (interpreter_memory_write), + .memory_mux_selector (memory_mux_selector), + .memory_page_number (memory_page_number), + .write_data (interpreter_memory_write_data), + .address (interpreter_memory_address), + .read_data (interpreter_memory_read_data) +); + +UART #( + .CLK_FREQ (CLK_FREQ), + .BIT_RATE (BIT_RATE), + .PAYLOAD_BITS (PAYLOAD_BITS), + .BUFFER_SIZE (BUFFER_SIZE), + .WORD_SIZE_BY (WORD_SIZE_BY) +) Uart( + .clk (clk), + .rst_n (rst_n), + + .rx (rx), + .tx (tx), + + .uart_rx_empty (communication_rx_empty), + .uart_tx_empty (communication_tx_empty), + + .read (communication_read), + .write (communication_write), + .read_response (communication_read_response), + .write_response (communication_write_response), + + .write_data (communication_write_data), + .read_data (communication_read_data) +); + +Memory #( + .MEMORY_FILE (MEMORY_FILE), + .MEMORY_SIZE (MEMORY_SIZE) +) Core_Memory ( + .clk (clk), + + .cyc_i (memory_cyc), + .stb_i (memory_stb), + .we_i (memory_we), + + .addr_i (memory_address), + .data_i (memory_write_data), + .data_o (memory_read_data), + + .ack_o (memory_ack) +); + + +`ifdef ENABLE_SECOND_MEMORY +Memory #( + .MEMORY_FILE (), + .MEMORY_SIZE (4096) +) Core_Data_Memory ( + .clk (clk), + + .cyc_i (data_memory_cyc_i), + .stb_i (data_memory_stb_i), + .we_i (data_memory_we_i), + + .addr_i (data_memory_addr_i), + .data_i (data_memory_data_i), + .data_o (data_memory_data_o), + + .ack_o (data_memory_ack_o) +); +`endif + +endmodule diff --git a/rtl/fifo.sv b/rtl/fifo.sv new file mode 100644 index 0000000..2f80b9c --- /dev/null +++ b/rtl/fifo.sv @@ -0,0 +1,55 @@ +module FIFO #( + parameter DEPTH = 8, + parameter WIDTH = 8 +) ( + input logic clk, + input logic rst_n, + + input logic wr_en_i, + input logic rd_en_i, + + input logic [WIDTH - 1'b1:0] write_data_i, + output logic full_o, + output logic empty_o, + output logic [WIDTH - 1'b1:0] read_data_o +); + +// Cálculo da largura do ponteiro +localparam PTR_WIDTH = $clog2(DEPTH) + ((DEPTH & (DEPTH - 1)) != 0 ? 1 : 0); + +// Memória FIFO +logic [WIDTH - 1'b1:0] memory[DEPTH - 1'b1:0]; + +// Ponteiros de leitura e escrita +logic [PTR_WIDTH:0] read_ptr; +logic [PTR_WIDTH:0] write_ptr; + +// Leitura +always_ff @(posedge clk) begin + if (!rst_n) begin + read_ptr <= 'd0; + read_data_o <= 'd0; + end else if (rd_en_i && !empty_o) begin + read_data_o <= memory[read_ptr[PTR_WIDTH-1:0]]; + read_ptr <= read_ptr + 1'b1; + end +end + +// Escrita +always_ff @(posedge clk) begin + if (!rst_n) begin + write_ptr <= 'd0; + end else if (wr_en_i && !full_o) begin + memory[write_ptr[PTR_WIDTH-1:0]] <= write_data_i; + write_ptr <= write_ptr + 1'b1; + end +end + +// FIFO cheia: ocorre quando o próximo `write_ptr` encontra `read_ptr` +assign full_o = (write_ptr[PTR_WIDTH] != read_ptr[PTR_WIDTH]) && + (write_ptr[PTR_WIDTH - 1'b1:0] == read_ptr[PTR_WIDTH - 1'b1:0]); + +// FIFO vazia: ocorre quando os ponteiros são iguais +assign empty_o = (write_ptr == read_ptr); + +endmodule diff --git a/rtl/interpreter.sv b/rtl/interpreter.sv new file mode 100644 index 0000000..6289f43 --- /dev/null +++ b/rtl/interpreter.sv @@ -0,0 +1,520 @@ +module Interpreter #( + parameter CLK_FREQ = 25000000, + parameter PULSE_CONTROL_BITS = 32, + parameter BUS_WIDTH = 32, + parameter ID = 32'h7700006A, + parameter RESET_CLK_CYCLES = 20 +) ( + // Control signals + input logic clk, + input logic rst_n, + + // communication + input logic communication_rx_empty, + input logic communication_tx_empty, + + output logic communication_read, + output logic communication_write, + input logic communication_read_response, + input logic communication_write_response, + + input logic [31:0] communication_read_data, + output logic [31:0] communication_write_data, + + // Core signals + output logic core_clk_enable, + output logic core_reset, + output logic [PULSE_CONTROL_BITS-1:0] num_of_cycles_to_pulse, + output logic write_pulse, + + // BUS signals + input logic finish_execution, + output logic reset_bus, + output logic bus_mode, // 1 - pagination mode, 0 - normal mode + output logic [23:0] memory_page_size, + output logic [31:0] end_position, + + // Memory BUS signal + input logic memory_response, + output logic memory_read, + output logic memory_write, + output logic memory_mux_selector, + output logic [23:0] memory_page_number, + output logic [BUS_WIDTH-1:0] write_data, + output logic [BUS_WIDTH-1:0] address, + input logic [BUS_WIDTH-1:0] read_data +); + +localparam RUN_TESTS_FINISH_MESSAGE = 32'h676F6F64; +localparam UNTIL_FINISH_MESSAGE = 32'h6C75636B; +localparam TIMEOUT_CLK_CYCLES = 'd360; +localparam DELAY_CYCLES = 'd30; + +logic [7:0] counter; +logic [23:0] num_of_pages, num_of_positions; +logic [31:0] communication_buffer, read_buffer, timeout, timeout_counter; +logic [63:0] accumulator, temp_buffer; + +typedef enum logic [7:0] { + IDLE = 8'b00000000, + FETCH = 8'b00000001, + DECODE = 8'b00000010, + SEND_READ_BUFFER = 8'b00000011, + WAIT_WRITE_RESPONSE = 8'b00000100, + MEMORY_READ = 8'b00000101, + READ_SECOND_PAGE_FROM_SERIAL = 8'b00000110, + SAVE_SECOND_WORD_IN_MEMORY = 8'b00000111, + MEMORY_WRITE_LOOP = 8'b00001000, + READ_WORD_FROM_SERIAL = 8'b00001001, + SAVE_WORD = 8'b00001010, + MEMORY_READ_LOOP = 8'b00001011, + READ_WORD_FROM_MEMORY = 8'b00001100, + RESET_CORE_LOOP = 8'b00001101, + RESET_CORE_END = 8'b00001110, + UNTIL_ENABLE_CORE = 8'b00001111, + UNTIL_END_POINT_WAIT = 8'b00010000, + SEND_UNTIL_FINISH_MESSAGE = 8'b00010001, + RUN_TESTS_ENABLE_CORE = 8'b00010010, + RUN_TESTS_WAIT = 8'b00010011, + RUN_TESTS_UPDATE_PAGE = 8'b00010100, + RUN_TESTS_FINISH = 8'b00010101, + RUN_TESTS_INIT = 8'b00010110, + SEND_UNTIL_RELATORY = 8'b00010111, + WRITE_CLK = 8'b01000011, // C - 0x43 + STOP_CLK = 8'b01010011, // S - 0x53 + RESUME_CLK = 8'b01110010, // r - 0x72 + RESET_CORE = 8'b01010010, // R - 0x52 + WRITE_IN_MEMORY = 8'b01010111, // W - 0x57 + READ_FROM_MEMORY = 8'b01001100, // L - 0x4C + LOAD_UPPER_ACUMULATOR = 8'b01010101, // U - 0x55 + LOAD_LOWER_ACUMULATOR = 8'b01101100, // l - 0x6C + ADD_N_TO_ACUMULATOR = 8'b01000001, // A - 0x41 + WRITE_ACUMULATOR_IN_POS_N = 8'b01110111, // w - 0x77 + WRITE_N_IN_POS_ACUMULATOR = 8'b01110011, // s - 0x73 + READ_ACUMULATOR_POS_IN_MEMORY = 8'b01000111, // G - 0x47 + SET_TIMEOUT = 8'b01010100, // T - 0x54 + SET_MEMORY_PAGE_SIZE = 8'b01010000, // P - 0x50 + RUN_TESTS = 8'b01000101, // E - 0x45 + PING = 8'b01110000, // p - 0x70 + DEFINE_N_AS_PROGRAM_FINISH_POSITION = 8'b01000100, // D - 0x44 + DEFINE_ACC_AS_PROG_FINISH_POSITION = 8'b01100100, // d - 0x64 + GET_ACUMULATOR = 8'b01100001, // a - 0x61 + SWITCH_MEMORY_TO_CORE = 8'b01001111, // O - 0x4F + WRITE_NEXT_N_WORDS_FROM_ACUMULATOR = 8'b01100101, // e - 0x65 + READ_NEXT_N_WORDS_FROM_ACUMULATOR = 8'b01001101, // M - 0x4D + UNTIL_END_POINT = 8'b01110101 // u - 0x75 +} interpreter_state_t; + +interpreter_state_t state, return_state; + +always @(posedge clk) begin + communication_read <= 1'b0; + communication_write <= 1'b0; + core_reset <= 1'b0; + write_pulse <= 1'b0; + memory_read <= 1'b0; + memory_write <= 1'b0; + reset_bus <= 1'b0; + + if(!rst_n) begin + state <= IDLE; + communication_buffer <= 32'h0; + accumulator <= 64'h0; + counter <= 8'h00; + core_clk_enable <= 1'b0; + memory_mux_selector <= 1'b0; + return_state <= IDLE; + num_of_pages <= 24'h0; + timeout_counter <= 8'h00; + reset_bus <= 1'b1; + bus_mode <= 1'b0; + end_position <= 32'h0; + read_buffer <= 32'h0; + timeout <= 32'h0; + end else begin + case (state) + IDLE: begin + counter <= 8'h00; + if(!communication_rx_empty) begin + state <= FETCH; + end else begin + state <= IDLE; + end + end + + FETCH: begin + communication_read <= 1'b1; + communication_buffer <= communication_read_data; + + if(communication_read_response) begin + state <= DECODE; + end else begin + state <= FETCH; + end + end + + DECODE: begin + return_state <= IDLE; + case (communication_buffer[7:0]) + WRITE_CLK: state <= WRITE_CLK; + STOP_CLK: state <= STOP_CLK; + RESUME_CLK: state <= RESUME_CLK; + RESET_CORE: state <= RESET_CORE; + WRITE_IN_MEMORY: state <= WRITE_IN_MEMORY; + READ_FROM_MEMORY: state <= READ_FROM_MEMORY; + LOAD_UPPER_ACUMULATOR: state <= LOAD_UPPER_ACUMULATOR; + LOAD_LOWER_ACUMULATOR: state <= LOAD_LOWER_ACUMULATOR; + ADD_N_TO_ACUMULATOR: state <= ADD_N_TO_ACUMULATOR; + WRITE_ACUMULATOR_IN_POS_N: state <= WRITE_ACUMULATOR_IN_POS_N; + WRITE_N_IN_POS_ACUMULATOR: state <= WRITE_N_IN_POS_ACUMULATOR; + READ_ACUMULATOR_POS_IN_MEMORY: state <= READ_ACUMULATOR_POS_IN_MEMORY; + SET_TIMEOUT: state <= SET_TIMEOUT; + SET_MEMORY_PAGE_SIZE: state <= SET_MEMORY_PAGE_SIZE; + RUN_TESTS: state <= RUN_TESTS; + PING: state <= PING; + DEFINE_N_AS_PROGRAM_FINISH_POSITION: state <= DEFINE_N_AS_PROGRAM_FINISH_POSITION; + DEFINE_ACC_AS_PROG_FINISH_POSITION: state <= DEFINE_ACC_AS_PROG_FINISH_POSITION; + GET_ACUMULATOR: state <= GET_ACUMULATOR; + SWITCH_MEMORY_TO_CORE: state <= SWITCH_MEMORY_TO_CORE; + WRITE_NEXT_N_WORDS_FROM_ACUMULATOR: state <= WRITE_NEXT_N_WORDS_FROM_ACUMULATOR; + READ_NEXT_N_WORDS_FROM_ACUMULATOR: state <= READ_NEXT_N_WORDS_FROM_ACUMULATOR; + UNTIL_END_POINT: state <= UNTIL_END_POINT; + default: state <= IDLE; + endcase + end + + WRITE_CLK: begin + core_clk_enable <= 1'b1; + num_of_cycles_to_pulse <= {8'h00, communication_buffer[31:8]}; + write_pulse <= 1'b1; + state <= IDLE; + end + STOP_CLK: begin + core_clk_enable <= 1'b0; + state <= IDLE; + end + + RESUME_CLK: begin + core_clk_enable <= 1'b1; + state <= IDLE; + end + + RESET_CORE: begin + counter <= 8'h00; + core_reset <= 1'b1; + core_clk_enable <= 1'b1; + num_of_cycles_to_pulse <= RESET_CLK_CYCLES; + write_pulse <= 1'b1; + state <= RESET_CORE_LOOP; + end + + RESET_CORE_LOOP: begin + core_reset <= 1'b1; + counter <= counter + 1'b1; + if(counter == RESET_CLK_CYCLES) begin + core_clk_enable <= 1'b0; + state <= RESET_CORE_END; + end else begin + state <= RESET_CORE_LOOP; + end + end + + RESET_CORE_END: begin + core_reset <= 1'b0; + core_clk_enable <= 1'b0; + state <= return_state; + end + + WRITE_IN_MEMORY: begin + memory_mux_selector <= 1'b0; + address <= {communication_buffer[31], 6'h0, communication_buffer[30:8], 2'b0}; + + if(!communication_rx_empty) begin + state <= READ_SECOND_PAGE_FROM_SERIAL; + end else begin + state <= WRITE_IN_MEMORY; + end + end + + READ_SECOND_PAGE_FROM_SERIAL: begin + communication_read <= 1'b1; + communication_buffer <= communication_read_data; + + if(communication_read_response) begin + state <= SAVE_SECOND_WORD_IN_MEMORY; + end else begin + state <= READ_SECOND_PAGE_FROM_SERIAL; + end + end + + SAVE_SECOND_WORD_IN_MEMORY: begin + memory_mux_selector <= 1'b0; + write_data <= communication_buffer[31:0]; + memory_write <= 1'b1; + state <= IDLE; + end + + READ_FROM_MEMORY: begin + memory_mux_selector <= 1'b0; + address <= {communication_buffer[31], 6'h0, communication_buffer[30:8], 2'b0}; + memory_read <= 1'b1; + state <= MEMORY_READ; + end + + LOAD_UPPER_ACUMULATOR: begin + accumulator <= {32'h0, communication_buffer[31:8], accumulator[7:0]}; + state <= IDLE; + end + + LOAD_LOWER_ACUMULATOR: begin + accumulator <= {accumulator[63:8], communication_buffer[15:8]}; + state <= IDLE; + end + + ADD_N_TO_ACUMULATOR: begin + accumulator <= accumulator + {{40{communication_buffer[31]}}, communication_buffer[31:8]}; + state <= IDLE; + end + + WRITE_ACUMULATOR_IN_POS_N: begin + memory_mux_selector <= 1'b0; + address <= {communication_buffer[31], 6'h0, communication_buffer[30:8], 2'b0}; // ver alinhamento depois + write_data <= accumulator[31:0]; + memory_write <= 1'b1; + state <= IDLE; + end + + WRITE_N_IN_POS_ACUMULATOR: begin + memory_mux_selector <= 1'b0; + address <= accumulator[31:0]; // ver alinhamento depois + write_data <= {8'h0, communication_buffer[31:8]}; + memory_write <= 1'b1; + state <= IDLE; + end + + READ_ACUMULATOR_POS_IN_MEMORY: begin + memory_mux_selector <= 1'b0; + address <= accumulator[31:0] + {6'h0, communication_buffer[31:8], 2'b0}; // ver alinhamento depois + memory_read <= 1'b1; + state <= MEMORY_READ; + return_state <= IDLE; + end + + MEMORY_READ: begin + read_buffer <= read_data; + state <= SEND_READ_BUFFER; + end + + SET_TIMEOUT: begin + timeout <= {8'h0, communication_buffer[31:8]}; + state <= IDLE; + end + + SET_MEMORY_PAGE_SIZE: begin + memory_page_size <= communication_buffer[31:8]; + state <= IDLE; + end + + PING: begin + read_buffer <= ID; + state <= SEND_READ_BUFFER; + return_state <= IDLE; + end + + GET_ACUMULATOR: begin + read_buffer <= accumulator[31:0]; + state <= SEND_READ_BUFFER; + return_state <= IDLE; + end + + DEFINE_N_AS_PROGRAM_FINISH_POSITION: begin + end_position <= {6'h00, communication_buffer[31:8], 2'b00}; + state <= IDLE; + end + + DEFINE_ACC_AS_PROG_FINISH_POSITION: begin + end_position <= accumulator[31:0]; + state <= IDLE; + end + + SWITCH_MEMORY_TO_CORE: begin + memory_mux_selector <= 1'b1; + state <= IDLE; + end + + WRITE_NEXT_N_WORDS_FROM_ACUMULATOR: begin + memory_mux_selector <= 1'b0; + num_of_positions <= {8'h0, communication_buffer[31:8]}; + temp_buffer <= accumulator; + state <= MEMORY_WRITE_LOOP; + end + + MEMORY_WRITE_LOOP: begin + if(!num_of_positions) begin + state <= IDLE; + end else begin + num_of_positions <= num_of_positions - 1'b1; + state <= READ_WORD_FROM_SERIAL; + address <= temp_buffer[31:0]; + temp_buffer <= temp_buffer + 32'h4; + end + end + + READ_WORD_FROM_SERIAL: begin + communication_read <= 1'b1; + communication_buffer <= communication_read_data; + + if(communication_read_response) begin + state <= SAVE_WORD; + end else begin + state <= READ_WORD_FROM_SERIAL; + end + end + + SAVE_WORD: begin + memory_mux_selector <= 1'b0; + write_data <= communication_buffer[31:0]; + memory_write <= 1'b1; + + state <= MEMORY_WRITE_LOOP; + end + + + READ_NEXT_N_WORDS_FROM_ACUMULATOR: begin + memory_mux_selector <= 1'b0; + num_of_positions <= {8'h0, communication_buffer[31:8]}; + temp_buffer <= accumulator; + state <= MEMORY_READ_LOOP; + end + + MEMORY_READ_LOOP: begin + if(num_of_positions == 'd0) begin + state <= IDLE; + end else begin + num_of_positions <= num_of_positions - 1'b1; + state <= READ_WORD_FROM_MEMORY; + address <= temp_buffer[31:0]; + temp_buffer <= temp_buffer + 32'h4; + end + end + + READ_WORD_FROM_MEMORY: begin + memory_mux_selector <= 1'b0; + memory_read <= 1'b1; + state <= MEMORY_READ; + return_state <= MEMORY_READ_LOOP; + end + + SEND_READ_BUFFER: begin + communication_write_data <= read_buffer; + communication_write <= 1'b1; + state <= WAIT_WRITE_RESPONSE; + end + + WAIT_WRITE_RESPONSE: begin + if(communication_write_response) begin + state <= return_state; + end else begin + state <= WAIT_WRITE_RESPONSE; + end + end + + RUN_TESTS: begin + memory_mux_selector <= 1'b0; + num_of_pages <= communication_buffer[31:8]; + bus_mode <= 1'b1; + memory_page_number <= 24'h0; + state <= RUN_TESTS_INIT; + end + + RUN_TESTS_INIT: begin + reset_bus <= 1'b1; + timeout_counter <= 32'h0; + if(memory_page_number == num_of_pages) begin + state <= RUN_TESTS_FINISH; + end else begin + state <= RESET_CORE; + return_state <= RUN_TESTS_ENABLE_CORE; + end + end + + RUN_TESTS_ENABLE_CORE: begin + core_clk_enable <= 1'b1; + state <= RUN_TESTS_WAIT; + num_of_cycles_to_pulse <= timeout; + write_pulse <= 1'b1; + end + + RUN_TESTS_WAIT: begin + timeout_counter <= timeout_counter + 1'b1; + if(finish_execution == 1'b1 || timeout < timeout_counter ) begin + state <= RUN_TESTS_UPDATE_PAGE; + end else begin + state <= RUN_TESTS_WAIT; + end + end + + RUN_TESTS_UPDATE_PAGE: begin + core_clk_enable <= 1'b0; + memory_page_number <= memory_page_number + 1'b1; + state <= RUN_TESTS_INIT; + end + + RUN_TESTS_FINISH: begin + bus_mode <= 1'b0; + core_clk_enable <= 1'b0; + read_buffer <= RUN_TESTS_FINISH_MESSAGE; + state <= SEND_READ_BUFFER; + return_state <= IDLE; + end + + UNTIL_END_POINT: begin + memory_mux_selector <= 1'b1; + bus_mode <= 1'b0; + reset_bus <= 1'b1; + timeout_counter <= 32'h0; + state <= RESET_CORE; + return_state <= UNTIL_ENABLE_CORE; + end + + UNTIL_ENABLE_CORE: begin + core_clk_enable <= 1'b1; + state <= UNTIL_END_POINT_WAIT; + num_of_cycles_to_pulse <= timeout; + write_pulse <= 1'b1; + end + + UNTIL_END_POINT_WAIT: begin + timeout_counter <= timeout_counter + 1'b1; + if(finish_execution || timeout == timeout_counter ) begin + state <= SEND_UNTIL_FINISH_MESSAGE; + end else begin + state <= UNTIL_END_POINT_WAIT; + end + end + + SEND_UNTIL_FINISH_MESSAGE: begin + reset_bus <= 1'b1; + core_clk_enable <= 1'b0; + memory_mux_selector <= 1'b0; + read_buffer <= UNTIL_FINISH_MESSAGE; + state <= SEND_READ_BUFFER; + return_state <= SEND_UNTIL_RELATORY; + end + + SEND_UNTIL_RELATORY: begin + read_buffer <= {timeout_counter[30:0], timeout >= timeout_counter}; + state <= SEND_READ_BUFFER; + return_state <= IDLE; + end + + default: begin + state <= IDLE; + end + endcase + end +end + +endmodule +// 00 00 03 65 73 6F 66 69 6C 61 69 73 67 61 62 69 +// 80 00 00 55 \ No newline at end of file diff --git a/rtl/memory.sv b/rtl/memory.sv new file mode 100644 index 0000000..7034ae5 --- /dev/null +++ b/rtl/memory.sv @@ -0,0 +1,41 @@ +module Memory #( + parameter MEMORY_FILE = "", + parameter MEMORY_SIZE = 4096 +)( + input logic clk, + + input logic cyc_i, // Indica uma transação ativa + input logic stb_i, // Indica uma solicitação ativa + input logic we_i, // 1 = Write, 0 = Read + + input logic [31:0] addr_i, // Endereço + input logic [31:0] data_i, // Dados de entrada (para escrita) + output logic [31:0] data_o, // Dados de saída (para leitura) + + output logic ack_o // Confirmação da transação (agora assíncrona) +); + + localparam BIT_INDEX = $clog2(MEMORY_SIZE) - 1'b1; + logic [31:0] memory [(MEMORY_SIZE/4)-1:0]; + + // Inicialização da memória com arquivo, se fornecido + initial begin + if (MEMORY_FILE != "") begin + $readmemh(MEMORY_FILE, memory); + end + end + + // Leitura assíncrona + assign data_o = (cyc_i && stb_i && !we_i) ? memory[addr_i[BIT_INDEX:2]] : 32'd0; + + // Resposta assíncrona de ACK (igual ao antigo `response`) + assign ack_o = cyc_i && stb_i; + + // Escrita síncrona + always_ff @(posedge clk) begin : MEMORY_SYNC_WRITE + if (cyc_i && stb_i && we_i) begin + memory[addr_i[BIT_INDEX:2]] <= data_i; + end + end + +endmodule diff --git a/rtl/reset.sv b/rtl/reset.sv new file mode 100644 index 0000000..e27c67c --- /dev/null +++ b/rtl/reset.sv @@ -0,0 +1,67 @@ +module ResetBootSystem #( + parameter int CYCLES = 20 +) ( + input logic clk, + input logic start, + output logic rst_o, + output logic rst_n_o +); + +assign rst_n_o = ~rst_o; + +logic [5:0] counter; + +typedef enum logic [1:0] { + INIT = 2'b00, + RESET_COUNTER = 2'b01, + IDLE = 2'b10 +} reset_state_t; + +reset_state_t state; + +initial begin + state = RESET_COUNTER; + rst_o = 1'b0; + counter = 6'h00; +end + +always_ff @(posedge clk) begin : RESET_FSM + if (start) begin + state <= INIT; + end else begin + unique case (state) + INIT: begin + rst_o <= 1'b1; + state <= RESET_COUNTER; + counter <= 6'h00; + end + + RESET_COUNTER: begin + if (!rst_o) begin + state <= INIT; + end else begin + if (counter < CYCLES) begin + counter <= counter + 1; + end else if (counter == CYCLES) begin + counter <= 0; + state <= IDLE; + end else begin + state <= INIT; + end + end + end + + IDLE: begin + if (counter != 0) begin + state <= INIT; + end else begin + rst_o <= 1'b0; + end + end + + default: state <= INIT; + endcase + end +end + +endmodule \ No newline at end of file diff --git a/src/clk_divider.v b/src/clk_divider.v deleted file mode 100644 index e7131c5..0000000 --- a/src/clk_divider.v +++ /dev/null @@ -1,72 +0,0 @@ -module ClkDivider #( - parameter COUNTER_BITS = 32, - parameter PULSE_CONTROL_BITS = 32 -)( - input wire clk, - input wire reset, - input wire write_pulse, - input wire option, // 0 - pulse, 1 - auto - input wire out_enable, // 0 not, 1 - yes - input wire [COUNTER_BITS - 1:0] divider, - input wire [PULSE_CONTROL_BITS - 1:0] pulse, - output wire clk_o -); - -wire clk_o_pulse; -reg clk_o_auto; -reg [COUNTER_BITS - 1:0] clk_counter; -reg [PULSE_CONTROL_BITS - 1:0] pulse_counter; - -//assign clk_o = (out_enable == 1'b1) ? (option == 1'b0) ? -// clk_o_pulse : clk_o_auto : 1'b0; // multiplexador da saida - -assign clk_o = (option == 1'b0) ? clk_o_pulse : (out_enable == 1'b1) ? - clk_o_auto : 1'b0; - -assign clk_o_pulse = (pulse_counter != 32'd0) - ? clk : 1'b0; // liga a saida ao clock enquanto o - // contador de pulsos for maior do que 0 - -initial begin - clk_counter = 32'd0; - clk_o_auto = 1'b0; - pulse_counter = 32'd0; -end - -always @(posedge clk ) begin - if(reset == 1'b1) begin - clk_counter <= 32'd0; - clk_o_auto <= 32'd0; - end else begin - if(clk_counter == 0) begin // Gera a parte alta do ciclo de clock de saida - clk_o_auto <= 1'b1; - clk_counter <= clk_counter + 1'b1; - end else if(clk_counter == {1'b0, divider[COUNTER_BITS-1:1]}) begin // Inverte a saida do clock para a parte baixa - clk_o_auto <= 1'b0; - clk_counter <= clk_counter + 1'b1; - end else begin - clk_counter <= clk_counter + 1'b1; // inclementa o contador - end - - if(clk_counter >= divider - 1) begin // para o caso em especifico em que a divisão e por 2 - clk_counter <= 32'd0; - end - end -end - -always @(posedge clk ) begin - if(reset == 1'b1) begin - pulse_counter <= 32'd0; - end else begin - if(out_enable == 1'b1) begin - if(pulse_counter > 32'd0) begin - pulse_counter <= pulse_counter - 1'b1; - end - end - if(write_pulse == 1'b1) begin - pulse_counter <= pulse; - end - end -end - -endmodule \ No newline at end of file diff --git a/src/controller.v b/src/controller.v deleted file mode 100644 index 499c0d4..0000000 --- a/src/controller.v +++ /dev/null @@ -1,281 +0,0 @@ -module Controller #( - parameter CLK_FREQ = 25000000, - parameter BIT_RATE = 9600, - parameter PAYLOAD_BITS = 8, - parameter BUFFER_SIZE = 8, - parameter PULSE_CONTROL_BITS = 12, - parameter BUS_WIDTH = 32, - parameter WORD_SIZE_BY = 4, - parameter ID = 32'h00000001, - parameter RESET_CLK_CYCLES = 20, - parameter MEMORY_FILE = "", - parameter MEMORY_SIZE = 4096 -) ( - input wire clk, - input wire reset, - - // SPI signals - input wire sck, - input wire cs, - input wire mosi, - input wire miso, - - // SPI callback signals - input wire rw, - output wire intr, - - - // UART signals - input wire rx, - output wire tx, - - //saída de clock para o core, reset, endereço de memória, - //barramento de leitura e escrita entre outros. - output wire clk_core, - output wire reset_core, - - // Memoria principal - memoria de instruções - output wire core_memory_response, - input wire core_read_memory, - input wire core_write_memory, - input wire [31:0] core_address_memory, - input wire [31:0] core_write_data_memory, - output wire [31:0] core_read_data_memory, - - output wire [31:0] core_read_data_memory_sync, - output wire core_memory_read_response_sync, - output wire core_memory_write_response_sync, - - // Memoria de dados - sete como zero para não ser usada - output wire core_memory_response_data, - input wire core_read_memory_data, - input wire core_write_memory_data, - input wire [31:0] core_address_memory_data, - input wire [31:0] core_write_data_memory_data, - output wire [31:0] core_read_data_memory_data - -); - -// UART Wires -wire communication_read, communication_write, communication_read_response, communication_write_response, - communication_rx_empty, communication_tx_empty; -wire [31:0] communication_read_data, communication_write_data; - -// Clock Divider Wires -wire write_pulse, clk_enable; -wire [PULSE_CONTROL_BITS-1:0] num_pulses; - -// Memory Wires -wire memory_read, memory_write, memory_response; -wire [31:0] memory_read_data, memory_write_data, memory_address; - -// Data Memory Wires -wire data_memory_read, data_memory_write, data_memory_response; -wire [31:0] data_memory_read_data, data_memory_write_data, data_memory_address; - -// Memory Interpreter Wires -wire interpreter_memory_read, interpreter_memory_write, interpreter_memory_response, memory_mux_selector; -wire [31:0] interpreter_memory_read_data, interpreter_memory_write_data, interpreter_memory_address; - -// Bus Logic -assign memory_read = (memory_mux_selector == 1'b1) ? core_read_memory : (interpreter_memory_address[31] == 1'b0) ? interpreter_memory_read : 1'b0; -assign memory_write = (memory_mux_selector == 1'b1) ? core_write_memory : (interpreter_memory_address[31] == 1'b0) ? interpreter_memory_write : 1'b0; - -assign memory_address = (memory_mux_selector == 1'b1) ? (bus_mode == 1'b1) ? { - memory_page_number, core_address_memory[5:0]}: core_address_memory : interpreter_memory_address; -assign memory_write_data = (memory_mux_selector == 1'b1) ? core_write_data_memory : interpreter_memory_write_data; - -// core memory instruction response -assign core_memory_response = (memory_mux_selector == 1'b1) ? memory_response : 1'b0; -assign core_read_data_memory = (memory_mux_selector == 1'b1) ? memory_read_data : 32'h00000000; - -// Bus Logic - Data Memory -assign data_memory_read = (memory_mux_selector == 1'b1) ? core_read_memory_data : (interpreter_memory_address[31] == 1'b1) ? interpreter_memory_read : 1'b0; -assign data_memory_write = (memory_mux_selector == 1'b1) ? core_write_memory_data : (interpreter_memory_address[31] == 1'b1) ? interpreter_memory_write : 1'b0; - -assign data_memory_address = (memory_mux_selector == 1'b1) ? core_address_memory_data : {1'b0, interpreter_memory_address[30:0]}; -assign data_memory_write_data = (memory_mux_selector == 1'b1) ? core_write_data_memory_data : interpreter_memory_write_data; - -// core memory data response -assign core_memory_response_data = (memory_mux_selector == 1'b1) ? data_memory_response : 1'b0; -assign core_read_data_memory_data = (memory_mux_selector == 1'b1) ? data_memory_read_data : 32'h00000000; - -// Bus Logic - Interpreter -// Interpreter memory response -assign interpreter_memory_response = (memory_mux_selector == 1'b0) ? (interpreter_memory_address[31] == 1'b1) ? data_memory_response : memory_response : 1'b0; -assign interpreter_memory_read_data = (memory_mux_selector == 1'b0) ? (interpreter_memory_address[31] == 1'b1) ? data_memory_read_data: memory_read_data : 32'h00000000; - -reg finish_execution; -wire reset_bus, bus_mode; -wire [23:0] memory_page_number; -wire [31:0] end_position; - -always @(posedge clk ) begin - if(reset_bus) - finish_execution <= 1'b0; - else begin - if(bus_mode == 1'b1) begin - if(core_address_memory[5:0] == end_position[5:0]) - finish_execution <= 1'b1; - end else begin - if(core_address_memory == end_position || core_address_memory_data == end_position) - finish_execution <= 1'b1; - end - end -end - - -ClkDivider #( - .COUNTER_BITS (32), - .PULSE_CONTROL_BITS(PULSE_CONTROL_BITS) -) ClkDivider( - .clk (clk), - .reset(reset), - .write_pulse(write_pulse), - .option(1'b0), // 0 - pulse, 1 - auto - .out_enable(clk_enable), // 0 not, 1 - yes - .divider(), - .pulse(num_pulses), - .clk_o(clk_core) -); - -Interpreter #( - .CLK_FREQ (CLK_FREQ), - .PULSE_CONTROL_BITS(PULSE_CONTROL_BITS), - .BUS_WIDTH (BUS_WIDTH), - .ID (ID), - .RESET_CLK_CYCLES (RESET_CLK_CYCLES) -) Interpreter( - .clk (clk), - .reset(reset), - - // uart buffer signal - .communication_rx_empty(communication_rx_empty), - .communication_tx_empty(communication_tx_empty), - - // uart control signal - .communication_read (communication_read), - .communication_write(communication_write), - .communication_read_response (communication_read_response), - .communication_write_response(communication_write_response), - - // uart data signal - .communication_read_data (communication_read_data), - .communication_write_data(communication_write_data), - - // core signals - .core_clk_enable(clk_enable), - .core_reset(reset_core), - .num_of_cycles_to_pulse(num_pulses), - .write_pulse(write_pulse), - - // BUS signals - .finish_execution(finish_execution), - .reset_bus (reset_bus), - .bus_mode (bus_mode), - .memory_page_size(), - .end_position (end_position), - - // memory bus signal - .memory_response(interpreter_memory_response), - .memory_read(interpreter_memory_read), - .memory_write(interpreter_memory_write), - .memory_mux_selector(memory_mux_selector), - .memory_page_number(memory_page_number), - .write_data(interpreter_memory_write_data), - .address(interpreter_memory_address), - .read_data(interpreter_memory_read_data) -); - -UART #( - .CLK_FREQ (CLK_FREQ), - .BIT_RATE (BIT_RATE), - .PAYLOAD_BITS(PAYLOAD_BITS), - .BUFFER_SIZE (BUFFER_SIZE), - .WORD_SIZE_BY(WORD_SIZE_BY) -) Uart( - .clk (clk), - .reset(reset), - - .rx(rx), - .tx(tx), - - .uart_rx_empty(communication_rx_empty), - .uart_tx_empty(communication_tx_empty), - - .read (communication_read), - .write(communication_write), - .read_response (communication_read_response), - .write_response(communication_write_response), - - .write_data(communication_write_data), - .read_data (communication_read_data) -); -/* -SPI #( - .PAYLOAD_BITS(PAYLOAD_BITS), - .BUFFER_SIZE (BUFFER_SIZE), - .WORD_SIZE_BY(WORD_SIZE_BY) -) Spi( - .clk (clk), - .reset(reset), - - .sck (sck), - .cs (cs), - .mosi(mosi), - .miso(miso), - - .rw (rx), - .intr(intr), - - .rx_fifo_empty(communication_rx_empty), - .tx_fifo_empty(communication_tx_empty), - - .read (communication_read), - .write(communication_write), - .read_response (communication_read_response), - .write_response(communication_write_response), - - .write_data(communication_write_data), - .read_data (communication_read_data) -); -*/ -Memory #( - .MEMORY_FILE(MEMORY_FILE), - .MEMORY_SIZE(MEMORY_SIZE) -) Memory( - .clk (clk), - .reset(reset), - - .memory_read (memory_read), - .memory_write(memory_write), - .address (memory_address), - - .write_data(memory_write_data), - .read_data (memory_read_data), - .response (memory_response), - - // sync sinals - - .read_sync (core_read_data_memory_sync), - .sync_write_response(core_memory_read_response_sync), - .sync_read_response (core_memory_write_response_sync) -); - -Memory #( - .MEMORY_FILE(""), - .MEMORY_SIZE(4096) -) Data_Memory( - .clk (clk), - .reset(reset), - - .memory_read (data_memory_read), - .memory_write(data_memory_write), - .address (data_memory_address), - - .write_data(data_memory_write_data), - .read_data (data_memory_read_data), - .response (data_memory_response) -); - -endmodule diff --git a/src/fifo.v b/src/fifo.v deleted file mode 100644 index 67c6c75..0000000 --- a/src/fifo.v +++ /dev/null @@ -1,50 +0,0 @@ -module FIFO #( - parameter DEPTH = 8, - parameter WIDTH = 8 -) ( - input wire clk, - input wire reset, - input wire write, - input wire read, - input wire [WIDTH-1:0] write_data, - output wire full, - output wire empty, - output reg [WIDTH-1:0] read_data -); - -reg [WIDTH-1:0] memory[DEPTH-1:0]; -reg [5:0] read_ptr; -reg [5:0] write_ptr; - -initial begin - read_ptr = 6'd0; - write_ptr = 6'd0; -end - - -always @(posedge clk ) begin - if(reset) begin - read_ptr <= 6'd0; - end else begin - if(read == 1'b1 && empty == 1'b0) begin - read_data <= memory[read_ptr]; - read_ptr <= (read_ptr == DEPTH-1'b1) ? 'd0 : read_ptr + 1'b1; - end - end -end - -always @(posedge clk ) begin - if(reset) begin - write_ptr <= 6'd0; - end else begin - if(write == 1'b1 && full == 1'b0) begin - memory[write_ptr] <= write_data; - write_ptr <= (write_ptr == DEPTH-1'b1) ? 'd0 : write_ptr + 1'b1; - end - end -end - -assign full = ((write_ptr == read_ptr - 1) || (write_ptr == DEPTH-1 && read_ptr == 'd0)) ? 1'b1 : 1'b0; -assign empty = (write_ptr == read_ptr) ? 1'b1 : 1'b0; - -endmodule \ No newline at end of file diff --git a/src/interpreter.v b/src/interpreter.v deleted file mode 100644 index 292ddda..0000000 --- a/src/interpreter.v +++ /dev/null @@ -1,525 +0,0 @@ -module Interpreter #( - parameter CLK_FREQ = 25000000, - parameter PULSE_CONTROL_BITS = 32, - parameter BUS_WIDTH = 32, - parameter ID = 32'h7700006A, - parameter RESET_CLK_CYCLES = 20 -) ( - // Control signals - input wire clk, - input wire reset, - - // communication - input wire communication_rx_empty, - input wire communication_tx_empty, - - output reg communication_read, - output reg communication_write, - input wire communication_read_response, - input wire communication_write_response, - - input wire [31:0] communication_read_data, - output reg [31:0] communication_write_data, - - // Core signals - output reg core_clk_enable, - output reg core_reset, - output reg [PULSE_CONTROL_BITS - 1:0] num_of_cycles_to_pulse, - output reg write_pulse, - - // BUS signals - input wire finish_execution, - output reg reset_bus, // 1 - reset, 0 - normal - output reg bus_mode, // 1 - page, 0 - until - output reg [23:0] memory_page_size, - output reg [31:0] end_position, - - // Memory BUS signal - input wire memory_response, - output reg memory_read, - output reg memory_write, - output reg memory_mux_selector, // 0 - controler, 1 - core - output reg [23:0] memory_page_number, - output reg [BUS_WIDTH - 1:0] write_data, - output reg [BUS_WIDTH - 1:0] address, - input wire [BUS_WIDTH - 1:0] read_data -); - -localparam RUN_TESTS_FINISH_MESSAGE = 32'h676F6F64; -localparam UNTIL_FINISH_MESSAGE = 32'h6C75636B; -localparam TIMEOUT_CLK_CYCLES = 'd360; -localparam DELAY_CYCLES = 'd30; - -reg [7:0] state, counter, return_state; -reg [23:0] num_of_pages, num_of_positions; -reg [31:0] communication_buffer, read_buffer, timeout, timeout_counter; -reg [63:0] accumulator, temp_buffer; - -localparam IDLE = 8'b00000000; -localparam FETCH = 8'b00000001; -localparam DECODE = 8'b00000010; -localparam SEND_READ_BUFFER = 8'b00000011; -localparam WAIT_WRITE_RESPONSE = 8'b00000100; -localparam MEMORY_READ = 8'b00000101; -localparam READ_SECOND_PAGE_FROM_SERIAL = 8'b00000110; -localparam SAVE_SECOND_WORD_IN_MEMORY = 8'b00000111; -localparam MEMORY_WRITE_LOOP = 8'b00001000; -localparam READ_WORD_FROM_SERIAL = 8'b00001001; -localparam SAVE_WORD = 8'b00001010; -localparam MEMORY_READ_LOOP = 8'b00001011; -localparam READ_WORD_FROM_MEMORY = 8'b00001100; -localparam RESET_CORE_LOOP = 8'b00001101; -localparam RESET_CORE_END = 8'b00001110; -localparam UNTIL_ENABLE_CORE = 8'b00001111; -localparam UNTIL_END_POINT_WAIT = 8'b00010000; -localparam SEND_UNTIL_FINISH_MESSAGE = 8'b00010001; -localparam RUN_TESTS_ENABLE_CORE = 8'b00010010; -localparam RUN_TESTS_WAIT = 8'b00010011; -localparam RUN_TESTS_UPDATE_PAGE = 8'b00010100; -localparam RUN_TESTS_FINISH = 8'b00010101; -localparam RUN_TESTS_INIT = 8'b00010110; -localparam SEND_UNTIL_RELATORY = 8'b00010111; -localparam WRITE_CLK = 8'b01000011; // C - 0x43 -localparam STOP_CLK = 8'b01010011; // S - 0x53 -localparam RESUME_CLK = 8'b01110010; // r - 0x72 -localparam RESET_CORE = 8'b01010010; // R - 0x52 -localparam WRITE_IN_MEMORY = 8'b01010111; // W - 0x57 -localparam READ_FROM_MEMORY = 8'b01001100; // L - 0x4C -localparam LOAD_UPPER_ACUMULATOR = 8'b01010101; // U - 0x55 -localparam LOAD_LOWER_ACUMULATOR = 8'b01101100; // l - 0x6C -localparam ADD_N_TO_ACUMULATOR = 8'b01000001; // A - 0x41 -localparam WRITE_ACUMULATOR_IN_POS_N = 8'b01110111; // w - 0x77 -localparam WRITE_N_IN_POS_ACUMULATOR = 8'b01110011; // s - 0x73 -localparam READ_ACUMULATOR_POS_IN_MEMORY = 8'b01000111; // G - 0x47 -localparam SET_TIMEOUT = 8'b01010100; // T - 0x54 -localparam SET_MEMORY_PAGE_SIZE = 8'b01010000; // P - 0x50 -localparam RUN_TESTS = 8'b01000101; // E - 0x45 -localparam PING = 8'b01110000; // p - 0x70 -localparam DEFINE_N_AS_PROGRAM_FINISH_POSITION = 8'b01000100; // D - 0x44 -localparam DEFINE_ACUMULATOR_AS_PROGRAM_FINISH_POSITION = 8'b01100100; // d - 0x64 -localparam GET_ACUMULATOR = 8'b01100001; // a - 0x61 -localparam SWITCH_MEMORY_TO_CORE = 8'b01001111; // O - 0x4F -localparam WRITE_NEXT_N_WORDS_FROM_ACUMULATOR = 8'b01100101; // e - 0x65 -localparam READ_NEXT_N_WORDS_FROM_ACUMULATOR = 8'b01001101; // M - 0x4D -localparam UNTIL_END_POINT = 8'b01110101; // u - 0x75 - - - -initial begin - state = IDLE; - counter = 8'h00; - read_buffer = 32'h0; - timeout = 32'h0; - accumulator = 64'h0; -end - -always @(posedge clk) begin - communication_read <= 1'b0; - communication_write <= 1'b0; - core_reset <= 1'b0; - write_pulse <= 1'b0; - memory_read <= 1'b0; - memory_write <= 1'b0; - reset_bus <= 1'b0; - - if(reset == 1'b1) begin - state <= IDLE; - communication_buffer <= 32'h0; - accumulator <= 64'h0; - counter <= 8'h00; - core_clk_enable <= 1'b0; - memory_mux_selector <= 1'b0; - return_state <= IDLE; - num_of_pages <= 24'h0; - timeout_counter <= 8'h00; - reset_bus <= 1'b1; - bus_mode <= 1'b0; - end_position <= 32'h0; - end else begin - case (state) - IDLE: begin - counter <= 8'h00; - if(communication_rx_empty == 1'b0) begin - state <= FETCH; - end - else begin - state <= IDLE; - end - end - - FETCH: begin - communication_read <= 1'b1; - communication_buffer <= communication_read_data; - - if(communication_read_response == 1'b1) begin - state <= DECODE; - end else begin - state <= FETCH; - end - end - - DECODE: begin - return_state <= IDLE; - case (communication_buffer[7:0]) - WRITE_CLK: state <= WRITE_CLK; - STOP_CLK: state <= STOP_CLK; - RESUME_CLK: state <= RESUME_CLK; - RESET_CORE: state <= RESET_CORE; - WRITE_IN_MEMORY: state <= WRITE_IN_MEMORY; - READ_FROM_MEMORY: state <= READ_FROM_MEMORY; - LOAD_UPPER_ACUMULATOR: state <= LOAD_UPPER_ACUMULATOR; - LOAD_LOWER_ACUMULATOR: state <= LOAD_LOWER_ACUMULATOR; - ADD_N_TO_ACUMULATOR: state <= ADD_N_TO_ACUMULATOR; - WRITE_ACUMULATOR_IN_POS_N: state <= WRITE_ACUMULATOR_IN_POS_N; - WRITE_N_IN_POS_ACUMULATOR: state <= WRITE_N_IN_POS_ACUMULATOR; - READ_ACUMULATOR_POS_IN_MEMORY: state <= READ_ACUMULATOR_POS_IN_MEMORY; - SET_TIMEOUT: state <= SET_TIMEOUT; - SET_MEMORY_PAGE_SIZE: state <= SET_MEMORY_PAGE_SIZE; - RUN_TESTS: state <= RUN_TESTS; - PING: state <= PING; - DEFINE_N_AS_PROGRAM_FINISH_POSITION: state <= DEFINE_N_AS_PROGRAM_FINISH_POSITION; - DEFINE_ACUMULATOR_AS_PROGRAM_FINISH_POSITION: state <= DEFINE_ACUMULATOR_AS_PROGRAM_FINISH_POSITION; - GET_ACUMULATOR: state <= GET_ACUMULATOR; - SWITCH_MEMORY_TO_CORE: state <= SWITCH_MEMORY_TO_CORE; - WRITE_NEXT_N_WORDS_FROM_ACUMULATOR: state <= WRITE_NEXT_N_WORDS_FROM_ACUMULATOR; - READ_NEXT_N_WORDS_FROM_ACUMULATOR: state <= READ_NEXT_N_WORDS_FROM_ACUMULATOR; - UNTIL_END_POINT: state <= UNTIL_END_POINT; - default: state <= IDLE; - endcase - end - - WRITE_CLK: begin - core_clk_enable <= 1'b1; - num_of_cycles_to_pulse <= {8'h00, communication_buffer[31:8]}; - write_pulse <= 1'b1; - state <= IDLE; - end - STOP_CLK: begin - core_clk_enable <= 1'b0; - state <= IDLE; - end - - RESUME_CLK: begin - core_clk_enable <= 1'b1; - state <= IDLE; - end - - RESET_CORE: begin - counter <= 8'h00; - core_reset <= 1'b1; - core_clk_enable <= 1'b1; - num_of_cycles_to_pulse <= RESET_CLK_CYCLES; - write_pulse <= 1'b1; - state <= RESET_CORE_LOOP; - end - - RESET_CORE_LOOP: begin - core_reset <= 1'b1; - counter <= counter + 1'b1; - if(counter == RESET_CLK_CYCLES) begin - core_clk_enable <= 1'b0; - state <= RESET_CORE_END; - end else begin - state <= RESET_CORE_LOOP; - end - end - - RESET_CORE_END: begin - core_reset <= 1'b0; - core_clk_enable <= 1'b0; - state <= return_state; - end - - WRITE_IN_MEMORY: begin - memory_mux_selector <= 1'b0; - address <= {communication_buffer[31], 6'h0, communication_buffer[30:8], 2'b0}; - - if(communication_rx_empty == 1'b0) begin - state <= READ_SECOND_PAGE_FROM_SERIAL; - end else begin - state <= WRITE_IN_MEMORY; - end - end - - READ_SECOND_PAGE_FROM_SERIAL: begin - communication_read <= 1'b1; - communication_buffer <= communication_read_data; - - if(communication_read_response == 1'b1) begin - state <= SAVE_SECOND_WORD_IN_MEMORY; - end else begin - state <= READ_SECOND_PAGE_FROM_SERIAL; - end - end - - SAVE_SECOND_WORD_IN_MEMORY: begin - memory_mux_selector <= 1'b0; - write_data <= communication_buffer[31:0]; - memory_write <= 1'b1; - state <= IDLE; - end - - READ_FROM_MEMORY: begin - memory_mux_selector <= 1'b0; - address <= {communication_buffer[31], 6'h0, communication_buffer[30:8], 2'b0}; - memory_read <= 1'b1; - state <= MEMORY_READ; - end - - LOAD_UPPER_ACUMULATOR: begin - accumulator <= {32'h0, communication_buffer[31:8], accumulator[7:0]}; - state <= IDLE; - end - - LOAD_LOWER_ACUMULATOR: begin - accumulator <= {accumulator[63:8], communication_buffer[15:8]}; - state <= IDLE; - end - - ADD_N_TO_ACUMULATOR: begin - accumulator <= accumulator + {{40{communication_buffer[31]}}, communication_buffer[31:8]}; - state <= IDLE; - end - - WRITE_ACUMULATOR_IN_POS_N: begin - memory_mux_selector <= 1'b0; - address <= {communication_buffer[31], 6'h0, communication_buffer[30:8], 2'b0}; // ver alinhamento depois - write_data <= accumulator[31:0]; - memory_write <= 1'b1; - state <= IDLE; - end - - WRITE_N_IN_POS_ACUMULATOR: begin - memory_mux_selector <= 1'b0; - address <= accumulator[31:0]; // ver alinhamento depois - write_data <= {8'h0, communication_buffer[31:8]}; - memory_write <= 1'b1; - state <= IDLE; - end - - READ_ACUMULATOR_POS_IN_MEMORY: begin - memory_mux_selector <= 1'b0; - address <= accumulator[31:0] + {6'h0, communication_buffer[31:8], 2'b0}; // ver alinhamento depois - memory_read <= 1'b1; - state <= MEMORY_READ; - return_state <= IDLE; - end - - MEMORY_READ: begin - read_buffer <= read_data; - state <= SEND_READ_BUFFER; - end - - SET_TIMEOUT: begin - timeout <= {8'h0, communication_buffer[31:8]}; - state <= IDLE; - end - - SET_MEMORY_PAGE_SIZE: begin - memory_page_size <= communication_buffer[31:8]; - state <= IDLE; - end - - PING: begin - read_buffer <= ID; - state <= SEND_READ_BUFFER; - return_state <= IDLE; - end - - GET_ACUMULATOR: begin - read_buffer <= accumulator[31:0]; - state <= SEND_READ_BUFFER; - return_state <= IDLE; - end - - DEFINE_N_AS_PROGRAM_FINISH_POSITION: begin - end_position <= {6'h00, communication_buffer[31:8], 2'b00}; - state <= IDLE; - end - - DEFINE_ACUMULATOR_AS_PROGRAM_FINISH_POSITION: begin - end_position <= accumulator[31:0]; - state <= IDLE; - end - - SWITCH_MEMORY_TO_CORE: begin - memory_mux_selector <= 1'b1; - state <= IDLE; - end - - WRITE_NEXT_N_WORDS_FROM_ACUMULATOR: begin - memory_mux_selector <= 1'b0; - num_of_positions <= {8'h0, communication_buffer[31:8]}; - temp_buffer <= accumulator; - state <= MEMORY_WRITE_LOOP; - end - - MEMORY_WRITE_LOOP: begin - if(num_of_positions == 1'b0) begin - state <= IDLE; - end else begin - num_of_positions <= num_of_positions - 1'b1; - state <= READ_WORD_FROM_SERIAL; - address <= temp_buffer[31:0]; - temp_buffer <= temp_buffer + 32'h4; - end - end - - READ_WORD_FROM_SERIAL: begin - communication_read <= 1'b1; - communication_buffer <= communication_read_data; - - if(communication_read_response == 1'b1) begin - state <= SAVE_WORD; - end else begin - state <= READ_WORD_FROM_SERIAL; - end - end - - SAVE_WORD: begin - memory_mux_selector <= 1'b0; - write_data <= communication_buffer[31:0]; - memory_write <= 1'b1; - - state <= MEMORY_WRITE_LOOP; - end - - - READ_NEXT_N_WORDS_FROM_ACUMULATOR: begin - memory_mux_selector <= 1'b0; - num_of_positions <= {8'h0, communication_buffer[31:8]}; - temp_buffer <= accumulator; - state <= MEMORY_READ_LOOP; - end - - MEMORY_READ_LOOP: begin - if(num_of_positions == 1'b0) begin - state <= IDLE; - end else begin - num_of_positions <= num_of_positions - 1'b1; - state <= READ_WORD_FROM_MEMORY; - address <= temp_buffer[31:0]; - temp_buffer <= temp_buffer + 32'h4; - end - end - - READ_WORD_FROM_MEMORY: begin - memory_mux_selector <= 1'b0; - memory_read <= 1'b1; - state <= MEMORY_READ; - return_state <= MEMORY_READ_LOOP; - end - - SEND_READ_BUFFER: begin - communication_write_data <= read_buffer; - communication_write <= 1'b1; - state <= WAIT_WRITE_RESPONSE; - end - - WAIT_WRITE_RESPONSE: begin - if(communication_write_response == 1'b1) begin - state <= return_state; - end else begin - state <= WAIT_WRITE_RESPONSE; - end - end - - RUN_TESTS: begin - memory_mux_selector <= 1'b0; - num_of_pages <= communication_buffer[31:8]; - bus_mode <= 1'b1; - memory_page_number <= 24'h0; - state <= RUN_TESTS_INIT; - end - - RUN_TESTS_INIT: begin - reset_bus <= 1'b1; - timeout_counter <= 32'h0; - if(memory_page_number == num_of_pages) begin - state <= RUN_TESTS_FINISH; - end else begin - state <= RESET_CORE; - return_state <= RUN_TESTS_ENABLE_CORE; - end - end - - RUN_TESTS_ENABLE_CORE: begin - core_clk_enable <= 1'b1; - state <= RUN_TESTS_WAIT; - num_of_cycles_to_pulse <= timeout; - write_pulse <= 1'b1; - end - - RUN_TESTS_WAIT: begin - timeout_counter <= timeout_counter + 1'b1; - if(finish_execution == 1'b1 || timeout < timeout_counter ) begin - state <= RUN_TESTS_UPDATE_PAGE; - end else begin - state <= RUN_TESTS_WAIT; - end - end - - RUN_TESTS_UPDATE_PAGE: begin - core_clk_enable <= 1'b0; - memory_page_number <= memory_page_number + 1'b1; - state <= RUN_TESTS_INIT; - end - - RUN_TESTS_FINISH: begin - bus_mode <= 1'b0; - core_clk_enable <= 1'b0; - read_buffer <= RUN_TESTS_FINISH_MESSAGE; - state <= SEND_READ_BUFFER; - return_state <= IDLE; - end - - UNTIL_END_POINT: begin - memory_mux_selector <= 1'b1; - bus_mode <= 1'b0; - reset_bus <= 1'b1; - timeout_counter <= 32'h0; - state <= RESET_CORE; - return_state <= UNTIL_ENABLE_CORE; - end - - UNTIL_ENABLE_CORE: begin - core_clk_enable <= 1'b1; - state <= UNTIL_END_POINT_WAIT; - num_of_cycles_to_pulse <= timeout; - write_pulse <= 1'b1; - end - - UNTIL_END_POINT_WAIT: begin - timeout_counter <= timeout_counter + 1'b1; - if(finish_execution == 1'b1 || timeout == timeout_counter ) begin - state <= SEND_UNTIL_FINISH_MESSAGE; - end else begin - state <= UNTIL_END_POINT_WAIT; - end - end - - SEND_UNTIL_FINISH_MESSAGE: begin - reset_bus <= 1'b1; - core_clk_enable <= 1'b0; - memory_mux_selector <= 1'b0; - read_buffer <= UNTIL_FINISH_MESSAGE; - state <= SEND_READ_BUFFER; - return_state <= SEND_UNTIL_RELATORY; - end - - SEND_UNTIL_RELATORY: begin - read_buffer <= {timeout_counter[30:0], timeout >= timeout_counter}; - state <= SEND_READ_BUFFER; - return_state <= IDLE; - end - - default: begin - state <= IDLE; - end - endcase - end -end - -endmodule -// 00 00 03 65 73 6F 66 69 6C 61 69 73 67 61 62 69 -// 80 00 00 55 \ No newline at end of file diff --git a/src/memory.v b/src/memory.v deleted file mode 100644 index dc515b5..0000000 --- a/src/memory.v +++ /dev/null @@ -1,50 +0,0 @@ -module Memory #( - parameter MEMORY_FILE = "", - parameter MEMORY_SIZE = 4096 -)( - input wire clk, - input wire reset, - input wire memory_read, - input wire memory_write, - input wire [31:0] address, - input wire [31:0] write_data, - output wire [31:0] read_data, - output reg [31:0] read_sync, - output wire response, - output reg sync_write_response, - output reg sync_read_response -); - -reg [31:0] memory [(MEMORY_SIZE/4)-1: 0]; -integer i; - -assign read_data = (memory_read == 1'b1) ? memory[{2'b00, address[31:2]}] : 32'h00000000; -assign response = memory_read | memory_write; - -initial begin - `ifdef __ICARUS__ - for (i = 0; i < (MEMORY_SIZE/4)-1; i = i + 1) begin - memory[i] = 32'h00000000; - end - `endif - - if(MEMORY_FILE != "") begin - $readmemh(MEMORY_FILE, memory, 0, (MEMORY_SIZE/4) - 1); - end -end - -always @(posedge clk) begin - if(memory_read == 1'b1) begin - read_sync <= memory[{2'b00, address[31:2]}]; - end - if(memory_write == 1'b1) begin - memory[{2'b00, address[31:2]}] <= write_data; - end -end - -always @(posedge clk ) begin - sync_write_response <= memory_write; - sync_read_response <= memory_read; -end - -endmodule diff --git a/src/reset.v b/src/reset.v deleted file mode 100644 index ebe903c..0000000 --- a/src/reset.v +++ /dev/null @@ -1,64 +0,0 @@ -module ResetBootSystem #( - parameter CYCLES = 20 -) ( - input wire clk, - input wire start, - output reg reset_o, - output wire resetn_o -); - -assign resetn_o = ~reset_o; - -reg [1:0] state; -reg [5:0] counter; - -parameter INIT = 2'b00; -parameter RESET_COUNTER = 2'b01; -parameter IDLE = 2'b10; - -initial begin - state = 2'b01; - reset_o = 2'b0; - counter = 6'h00; -end - -always @(posedge clk ) begin - if(start == 1'b1) begin - state <= INIT; - end - - case (state) - INIT: begin - reset_o <= 1'b1; - state <= RESET_COUNTER; - counter <= 6'h00; - end - - RESET_COUNTER: begin - if(reset_o == 1'b0) begin - state <= INIT; - end else begin - if(counter < CYCLES) begin - counter <= counter + 1; - end else if(counter == CYCLES) begin - counter <= 0; - state <= IDLE; - end else begin - state <= INIT; - end - end - end - - IDLE: begin - if(counter != 0) begin - state <= INIT; - end else begin - reset_o <= 1'b0; - end - end - - default: state <= INIT; - endcase -end - -endmodule diff --git a/testbenchs/clk_divider_tb.sv b/testbenchs/clk_divider_tb.sv new file mode 100644 index 0000000..7b8115e --- /dev/null +++ b/testbenchs/clk_divider_tb.sv @@ -0,0 +1,80 @@ +module ClkDivider_tb; + parameter COUNTER_BITS = 32; + parameter PULSE_CONTROL_BITS = 32; + + logic clk; + logic rst_n; + logic write_pulse; + logic option; + logic out_enable; + logic [COUNTER_BITS-1:0] divider; + logic [PULSE_CONTROL_BITS-1:0] pulse; + logic clk_o; + + ClkDivider #( + .COUNTER_BITS (COUNTER_BITS), + .PULSE_CONTROL_BITS (PULSE_CONTROL_BITS) + ) uut ( + .clk (clk), + .rst_n (rst_n), + .write_pulse (write_pulse), + .option (option), + .out_enable (out_enable), + .divider (divider), + .pulse (pulse), + .clk_o (clk_o) + ); + + // Clock generation + always #5 clk = ~clk; + + initial begin + // Inicialização dos sinais + clk = 0; + rst_n = 0; + write_pulse = 0; + option = 0; + out_enable = 0; + divider = 10; + pulse = 5; + + // Reset ativo + #10 rst_n = 1; + assert(clk_o == 0) else $fatal(1, "Erro: clk_o deveria estar em 0 após reset"); + + // Teste de divisão de clock no modo automático + #20 out_enable = 1; + option = 1; + + #50; + assert(clk_o == 1 || clk_o == 0) else $fatal(1, "Erro: clk_o inválido no modo automático"); + + #200; + + // Teste de geração de pulsos + option = 0; + write_pulse = 1; + pulse = 50; + #10 write_pulse = 0; + + #50; + assert(clk_o == clk) else $fatal(1, "Erro: clk_o deveria seguir clk no modo pulse quando pulse_counter > 0"); + + #100; + + // Teste de reset + rst_n = 0; + #20 rst_n = 1; + + assert(clk_o == 0) else $fatal(1, "Erro: clk_o deveria estar em 0 após reset"); + + #200; + + $finish; + end + + initial begin + $dumpfile("build/ClkDivider_tb.vcd"); + $dumpvars(0, ClkDivider_tb); + end +endmodule diff --git a/testbenchs/controller_tb.sv b/testbenchs/controller_tb.sv new file mode 100644 index 0000000..08c3729 --- /dev/null +++ b/testbenchs/controller_tb.sv @@ -0,0 +1,142 @@ +`timescale 1ns / 1ns + +module controller_tb(); + +logic clk, rx, rst_n, tx; +logic [7:0] tx_data; +logic tx_en; +logic tx_busy; +logic [7:0] tx_data_memory [0:16]; +logic [4:0] pointer; + +initial begin + $dumpfile("build/controller.vcd"); + $dumpvars; + clk = 0; + rst_n = 0; + + #20 rst_n = 1; + + #12000; + + $finish; +end + +logic [7:0] uart_rx_data; + +always #1 clk = ~clk; + +parameter BIT_RATE = 4000000; +parameter PAYLOAD_BITS = 8; +parameter CLK_FREQ = 50000000; + +uart_rx #( + .BIT_RATE (BIT_RATE), + .PAYLOAD_BITS (PAYLOAD_BITS), + .CLK_HZ (CLK_FREQ) +) i_uart_rx( + .clk (clk ), // Top level system clock input. + .resetn (rst_n ), // Asynchronous active low reset. + .uart_rxd (tx ), // UART Recieve pin. + .uart_rx_en (1'b1 ), // Recieve enable + .uart_rx_break( ), // Did we get a BREAK message? + .uart_rx_valid( ), // Valid data recieved and available. + .uart_rx_data (uart_rx_data ) // The recieved data. +); + +uart_tx #( + .BIT_RATE (BIT_RATE), + .PAYLOAD_BITS (PAYLOAD_BITS), + .CLK_HZ (CLK_FREQ) +) tx_tb ( + .clk (clk ), + .resetn (rst_n ), + .uart_txd (rx ), // serial_tx + .uart_tx_en (tx_en ), + .uart_tx_busy (tx_busy), + .uart_tx_data (tx_data) +); + + +Controller #( + .CLK_FREQ (50000000), + .BIT_RATE (BIT_RATE), + .PAYLOAD_BITS (8), + .BUFFER_SIZE (8), + .PULSE_CONTROL_BITS (32), + .BUS_WIDTH (32), + .WORD_SIZE_BY (4), + .ID (32'h7700006A), + .RESET_CLK_CYCLES (20), + .MEMORY_FILE (""), + .MEMORY_SIZE (4096) +) u_Controller ( + .clk (clk), + .rst_n (rst_n), + + // SPI signals + .sck_i (), + .cs_i (), + .mosi_i (), + .miso_o (), + + // SPI callback signals + .rw_i (), + .intr_o (), + + // UART signals + .rx (rx), + .tx (tx), + + // Clock, reset, and bus signals + .clk_core_o (), + .rst_core_o (), + + // Barramento padrão (não AXI4-Lite) + .core_cyc_i (), + .core_stb_i (), + .core_we_i (), + .core_addr_i (), + .core_data_i (), + .core_data_o (), + .core_ack_o () +); + + +initial begin + tx_data_memory[0] = 8'h00; + tx_data_memory[1] = 8'h00; + tx_data_memory[2] = 8'h00; + tx_data_memory[3] = 8'h70; + tx_data_memory[4] = 8'h00; + tx_data_memory[5] = 8'h00; + tx_data_memory[6] = 8'h00; + tx_data_memory[7] = 8'h57; + tx_data_memory[8] = 8'h73; + tx_data_memory[9] = 8'h75; + tx_data_memory[10]= 8'h6E; + tx_data_memory[11]= 8'h67; + tx_data_memory[12]= 8'h00; + tx_data_memory[13]= 8'h00; + tx_data_memory[14]= 8'h00; + tx_data_memory[15]= 8'h4C; +end + + +always_ff @( posedge clk ) begin : TX_DATA_SEND + if (!rst_n) begin + tx_data <= 8'h00; + pointer <= 0; + end else begin + if (!tx_busy && !pointer[4] && !tx_en) begin + tx_data <= tx_data_memory[pointer]; + pointer <= pointer + 1; + tx_en <= 1'b1; + end else begin + tx_en <= 1'b0; + end + end + +end + +endmodule diff --git a/testbenchs/fifo_tb.sv b/testbenchs/fifo_tb.sv new file mode 100644 index 0000000..028d3b8 --- /dev/null +++ b/testbenchs/fifo_tb.sv @@ -0,0 +1,86 @@ +`timescale 1ns/1ps + +module fifo_tb; + parameter DEPTH = 8; + parameter WIDTH = 8; + + logic clk = 0; + logic rst_n; + logic wr_en_i; + logic rd_en_i; + logic [WIDTH-1:0] write_data_i; + logic full_o; + logic empty_o; + logic [WIDTH-1:0] read_data_o; + + // Instância do DUT (Device Under Test) + FIFO #( + .DEPTH(DEPTH), + .WIDTH(WIDTH) + ) uut ( + .clk (clk), + .rst_n (rst_n), + .wr_en_i (wr_en_i), + .rd_en_i (rd_en_i), + .write_data_i (write_data_i), + .full_o (full_o), + .empty_o (empty_o), + .read_data_o (read_data_o) + ); + + // Geração de clock + always #5 clk = ~clk; + + initial begin + $dumpfile("build/fifo_tb.vcd"); + $dumpvars(0, fifo_tb); + + // Reset + rst_n = 0; + wr_en_i = 0; + rd_en_i = 0; + write_data_i = 0; + #20 rst_n = 1; + + // Escrever até encher a FIFO + for (int i = 0; i < DEPTH; i++) begin + write_data_i = i; + wr_en_i = 1; + #10; + wr_en_i = 0; + #10; + end + + // Verificar que a FIFO está cheia + assert(full_o) else $error("Erro: FIFO deveria estar cheia!"); + + // Tentar escrever com a FIFO cheia + write_data_i = 42; + wr_en_i = 1; + #10; + wr_en_i = 0; + assert(full_o) else $error("Erro: FIFO deveria continuar cheia!"); + + // Ler até esvaziar + for (int i = 0; i < DEPTH; i++) begin + rd_en_i = 1; + #10; + rd_en_i = 0; + assert(read_data_o == i) else $error("Erro: Dados lidos incorretamente!"); + #10; + end + + // Verificar que a FIFO está vazia + assert(empty_o) else $error("Erro: FIFO deveria estar vazia!"); + + // Teste de leitura com FIFO vazia + rd_en_i = 1; + #10; + rd_en_i = 0; + assert(empty_o) else $error("Erro: FIFO deveria continuar vazia!"); + + // Finaliza simulação + $display("Testbench finalizado com sucesso."); + $finish; + end +endmodule diff --git a/tests/clk_divider_test.v b/tests/clk_divider_test.v deleted file mode 100644 index 27273df..0000000 --- a/tests/clk_divider_test.v +++ /dev/null @@ -1,72 +0,0 @@ -module clk_divider_tb (); - -parameter COUNTER_BITS = 32; -parameter PULSE_BITS = 32; - -wire clk_o; -reg option, out_enable, clk, reset, write_pulse; -reg [COUNTER_BITS - 1 : 0] divider; -reg [PULSE_BITS - 1 : 0] pulse; - -initial begin - $dumpfile("build/clk_divider.vcd"); - $dumpvars; - - clk = 0; - reset = 0; - option = 1'b1; - out_enable = 1'b1; - pulse = 32'd0; - divider = 32'd0; - write_pulse = 1'b0; - - #2 - reset = 1'b1; - #2 - reset = 1'b0; - - #30 - - out_enable = 1'b0; - - #30 - - out_enable = 1'b1; - - #30 - - pulse = 32'd8; - - #16 - - write_pulse = 1'b1; - - #2 - - write_pulse = 1'b0; - - #2 - - - #40 - - $finish; -end - -always #1 clk = ~clk; - -ClkDivider #( - .COUNTER_BITS(COUNTER_BITS), - .PULSE_CONTROL_BITS(PULSE_BITS) -) ClkDivider( - .clk(clk), - .reset(reset), - .option(option), - .write_pulse(write_pulse), - .out_enable(out_enable), - .divider(divider), - .pulse(pulse), - .clk_o(clk_o) -); - -endmodule diff --git a/tests/controller_test.v b/tests/controller_test.v deleted file mode 100644 index 672d325..0000000 --- a/tests/controller_test.v +++ /dev/null @@ -1,53 +0,0 @@ -module controller_tb(); - -reg clk, rx, reset; -wire tx; - -initial begin - $dumpfile("build/controller.vcd"); - $dumpvars; - clk = 0; - reset = 1; - - #20 reset = 0; - - #1000; - - $finish; -end - - -always #1 clk = ~clk; - - -Controller #( - .CLK_FREQ(25000000), - .BIT_RATE(115200), - .PAYLOAD_BITS(8), - .BUFFER_SIZE(8), - .PULSE_CONTROL_BITS(32), - .BUS_WIDTH(32), - .WORD_SIZE_BY(4), - .ID(32'h0000004A), - .RESET_CLK_CYCLES(20), - .MEMORY_FILE(""), - .MEMORY_SIZE(4096) -) Controller( - .clk(clk), - .reset(reset), - - .tx(tx), - .rx(rx), - - .clk_core(), - .reset_core(), - - .core_memory_response(), - .core_read_memory(), - .core_write_memory(), - .core_address_memory(), - .core_write_data_memory(), - .core_read_data_memory() -); - -endmodule diff --git a/tests/fifo_test.v b/tests/fifo_test.v deleted file mode 100644 index d9798c0..0000000 --- a/tests/fifo_test.v +++ /dev/null @@ -1,78 +0,0 @@ -module fifo_tb (); - -reg clk, reset, read, write; -reg [7:0] write_data, buffer; -wire [7:0] read_data; - -initial begin - clk = 1'b0; - reset = 1'b0; -end - -FIFO #( - .DEPTH(8), - .WIDTH(8) -) fifo ( - .clk(clk), - .reset(reset), - .write(write), - .read(read), - .write_data(write_data), - .full(), - .empty(), - .read_data(read_data) -); - -always #1 clk = ~clk; - -initial begin - $dumpfile("build/fifo.vcd"); - $dumpvars; - - clk = 1'b0; - reset = 1'b1; - read = 1'b0; - write = 1'b0; - - #10 reset = 1'b0; - - write_data = 8'h70; - write = 1'b1; - - #2 - - write_data = 8'h71; - write = 1'b1; - - #2 - - write = 1'b0; - read = 1'b1; - - #2 - - read = 1'b0; - buffer = read_data; - - #2 - - write_data = 8'h72; - - write = 1'b1; - - #2 - - write = 1'b0; - read = 1'b1; - - #2 - - buffer = read_data; - read = 1'b0; - - #2 - - $finish; -end - -endmodule diff --git a/tests/reset_test.v b/tests/reset_test.v deleted file mode 100644 index 6acab34..0000000 --- a/tests/reset_test.v +++ /dev/null @@ -1,27 +0,0 @@ -module reset_tb (); - -reg clk; -wire reset, resetn; - -always #1 clk = ~clk; - -ResetBootSystem #( - .CYCLES(20) -) Reset( - .clk(clk), - .reset_o(reset), - .resetn_o(resetn) -); - -initial begin - $dumpfile("build/reset.vcd"); - $dumpvars; - - clk = 1'b0; - - #60 - - $finish; -end - -endmodule