adjust optimizer for instructions with a separate destination

[LADSoft]

in powerpc and other architectures, it deviates from x86 in that in x86 the destination is also one of the sources, whereas in powerpc the destination is separate from the sources.

The primary place this is going to make a difference is in the register allocator. There may be other differences as well such as in how we handle rewrite functions in the optimizer. But that might be handled by a better way of specifying addressing modes.

[chuggafan]

I think this will also be useful for future APX work.
Panther Lake intel CPUs have "Advanced Performance Extensions" which use a Three Address Code that allows for constructs such as:
add <dest>, src1, src2