Add ShiftArray

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Author: seldridge

src/main/scala/esp/examples/ShiftArray.scala

@@ -0,0 +1,50 @@
+// Copyright 2019 IBM
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package esp.examples
+
+import chisel3._
+import chisel3.util.Valid
+import chisel3.experimental.withReset
+
+class ShiftArrayIO[A <: Data](rows: Int, cols: Int, gen: A) extends Bundle {
+
+  val in = Flipped(Valid(Vec(rows, gen.cloneType)))
+  val out = Valid(Vec(rows, Vec(cols, gen.cloneType)))
+
+}
+
+class ShiftArray[A <: Data](val rows: Int, val cols: Int, gen: A) extends Module {
+
+  val io = IO(new ShiftArrayIO(rows, cols, gen))
+
+  val regArray = Seq.fill(rows)(Seq.fill(cols)(Reg(gen)))
+  val count = RegInit(0.U(cols.W))
+
+  /* Shift regArray left when the input fires */
+  when (io.in.fire()) {
+    count := count ## 1.U
+    regArray
+      .zip(io.in.bits)
+      .foreach{ case (a, in) => a.foldLeft(in){ case (r, l) => l := r; l } }
+  }
+
+  /* Route the regArray to the output */
+  io.out.bits.flatten
+    .zip(regArray.flatten)
+    .foreach{ case (l, r) => l := r }
+
+  io.out.valid := count.toBools.last
+
+}

src/test/scala/esptests/examples/ShiftArraySpec.scala

@@ -0,0 +1,69 @@
+// Copyright 2019 IBM
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package esptests.examples
+
+import chisel3._
+import chisel3.iotesters.{ChiselFlatSpec, Driver, AdvTester}
+
+import esp.examples.ShiftArray
+
+class ShiftArrayTester[A <: Bits](dut: ShiftArray[A]) extends AdvTester(dut) {
+  def init(): Unit = {
+    Seq(dut.io.in.valid).map(p => wire_poke(p, false))
+  }
+
+  def load(in: Seq[Int]): Unit = {
+    require(in.size % dut.cols == 0)
+    in
+      .grouped(dut.cols)
+      .foreach{ case a =>
+        wire_poke(dut.io.in.valid, 1)
+        a.zipWithIndex.map{ case (b, i) => wire_poke(dut.io.in.bits(i), b) }
+        step(1)
+        wire_poke(dut.io.in.valid, 0) }
+  }
+
+  val input: Seq[Int] = 0 until dut.rows * dut.cols
+
+  reset(4)
+  expect(dut.io.out.valid, false)
+
+  init()
+  step(1)
+
+  load(0 until 9)
+
+  expect(dut.io.out.valid, true)
+  println(peek(dut.io.out.bits).mkString(", "))
+
+  load(9 until 12)
+  expect(dut.io.out.valid, true)
+  println(peek(dut.io.out.bits).mkString(", "))
+
+  reset(1)
+  expect(dut.io.out.valid, false)
+}
+
+class ShiftArraySpec extends ChiselFlatSpec {
+
+  behavior of "ShiftArray"
+
+  it should "present a 3x3 array" in {
+    Driver(() => new ShiftArray(3, 3, UInt(16.W)), "treadle") {
+      dut => new ShiftArrayTester(dut)
+    } should be (true)
+  }
+
+}