feat: RV32A atomics, FENCE.I, per-FU pipeline, and cache coherence fixes

## New instructions

- **RV32A**: LR.W, SC.W, and all AMO variants (AMOSWAP, AMOADD, AMOXOR,
  AMOAND, AMOOR, AMOMAX, AMOMIN, AMOMAXU, AMOMINU) now route through the
  cache layer via `lr_w` / `sc_w` / `amo_w` on the `Bus` trait.
  LR/SC reservations are tracked per-hart inside `CacheController`
  (and per-hart in the CPU registers as a fallback for bypass mode).
  Any store to a reserved word cancels the reservation.
- **FENCE**: forwards to `Bus::fence()` (was a no-op).
- **FENCE.I**: implemented as `Bus::fence_i()`, invalidates the I-cache
  so self-modifying code picks up freshly written instructions.
- Instruction panel type badges extended: `[A]` (atomic) and `[F]` (float).

## Cache coherence bug fixes (multi-level hierarchy)

Four bugs that caused silent data corruption when L1 D-cache + L2 are both
enabled (program crash at PC=0x00000000 with rust-to-raven.elf):

1. **Blanket L2 invalidation after write-back stores removed.**
   `dcache_store_bytes` was invalidating L2 after every store.  On a
   write-allocate miss this sequence ran: fetch L2 → evict dirty D-cache
   line → writeback dirty data to L2 → then invalidate that same L2 line.
   Data ended up in neither cache level nor RAM (silent loss, corrupted
   stack return addresses → PC=0).

2. **Write-through stores now correctly invalidate L2.**
   Write-through keeps D-cache lines clean, so evictions never writeback
   to L2.  After a write-through store, the L2 copy is stale and must be
   dropped so future misses re-read the updated value from RAM.

3. **`sync_to_ram` writeback order fixed.**
   Was: D-cache first, then L2. Now: L2 (reversed outer levels) first,
   then D-cache.  D-cache is always authoritative; writing L2 last would
   overwrite correct D-cache data with stale L2 data in RAM.

4. **`flush_all` writeback order fixed** (same root cause as #3).
   Called when the user toggles the cache off; same reversal applied.

## Pipeline improvements

- Per-FU (ALU, MUL, DIV, FPU, LSU, SYS) stall counters and configurable
  functional-unit counts.
- Branch predictor extended: not-taken (default), always-taken, BTFNT,
  and 2-bit dynamic.
- Per-hazard stall tag breakdown in the pipeline footer.
- `.pcfg` config format updated: per-bypass-path flags replace single
  `forwarding` boolean; `fu.*` counts added.
- Speculative Gantt: in-flight speculative instructions shown with distinct
  styling; flushed instructions marked.

## rust-to-raven

- `raven_api` restructured: `hart.rs` moved to `hardware_thread/`,
  `atomic/` module added with `Arc`, `AtomicBool`, `AtomicU32`, etc.
  backed by LR.W/SC.W so they actually work on the simulator.
- `main.rs` updated to use `HartTask` with a closure-based API.

Author: Gaok1

README.md

@@ -43,7 +43,7 @@ Requires Rust 1.75+. No other dependencies.
   - **R/W**: still RAM view, but auto-follows the last memory access address from `LOAD` and `STORE`
   - **Registers**: integer or float register bank with per-register age highlighting; pin with `P`
   - **Dyn**: self-narrating mode for single-stepping — STORE → RAM centered on the written address (`▶`); LOAD / ALU / branch → register bank so you see the result
-- Instruction memory panel: type badge `[R][I][S][B][U][J]`, execution heat `×N`, branch outcome
+- Instruction memory panel: type badge `[R][I][S][B][U][J][A][F]`, execution heat `×N`, branch outcome
 - Instruction decoder: full field breakdown (opcode, funct3/7, rs1/rs2/rd, immediate, sign-extended)
 
 ### Cache Simulator (Tab 3)
@@ -66,7 +66,7 @@ Requires Rust 1.75+. No other dependencies.
 
 | Extension | Instructions |
 |-----------|-------------|
-| RV32I | ADD, SUB, AND, OR, XOR, SLL, SRL, SRA, SLT, SLTU, ADDI, ANDI, ORI, XORI, SLTI, SLTIU, SLLI, SRLI, SRAI, LB, LH, LW, LBU, LHU, SB, SH, SW, BEQ, BNE, BLT, BGE, BLTU, BGEU, JAL, JALR, LUI, AUIPC, ECALL, EBREAK |
+| RV32I | ADD, SUB, AND, OR, XOR, SLL, SRL, SRA, SLT, SLTU, ADDI, ANDI, ORI, XORI, SLTI, SLTIU, SLLI, SRLI, SRAI, LB, LH, LW, LBU, LHU, SB, SH, SW, BEQ, BNE, BLT, BGE, BLTU, BGEU, JAL, JALR, LUI, AUIPC, FENCE, FENCE.I, ECALL, EBREAK |
 | RV32M | MUL, MULH, MULHSU, MULHU, DIV, DIVU, REM, REMU |
 | RV32A | LR.W, SC.W, AMOSWAP.W, AMOADD.W, AMOXOR.W, AMOAND.W, AMOOR.W, AMOMAX.W, AMOMIN.W, AMOMAXU.W, AMOMINU.W |
 | RV32F | FADD.S, FSUB.S, FMUL.S, FDIV.S, FSQRT.S, FMIN.S, FMAX.S, FEQ.S, FLT.S, FLE.S, FLW, FSW, FMV.W.X, FMV.X.W, FCVT.W.S, FCVT.WU.S, FCVT.S.W, FCVT.S.WU, FCLASS.S, FMADD.S, FMSUB.S, FNMADD.S, FNMSUB.S, FNEG.S, FABS.S |

docs/en/README.md

@@ -40,7 +40,7 @@ Requires Rust 1.75+. No other dependencies.
   - **RAM**: `k` cycles region: Data / Stack / R/W / Heap (sbrk pointer with `▶HB` marker)
   - **R/W**: still RAM view, but auto-follows the last memory access address from `LOAD` and `STORE`
   - **Dyn**: STORE → RAM at written address; LOAD/ALU → register bank
-- Instruction memory panel: type badge `[R][I][S][B][U][J]`, execution heat `×N`, branch outcome
+- Instruction memory panel: type badge `[R][I][S][B][U][J][A][F]`, execution heat `×N`, branch outcome
 - Instruction decoder: full field breakdown (opcode, funct3/7, rs1/rs2/rd, immediate, sign-extended)
 
 ### Cache Simulator (Tab 3)
@@ -63,7 +63,7 @@ Requires Rust 1.75+. No other dependencies.
 
 | Extension | Instructions |
 |-----------|-------------|
-| RV32I | ADD, SUB, AND, OR, XOR, SLL, SRL, SRA, SLT, SLTU, ADDI, ANDI, ORI, XORI, SLTI, SLTIU, SLLI, SRLI, SRAI, LB, LH, LW, LBU, LHU, SB, SH, SW, BEQ, BNE, BLT, BGE, BLTU, BGEU, JAL, JALR, LUI, AUIPC, ECALL, EBREAK |
+| RV32I | ADD, SUB, AND, OR, XOR, SLL, SRL, SRA, SLT, SLTU, ADDI, ANDI, ORI, XORI, SLTI, SLTIU, SLLI, SRLI, SRAI, LB, LH, LW, LBU, LHU, SB, SH, SW, BEQ, BNE, BLT, BGE, BLTU, BGEU, JAL, JALR, LUI, AUIPC, FENCE, FENCE.I, ECALL, EBREAK |
 | RV32M | MUL, MULH, MULHSU, MULHU, DIV, DIVU, REM, REMU |
 | RV32A | LR.W, SC.W, AMOSWAP.W, AMOADD.W, AMOXOR.W, AMOAND.W, AMOOR.W, AMOMAX.W, AMOMIN.W, AMOMAXU.W, AMOMINU.W |
 | RV32F | FADD.S, FSUB.S, FMUL.S, FDIV.S, FSQRT.S, FMIN.S, FMAX.S, FEQ.S, FLT.S, FLE.S, FLW, FSW, FMV.W.X, FMV.X.W, FCVT.W.S, FCVT.WU.S, FCVT.S.W, FCVT.S.WU, FCLASS.S, FMADD.S, FMSUB.S, FNMADD.S, FNMSUB.S, FNEG.S, FABS.S |

docs/en/RELEASE-pipeline-hart.md

@@ -60,7 +60,7 @@ The map distinguishes a forwarding-covered RAW (no stall, shown as `FWD`) from a
 
 ### Branch prediction
 
-Static prediction is configurable: **not-taken** (default) or **taken**. The pipeline attaches a prediction badge when the branch reaches `ID`. If the prediction is wrong, younger speculative instructions are flushed and the fetch redirects.
+Prediction is configurable: **not-taken** (default), **always-taken**, **BTFNT**, or **2-bit Dynamic**. The pipeline attaches a prediction badge when the branch reaches `ID`. If the prediction is wrong, younger speculative instructions are flushed and the fetch redirects.
 
 You can also choose where branches resolve: `ID` (1 bubble), `EX` (2 bubbles, default), or `MEM` (3 bubbles).
 
@@ -74,13 +74,22 @@ The pipeline and cache share one clock model. An IF or MEM access pays the full
 
 ### Configuration file
 
-Pipeline settings persist in a `.pcfg` file (`Ctrl+Shift+P` to save/load):
+Pipeline settings persist in a `.pcfg` file:
 
 ```
 # Raven Pipeline Config v1
 enabled=true
-forwarding=true
+bypass.ex_to_ex=true
+bypass.mem_to_ex=true
+bypass.wb_to_id=true
+bypass.store_to_load=false
 mode=SingleCycle
+fu.alu=1
+fu.mul=1
+fu.div=1
+fu.fpu=1
+fu.lsu=1
+fu.sys=1
 branch_resolve=Ex
 predict=NotTaken
 speed=Normal
@@ -181,7 +190,7 @@ The pipeline tab footer shows live metrics:
 Cycle  342   Instr  211   CPI  1.62   Stalls  89   Flushes  12
 ```
 
-Per-class instruction counts are visible in the Gantt color legend.
+The per-hazard breakdown is reported as **stall tags**. A single stalled cycle can contribute to more than one tag when multiple causes overlap.
 
 ---
 

docs/en/cli.md

@@ -147,11 +147,13 @@ printf "42\n" | raven run calculator.fas --nout
 
 When `--pipeline` is enabled, Raven still writes the normal cache statistics, but also includes a pipeline summary:
 
+- scope (`selected` for pipeline-only export, `aggregate` in cache/program summaries)
 - committed instructions
 - pipeline cycles
 - stall count
 - flush count
 - pipeline CPI
+- stall-tag breakdown (`RAW`, `load-use`, `branch`, `FU`, `mem`)
 
 ### Assertions
 
@@ -401,8 +403,17 @@ Controls pipeline-specific behavior used by the TUI pipeline tab and by `raven r
 ```ini
 # Raven Pipeline Config v1
 enabled=true
-forwarding=true
+bypass.ex_to_ex=true
+bypass.mem_to_ex=true
+bypass.wb_to_id=true
+bypass.store_to_load=false
 mode=SingleCycle
+fu.alu=1
+fu.mul=1
+fu.div=1
+fu.fpu=1
+fu.lsu=1
+fu.sys=1
 branch_resolve=Ex
 predict=NotTaken
 speed=Normal
@@ -411,10 +422,14 @@ speed=Normal
 Fields:
 
 - `enabled` — pipeline enabled in the TUI
-- `forwarding` — enable bypass/forwarding paths
-- `mode` — `SingleCycle` or `FunctionalUnits`
+- `bypass.ex_to_ex` — enable EX->EX bypass
+- `bypass.mem_to_ex` — enable MEM->EX bypass
+- `bypass.wb_to_id` — enable WB->ID bypass
+- `bypass.store_to_load` — enable store-to-load forwarding
+- `mode` — legacy field currently mapped in the UI as `Serialized` or `Parallel UFs`
+- `fu.alu` / `fu.mul` / `fu.div` / `fu.fpu` / `fu.lsu` / `fu.sys` — number of functional units of each type used by `Parallel UFs` mode
 - `branch_resolve` — `Id`, `Ex`, or `Mem`
-- `predict` — `NotTaken` or `Taken`
+- `predict` — `NotTaken`, `Taken`, `Btfnt`, or `TwoBit`
 - `speed` — TUI playback speed (`Slow`, `Normal`, `Fast`, `Instant`)
 
 Export / import from the TUI: **Pipeline tab → `Ctrl+E` / `Ctrl+L`**

docs/en/pipeline.md

@@ -44,7 +44,7 @@ Each visible pipeline step corresponds to exactly one CPU clock cycle. Cache lat
 - Computes effective addresses for loads/stores/atomics
 - Applies forwarding again for EX-stage consumers
 - Holds instructions for the configured `CPIConfig` latency in both pipeline modes
-- Uses the functional-unit panel only as an expanded visualization when that mode is enabled
+- Always renders the functional-unit panel in the TUI so execution opportunities stay visible
 
 ### MEM
 
@@ -161,9 +161,16 @@ Visual markers:
 
 ---
 
-## Functional-unit mode
+## Execution model
 
-In functional-unit mode, `EX` can remain busy for multiple cycles depending on class:
+The pipeline config currently exposes two execution models:
+
+- `Serialized`
+- `Parallel UFs`
+
+Both use the same functional-unit panel in the UI. The difference is semantic, not cosmetic.
+
+In the current implementation, execution still behaves like a single in-order EX path, and `EX` can remain busy for multiple cycles depending on class:
 
 - `ALU`
 - `MUL`
@@ -175,7 +182,7 @@ In functional-unit mode, `EX` can remain busy for multiple cycles depending on c
 - `SYSTEM`
 - `FP`
 
-While a long-latency instruction holds `EX`, the front of the pipe remains blocked and Raven keeps that state visible without letting unrelated IF latency progress incorrectly. In `FunctionalUnits`, the same latency is also broken down by FU in the expanded EX panel.
+While a long-latency instruction holds `EX`, the front of the pipe remains blocked and Raven keeps that state visible without letting unrelated IF latency progress incorrectly. The functional-unit panel breaks that latency down by FU so the user can see which resource is active and where parallelism could exist once the execution model allows it.
 
 ---
 

docs/pt-BR/README.md

@@ -34,7 +34,7 @@ Tudo vive em uma única TUI: escreva código, monte, execute passo a passo, insp
 ### Aba Run (Aba 2)
 **Memória de Instruções**
 - Headers de label e separadores de bloco renderizados inline
-- Badge de tipo por instrução (`[R]` `[I]` `[S]` `[B]` `[U]` `[J]`)
+- Badge de tipo por instrução (`[R]` `[I]` `[S]` `[B]` `[U]` `[J]` `[A]` `[F]`)
 - Heat coloring — sufixo `×N` de contagem de execuções colorido por frequência
 - Resultado de branch no PC atual: `→ 0xADDR (taken)` / `↛ (not taken)`
 - Breakpoints (`b`), saltar para endereço (`g`), painel de trace de execução (`t`)

docs/pt-BR/cli.md

@@ -145,13 +145,15 @@ printf "42\n" | raven run calculadora.fas --nout
 | `fstats` | Tabela legível por humanos (`.fstats`) |
 | `csv` | CSV compatível com planilhas |
 
-Quando `--pipeline` está ativo, o Raven inclui também um resumo do pipeline:
+Quando `--pipeline` está ativo, o Raven ainda exporta as estatísticas normais de cache, mas inclui também um resumo do pipeline:
 
+- escopo (`selected` na exportação específica do pipeline, `aggregate` nos resumos de cache/programa)
 - instruções committed
 - ciclos do pipeline
-- stalls
-- flushes
+- contagem de stalls
+- contagem de flushes
 - CPI do pipeline
+- breakdown por tags de stall (`RAW`, `load-use`, `branch`, `FU`, `mem`)
 
 ### Asserções
 
@@ -396,8 +398,17 @@ Controla o comportamento do pipeline usado pela aba de pipeline da TUI e pelo `r
 ```ini
 # Raven Pipeline Config v1
 enabled=true
-forwarding=true
+bypass.ex_to_ex=true
+bypass.mem_to_ex=true
+bypass.wb_to_id=true
+bypass.store_to_load=false
 mode=SingleCycle
+fu.alu=1
+fu.mul=1
+fu.div=1
+fu.fpu=1
+fu.lsu=1
+fu.sys=1
 branch_resolve=Ex
 predict=NotTaken
 speed=Normal
@@ -406,10 +417,14 @@ speed=Normal
 Campos:
 
 - `enabled` — pipeline habilitado na TUI
-- `forwarding` — habilitar caminhos de bypass/forwarding
-- `mode` — `SingleCycle` ou `FunctionalUnits`
+- `bypass.ex_to_ex` — habilitar bypass EX->EX
+- `bypass.mem_to_ex` — habilitar bypass MEM->EX
+- `bypass.wb_to_id` — habilitar bypass WB->ID
+- `bypass.store_to_load` — habilitar forwarding store-to-load
+- `mode` — campo legado hoje mapeado na UI como `Serialized` ou `Parallel UFs`
+- `fu.alu` / `fu.mul` / `fu.div` / `fu.fpu` / `fu.lsu` / `fu.sys` — quantidade de unidades funcionais de cada tipo usada no modo `Parallel UFs`
 - `branch_resolve` — `Id`, `Ex` ou `Mem`
-- `predict` — `NotTaken` ou `Taken`
+- `predict` — `NotTaken`, `Taken`, `Btfnt` ou `TwoBit`
 - `speed` — velocidade de reprodução na TUI (`Slow`, `Normal`, `Fast`, `Instant`)
 
 Exportar / importar pela TUI: **aba Pipeline → `Ctrl+E` / `Ctrl+L`**

rust-to-raven/.cargo/config.toml

@@ -5,4 +5,4 @@ target = "riscv32im-unknown-none-elf"
 build-std = ["core", "alloc"]
 
 [target.riscv32im-unknown-none-elf]
-rustflags = ["-C", "link-arg=-e", "-C", "link-arg=_start", "-C", "link-arg=--gc-sections"]
+rustflags = ["-C", "target-feature=+a,+f", "-C", "link-arg=-e", "-C", "link-arg=_start", "-C", "link-arg=--gc-sections"]

rust-to-raven/.vscode/settings.json

@@ -7,10 +7,10 @@
     "cargo",
     "+nightly",
     "check",
-    "-Zbuild-std=core,compiler_builtins",
+    "-Zbuild-std=core,alloc,compiler_builtins",
     "-Zbuild-std-features=compiler-builtins-mem",
     "--target",
-    "riscv32im-unknown-none-elf",
+    "riscv32imafc-unknown-none-elf",
     "--message-format=json"
   ]
 }

rust-to-raven/API.md

@@ -22,7 +22,7 @@ use raven_api::{exit, pause_sim};
 use raven_api::{spawn_hart, spawn_hart_fn};
 ```
 
-The crate is `no_std` and requires the `riscv32im` target.
+The crate is `no_std` and targets Raven's RV32IM baseline with `A` and `F` enabled explicitly at build time.
 Build with:
 
 ```bash