The following program can be compiled by Dynamatic (9204faf) but causes errors when verilating with Verilator (v5.040) because there are duplicate instance names in the addf module.
float myfunc(float var_2, float var_3) {
return var_2 + var_3;
}
#include <stdlib.h>
#include "dynamatic/Integration.h"
int main() {
float var_2 = (float) rand();
float var_3 = (float) rand();
CALL_KERNEL(myfunc,var_2,var_3);
return 0;
}
This is my synthesis script:
set-dynamatic-path ./dynamatic
set-src ../myfunc.c
set-clock-period 1
compile --sharing --buffer-algorithm fpl22
write-hdl --hdl verilog
exit
This is the command line output of Dynamatic:
[INFO] Compiled to LLVM IR
[INFO] Optimized LLVM IR
[INFO] Applied memory dependency analysis to LLVM IR
[INFO] Converted to std dialect
[INFO] Applied CF transformations
[INFO] Marked memory accesses with the corresponding interfaces in cf
[INFO] Compiled cf to handshake
[INFO] Applied transformations to handshake
[INFO] Set to apply credit-based sharing after buffer placement.
[INFO] Built kernel for profiling
[INFO] Ran kernel for profiling
[INFO] Profiled cf-level
[INFO] Set to use "gurobi" to solve buffer placement MILP!
[INFO] Running smart buffer placement with CP = 1.000 and algorithm = 'fpl22'
[INFO] Placed smart buffers
[INFO] Canonicalized handshake
[INFO] Created myfunc DOT
[INFO] Converted myfunc DOT to PNG
[INFO] Created myfunc_CFG DOT
[INFO] Converted myfunc_CFG DOT to PNG
[INFO] Lowered to HW
[INFO] Compilation succeeded
[INFO] Exported RTL (verilog)
[INFO] HDL generation succeeded
================================================================================
============== Dynamatic | Dynamic High-Level Synthesis Compiler ===============
======================== EPFL-LAP - v2.0.0 | March 2024 ========================
================================================================================
dynamatic> set-dynamatic-path /home/zdenis/.local/share/dynamatic
dynamatic> set-src ../myfunc.c
dynamatic> set-clock-period 1
dynamatic> compile --sharing --buffer-algorithm fpl22
dynamatic> write-hdl --hdl verilog
dynamatic> exit
Goodbye!
This is the command line output of Verilator:
%Error: ../rtl/../rtl/addf.v:65:20: Duplicate declaration of instance: 'InputIEEE_32bit'
65 | ieee2nfloat_rhs InputIEEE_32bit (
| ^~~~~~~~~~~~~~~
../rtl/../rtl/addf.v:60:20: ... Location of original declaration
60 | ieee2nfloat_lhs InputIEEE_32bit (
| ^~~~~~~~~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=5.040 for more assistance.
%Error: Exiting due to 1 error(s)
The following program can be compiled by Dynamatic (9204faf) but causes errors when verilating with Verilator (v5.040) because there are duplicate instance names in the addf module.
This is my synthesis script:
This is the command line output of Dynamatic:
This is the command line output of Verilator: