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computer.qsf
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120 lines (118 loc) · 6.14 KB
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition
# Date created = 20:44:35 July 07, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# computer_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22C8
set_global_assignment -name TOP_LEVEL_ENTITY computer
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:44:35 JULY 07, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Standard Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_location_assignment PIN_23 -to clk50m
set_location_assignment PIN_25 -to resetkey
set_location_assignment PIN_133 -to dig[1]
set_location_assignment PIN_135 -to dig[2]
set_location_assignment PIN_136 -to dig[3]
set_location_assignment PIN_137 -to dig[4]
set_location_assignment PIN_88 -to key1
set_location_assignment PIN_89 -to key2
set_location_assignment PIN_90 -to key3
set_location_assignment PIN_91 -to key4
set_location_assignment PIN_87 -to led1
set_location_assignment PIN_86 -to led2
set_location_assignment PIN_85 -to led3
set_location_assignment PIN_84 -to led4
set_location_assignment PIN_115 -to rx
set_location_assignment PIN_114 -to tx
set_location_assignment PIN_128 -to seg[0]
set_location_assignment PIN_121 -to seg[1]
set_location_assignment PIN_125 -to seg[2]
set_location_assignment PIN_129 -to seg[3]
set_location_assignment PIN_132 -to seg[4]
set_location_assignment PIN_126 -to seg[5]
set_location_assignment PIN_124 -to seg[6]
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH ptest -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME ptest -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME U0 -section_id ptest
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ptest -section_id ptest
set_global_assignment -name VHDL_FILE testtop.vhd
set_global_assignment -name VHDL_FILE my74151.vhd
set_global_assignment -name VHDL_FILE UART_TX.vhd
set_global_assignment -name VHDL_FILE UART_RX.vhd
set_global_assignment -name VHDL_FILE tri_gate.vhd
set_global_assignment -name VHDL_FILE subtract.vhd
set_global_assignment -name VHDL_FILE shiftr.vhd
set_global_assignment -name VHDL_FILE shiftl.vhd
set_global_assignment -name VHDL_FILE rs232tx.vhd
set_global_assignment -name VHDL_FILE rs232rx.vhd
set_global_assignment -name VHDL_FILE programmeCounter.vhd
set_global_assignment -name VHDL_FILE paralleladder8.vhd
set_global_assignment -name VHDL_FILE numtoled.vhd
set_global_assignment -name VHDL_FILE memory.vhd
set_global_assignment -name VHDL_FILE MAR.vhd
set_global_assignment -name VHDL_FILE led.vhd
set_global_assignment -name VHDL_FILE keyFitting.vhd
set_global_assignment -name VHDL_FILE hex_to_7_seg.vhd
set_global_assignment -name VHDL_FILE D_flip_flop.vhd
set_global_assignment -name VHDL_FILE dataRegister.vhd
set_global_assignment -name VHDL_FILE control.vhd
set_global_assignment -name VHDL_FILE computer.vhd
set_global_assignment -name VHDL_FILE clockSource.vhd
set_global_assignment -name VHDL_FILE clockPulse.vhd
set_global_assignment -name VHDL_FILE alu.vhd
set_global_assignment -name VHDL_FILE accumulator.vhd
set_global_assignment -name VHDL_FILE 8trigate.vhd
set_global_assignment -name VHDL_FILE 74283.vhd
set_instance_assignment -name VIRTUAL_PIN ON -to "res[0];res[1];res[2];res[3];res[4];res[5];res[6];res[7]"
set_global_assignment -name EDA_TEST_BENCH_FILE test/p_test.vhd -section_id ptest
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name VIRTUAL_PIN ON -to dbusout
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp2.stp
set_global_assignment -name SIGNALTAP_FILE output_files/stp2.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top