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Backport: std.math: Add FloatingPointControl.roundingMask value
e61f4bc0828c8007835836e3e1b19729876929c3
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+16
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libphobos/src/std/math.d

Lines changed: 16 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -4509,7 +4509,7 @@ real round(real x) @trusted nothrow @nogc
45094509
{
45104510
auto old = FloatingPointControl.getControlState();
45114511
FloatingPointControl.setControlState(
4512-
(old & ~FloatingPointControl.ROUNDING_MASK) | FloatingPointControl.roundToZero
4512+
(old & ~FloatingPointControl.roundingMask) | FloatingPointControl.roundToZero
45134513
);
45144514
x = rint((x >= 0) ? x + 0.5 : x - 0.5);
45154515
FloatingPointControl.setControlState(old);
@@ -5037,11 +5037,14 @@ struct FloatingPointControl
50375037
{
50385038
/** IEEE rounding modes.
50395039
* The default mode is roundToNearest.
5040+
*
5041+
* roundingMask = A mask of all rounding modes.
50405042
*/
50415043
roundToNearest,
50425044
roundDown, /// ditto
50435045
roundUp, /// ditto
5044-
roundToZero /// ditto
5046+
roundToZero, /// ditto
5047+
roundingMask, /// ditto
50455048
}
50465049
}
50475050
else version (CRuntime_Microsoft)
@@ -5052,7 +5055,9 @@ struct FloatingPointControl
50525055
roundToNearest = 0x0000,
50535056
roundDown = 0x0400,
50545057
roundUp = 0x0800,
5055-
roundToZero = 0x0C00
5058+
roundToZero = 0x0C00,
5059+
roundingMask = roundToNearest | roundDown
5060+
| roundUp | roundToZero,
50565061
}
50575062
}
50585063
else
@@ -5063,20 +5068,22 @@ struct FloatingPointControl
50635068
roundDown = core.stdc.fenv.FE_DOWNWARD,
50645069
roundUp = core.stdc.fenv.FE_UPWARD,
50655070
roundToZero = core.stdc.fenv.FE_TOWARDZERO,
5071+
roundingMask = roundToNearest | roundDown
5072+
| roundUp | roundToZero,
50665073
}
50675074
}
50685075

50695076
//// Change the floating-point hardware rounding mode
50705077
@property void rounding(RoundingMode newMode) @nogc
50715078
{
50725079
initialize();
5073-
setControlState((getControlState() & (-1 - ROUNDING_MASK)) | (newMode & ROUNDING_MASK));
5080+
setControlState(cast(ushort)((getControlState() & (-1 - roundingMask)) | (newMode & roundingMask)));
50745081
}
50755082

50765083
/// Returns: the currently active rounding mode
50775084
@property static RoundingMode rounding() @nogc
50785085
{
5079-
return cast(RoundingMode)(getControlState() & ROUNDING_MASK);
5086+
return cast(RoundingMode)(getControlState() & roundingMask);
50805087
}
50815088

50825089
version(StdDdoc)
@@ -5147,26 +5154,6 @@ struct FloatingPointControl
51475154
}
51485155
}
51495156

5150-
private:
5151-
version(ARM)
5152-
{
5153-
enum uint ROUNDING_MASK = 0xC00000;
5154-
}
5155-
else version(PPC_Any)
5156-
{
5157-
enum uint ROUNDING_MASK = 0x0003;
5158-
}
5159-
else version(X86)
5160-
{
5161-
enum ushort ROUNDING_MASK = 0xC00;
5162-
}
5163-
else version(X86_64)
5164-
{
5165-
enum ushort ROUNDING_MASK = 0xC00;
5166-
}
5167-
else
5168-
static assert(false, "Architecture not supported");
5169-
51705157
public:
51715158
/// Returns: true if the current FPU supports exception trapping
51725159
@property static bool hasExceptionTraps() @safe nothrow @nogc
@@ -5343,8 +5330,8 @@ private:
53435330

53445331
/* In the FPU control register, rounding mode is in bits 10 and
53455332
11. In MXCSR it's in bits 13 and 14. */
5346-
enum ROUNDING_MASK_SSE = ROUNDING_MASK << 3;
5347-
immutable newRoundingModeSSE = (newState & ROUNDING_MASK) << 3;
5333+
enum ROUNDING_MASK_SSE = roundingMask << 3;
5334+
immutable newRoundingModeSSE = (newState & roundingMask) << 3;
53485335
mxcsr &= ~ROUNDING_MASK_SSE; // delete old rounding mode
53495336
mxcsr |= newRoundingModeSSE; // write new rounding mode
53505337

@@ -5378,8 +5365,8 @@ private:
53785365

53795366
/* In the FPU control register, rounding mode is in bits 10 and
53805367
11. In MXCSR it's in bits 13 and 14. */
5381-
mxcsr &= ~(ROUNDING_MASK << 3); // delete old rounding mode
5382-
mxcsr |= (newState & ROUNDING_MASK) << 3; // write new rounding mode
5368+
mxcsr &= ~(roundingMask << 3); // delete old rounding mode
5369+
mxcsr |= (newState & roundingMask) << 3; // write new rounding mode
53835370

53845371
/* In the FPU control register, masks are bits 0 through 5.
53855372
In MXCSR they're 7 through 12. */

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