When the FPGA receives a command that will invalidate the data in the FPGA->uC FIFO (such as seek), it doesn't assert the WAIT line until the command gets to the execution step of the pipeline.
Use one of the bits of the command field to represent instructions that will invalidate the FIFOs and immediately assert WAIT on seeing it.
When the FPGA receives a command that will invalidate the data in the FPGA->uC FIFO (such as seek), it doesn't assert the WAIT line until the command gets to the execution step of the pipeline.
Use one of the bits of the command field to represent instructions that will invalidate the FIFOs and immediately assert WAIT on seeing it.