diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.c b/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.c
index 37fc0c1fb4..d513eba592 100644
--- a/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.c
+++ b/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.c
@@ -266,6 +266,7 @@ void gpt_lld_start(GPTDriver *gptp) {
 #    if SN32_GPT_USE_CT16B0
         if (&GPTD1 == gptp) {
             sys1EnableCT16B0();
+            sys1ResetCT16B0();
             CT16B0_ResetTimer();
 #        if !defined(SN32_CT16B0_SUPPRESS_ISR)
             nvicEnableVector(SN32_CT16B0_NUMBER, SN32_GPT_CT16B0_IRQ_PRIORITY);
@@ -276,6 +277,7 @@ void gpt_lld_start(GPTDriver *gptp) {
 #    if SN32_GPT_USE_CT16B1
         if (&GPTD2 == gptp) {
             sys1EnableCT16B1();
+            sys1ResetCT16B1();
             CT16B1_ResetTimer();
 #        if !defined(SN32_CT16B1_SUPPRESS_ISR)
             nvicEnableVector(SN32_CT16B1_NUMBER, SN32_GPT_CT16B1_IRQ_PRIORITY);
@@ -286,6 +288,7 @@ void gpt_lld_start(GPTDriver *gptp) {
 #    if SN32_GPT_USE_CT16B2
         if (&GPTD3 == gptp) {
             sys1EnableCT16B2();
+            sys1ResetCT16B2();
             CT16B2_ResetTimer();
 #        if !defined(SN32_CT16B2_SUPPRESS_ISR)
             nvicEnableVector(SN32_CT16B2_NUMBER, SN32_GPT_CT16B2_IRQ_PRIORITY);
@@ -296,6 +299,7 @@ void gpt_lld_start(GPTDriver *gptp) {
 #    if SN32_GPT_USE_CT16B3
         if (&GPTD4 == gptp) {
             sys1EnableCT16B3();
+            sys1ResetCT16B3();
             CT16B3_ResetTimer();
 #        if !defined(SN32_CT16B3_SUPPRESS_ISR)
             nvicEnableVector(SN32_CT16B3_NUMBER, SN32_GPT_CT16B3_IRQ_PRIORITY);
@@ -306,6 +310,7 @@ void gpt_lld_start(GPTDriver *gptp) {
 #    if SN32_GPT_USE_CT16B4
         if (&GPTD5 == gptp) {
             sys1EnableCT16B4();
+            sys1ResetCT16B4();
             CT16B4_ResetTimer();
 #        if !defined(SN32_CT16B4_SUPPRESS_ISR)
             nvicEnableVector(SN32_CT16B4_NUMBER, SN32_GPT_CT16B4_IRQ_PRIORITY);
@@ -316,7 +321,8 @@ void gpt_lld_start(GPTDriver *gptp) {
 #    if SN32_GPT_USE_CT16B5
         if (&GPTD6 == gptp) {
             sys1EnableCT16B5();
-            CT16B6_ResetTimer();
+            sys1ResetCT16B5();
+            CT16B5_ResetTimer();
 #        if !defined(SN32_CT16B5_SUPPRESS_ISR)
             nvicEnableVector(SN32_CT16B5_NUMBER, SN32_GPT_CT16B5_IRQ_PRIORITY);
 #        endif
@@ -328,32 +334,38 @@ void gpt_lld_start(GPTDriver *gptp) {
         SN32_CT_GPT_SET(gptp, config.TMRCTRL, CT16_CEN_DIS); /* Timer disabled.*/
 #    if SN32_GPT_USE_CT16B0
         if (&GPTD1 == gptp) {
+            sys1ResetCT16B0();
             CT16B0_ResetTimer(); /* Counter reset to zero.*/
         }
 #    endif
 #    if SN32_GPT_USE_CT16B1
         if (&GPTD2 == gptp) {
+            sys1ResetCT16B1();
             CT16B1_ResetTimer(); /* Counter reset to zero.*/
         }
 #    endif
 #    if SN32_GPT_USE_CT16B2
         if (&GPTD3 == gptp) {
+            sys1ResetCT16B2();
             CT16B2_ResetTimer(); /* Counter reset to zero.*/
         }
 #    endif
 #    if SN32_GPT_USE_CT16B3
         if (&GPTD4 == gptp) {
+            sys1ResetCT16B3();
             CT16B3_ResetTimer(); /* Counter reset to zero.*/
         }
 #    endif
 #    if SN32_GPT_USE_CT16B4
         if (&GPTD5 == gptp) {
+            sys1ResetCT16B4();
             CT16B4_ResetTimer(); /* Counter reset to zero.*/
         }
 #    endif
 #    if SN32_GPT_USE_CT16B5
         if (&GPTD6 == gptp) {
-            CT16B4_ResetTimer(); /* Counter reset to zero.*/
+            sys1ResetCT16B5();
+            CT16B5_ResetTimer(); /* Counter reset to zero.*/
         }
 #    endif
     }
@@ -423,7 +435,7 @@ void gpt_lld_stop(GPTDriver *gptp) {
         }
 #    endif
 #    if SN32_GPT_USE_CT16B5
-        if (&GPTD5 == gptp) {
+        if (&GPTD6 == gptp) {
 #        if !defined(SN32_CT16B5_SUPPRESS_ISR)
             nvicDisableVector(SN32_CT16B5_NUMBER);
 #        endif
diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.h b/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.h
index 2e6104d0b6..643eece9ed 100644
--- a/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.h
+++ b/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.h
@@ -638,8 +638,7 @@ struct GPTDriver {
  *
  * @notapi
  */
-#define gpt_lld_get_counter(gptp) (gptcnt_t)SN32_CT_GPT_GET((gptp), config.TC)
-
+#define gpt_lld_get_counter(gptp) (gptcnt_t)(SN32_CT_GPT_GET((gptp), config.TC) & SN32_CT16_TC_LIMIT)
 /*===========================================================================*/
 /* External declarations.                                                    */
 /*===========================================================================*/
diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.c b/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.c
index 12e366e9c3..c7771f95d6 100644
--- a/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.c
+++ b/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.c
@@ -112,6 +112,7 @@ void pwm_lld_start(PWMDriver *pwmp) {
 #    if SN32_PWM_USE_CT16B1
         if (&PWMD1 == pwmp) {
             sys1EnableCT16B1();
+            sys1ResetCT16B1();
             CT16B1_ResetTimer();
 #        if !defined(SN32_CT16B1_SUPPRESS_ISR)
             nvicEnableVector(SN32_CT16B1_NUMBER, SN32_PWM_CT16B1_IRQ_PRIORITY);
diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.c b/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.c
index 242c6d7b77..991bb8e619 100644
--- a/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.c
+++ b/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.c
@@ -147,19 +147,19 @@ void _pal_lld_init(const PALConfig *config) {
 
 #if (PAL_USE_WAIT == TRUE) || (PAL_USE_CALLBACKS == TRUE)
 #if SN32_HAS_GPIOA
-  sys1EnableP0();
+  sys1EnableGPIO0();
   nvicEnableVector(SN32_GPIOA_NUMBER, SN32_GPIOA_IRQ_PRIORITY);
 #endif
 #if SN32_HAS_GPIOB
-  sys1EnableP1();
+  sys1EnableGPIO1();
   nvicEnableVector(SN32_GPIOB_NUMBER, SN32_GPIOB_IRQ_PRIORITY);
 #endif
 #if SN32_HAS_GPIOC
-  sys1EnableP2();
+  sys1EnableGPIO2();
   nvicEnableVector(SN32_GPIOC_NUMBER, SN32_GPIOC_IRQ_PRIORITY);
 #endif
 #if SN32_HAS_GPIOD
-  sys1EnableP3();
+  sys1EnableGPIO3();
   nvicEnableVector(SN32_GPIOD_NUMBER, SN32_GPIOD_IRQ_PRIORITY);
 #endif
 
diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.h b/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.h
index b70a4c276c..2181ccda60 100644
--- a/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.h
+++ b/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.h
@@ -340,7 +340,7 @@ typedef uint32_t iopadid_t;
  *
  * @notapi
  */
-#define pal_lld_clearport(port, bits) ((port)->BCLR = ~(uint32_t)(bits))
+#define pal_lld_clearport(port, bits) ((port)->BCLR = (uint32_t)(bits))
 
 /**
  * @brief   Writes a group of bits.
diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.c b/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.c
index b062477b91..5277a2e94e 100644
--- a/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.c
+++ b/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.c
@@ -44,6 +44,7 @@
 #endif
 
 #define ST_ENABLE_CLOCK()                   sys1EnableCT16B0()
+#define ST_RESET_CLOCK()                    sys1ResetCT16B0()
 #define ST_INIT_CLOCK()                     CT16B0_ResetTimer()
 
 #elif SN32_ST_USE_TIMER == SN32_TIM_CT16B1
@@ -53,6 +54,7 @@
 #endif
 
 #define ST_ENABLE_CLOCK()                   sys1EnableCT16B1()
+#define ST_RESET_CLOCK()                    sys1ResetCT16B1()
 #define ST_INIT_CLOCK()                     CT16B1_ResetTimer()
 
 #else
@@ -128,6 +130,7 @@ void st_lld_init(void) {
 
   /* Enabling timer clock.*/
   ST_ENABLE_CLOCK();
+  ST_RESET_CLOCK();
   ST_INIT_CLOCK();
   /* Initializing the counter in free running mode.*/
   SN32_ST_TIM->config.PRE    = (SYSTICK_CK / OSAL_ST_FREQUENCY) - 1;
diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.h b/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.h
index 3c003eb793..796b7d335b 100644
--- a/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.h
+++ b/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.h
@@ -136,6 +136,16 @@ static inline systime_t st_lld_get_counter(void) {
   return (systime_t)(SN32_ST_TIM->config.TC & UINT16_MAX);
 }
 
+/**
+ * @brief   Stops the alarm interrupt.
+ *
+ * @notapi
+ */
+static inline void st_lld_stop_alarm(void) {
+  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk;
+  SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
+}
+
 /**
  * @brief   Starts the alarm.
  * @note    Makes sure that no spurious alarms are triggered after
@@ -147,28 +157,42 @@ static inline systime_t st_lld_get_counter(void) {
  */
 static inline void st_lld_start_alarm(systime_t abstime) {
 
-  /* The requested delay in OSAL_ST_FREQUENCY ticks, decreased by 1 to bring it
-   * into the 0...0xFFFF range instead of 1...0x10000. */
-  uint32_t delay = ((uint32_t)abstime - SN32_ST_TIM->config.TC - 1U) & SN32_CT16_TC_LIMIT;
+  uint32_t now = SN32_ST_TIM->config.TC;
+  uint32_t delay = ((uint32_t)abstime - now) & SN32_CT16_TC_LIMIT;
+  uint32_t prescale = (SN32_ST_TIM->config.PRE & UINT8_MAX) + 1U;
+
+  /* Minimum safe delay */
+  uint32_t min_delay_ticks = 4U;
+
+  /* Handle wrap-around */
+  if (delay > (SN32_CT16_TC_LIMIT >> 1)) {
+    delay = min_delay_ticks;
+  }
 
-  /* The conversion factor between the SN32_ST_TIM and SysTick clock
-   * frequencies (SN32_HCLK / OSAL_ST_FREQUENCY).
-   * TODO: Actually use (SN32_HCLK / OSAL_ST_FREQUENCY) instead of reading the
-   * value from a hardware register (this requires making SN32_HCLK a compile
-   * time constant). */
-  uint32_t prescale = (SN32_ST_TIM->config.PRE & UINT8_MAX) + 1;
+  if (delay < min_delay_ticks) {
+    delay = min_delay_ticks;
+  }
 
   /* The requested delay in the SysTick clock ticks.  The maximum possible
    * value with prescale=256 is 0xFFFFFF, which just fits into the 24-bit
    * SysTick timer registers. */
-  uint32_t systick_delay = delay * prescale + (prescale - 1);
+  uint32_t systick_delay = delay * prescale;
+
+  if (systick_delay > 0xFFFFFFU) {
+    systick_delay = 0xFFFFFFU;
+  }
 
-  if (systick_delay > 0xFFFFFF) {
-    systick_delay = 0xFFFFFF;
+  if (systick_delay < prescale) {
+    systick_delay = prescale;
   }
+
+  st_lld_stop_alarm();
+
   /* Start SysTick to generate an interrupt after systick_delay. */
   SysTick->LOAD = systick_delay;
-  SysTick->VAL = 0;
+  SysTick->VAL = 0U;
+
+  SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
   SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
                   SysTick_CTRL_ENABLE_Msk |
                   SysTick_CTRL_TICKINT_Msk;
@@ -182,16 +206,6 @@ static inline void st_lld_start_alarm(systime_t abstime) {
 #endif
 }
 
-/**
- * @brief   Stops the alarm interrupt.
- *
- * @notapi
- */
-static inline void st_lld_stop_alarm(void) {
-  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk;
-  SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
-}
-
 /**
  * @brief   Sets the alarm time.
  *
@@ -200,7 +214,6 @@ static inline void st_lld_stop_alarm(void) {
  * @notapi
  */
 static inline void st_lld_set_alarm(systime_t abstime) {
-  st_lld_stop_alarm();
   st_lld_start_alarm(abstime);
 }
 
diff --git a/os/hal/ports/SN32/SN32F240/sn32_sys1.h b/os/hal/ports/SN32/SN32F240/sn32_sys1.h
index 5bd78ea72e..095fe1912d 100644
--- a/os/hal/ports/SN32/SN32F240/sn32_sys1.h
+++ b/os/hal/ports/SN32/SN32F240/sn32_sys1.h
@@ -135,6 +135,10 @@
  * @api
  */
 #define sys1EnableGPIO() sys1EnableAHB(0x1<<0)
+#define sys1EnableGPIO0() sys1EnableGPIO()
+#define sys1EnableGPIO1() sys1EnableGPIO()
+#define sys1EnableGPIO2() sys1EnableGPIO()
+#define sys1EnableGPIO3() sys1EnableGPIO()
 
 /**
  * @brief   Disables the GPIO peripheral clock.
@@ -144,32 +148,32 @@
 #define sys1DisableGPIO() sys1DisableAHB(0x1<<0)
 
 /**
- * @brief   Resets the GPIOP0 peripheral.
+ * @brief   Resets the GPIO0 peripheral.
  *
  * @api
  */
-#define sys1ResetGPIOP0() sys1Reset(0x1<<0)
+#define sys1ResetGPIO0() sys1Reset(0x1<<0)
 
 /**
- * @brief   Resets the GPIOP1 peripheral.
+ * @brief   Resets the GPIO1 peripheral.
  *
  * @api
  */
-#define sys1ResetGPIOP1() sys1Reset(0x1<<1)
+#define sys1ResetGPIO1() sys1Reset(0x1<<1)
 
 /**
- * @brief   Resets the GPIOP2 peripheral.
+ * @brief   Resets the GPIO2 peripheral.
  *
  * @api
  */
-#define sys1ResetGPIOP2() sys1Reset(0x1<<2)
+#define sys1ResetGPIO2() sys1Reset(0x1<<2)
 
 /**
- * @brief   Resets the GPIOP3 peripheral.
+ * @brief   Resets the GPIO3 peripheral.
  *
  * @api
  */
-#define sys1ResetGPIOP3() sys1Reset(0x1<<3)
+#define sys1ResetGPIO3() sys1Reset(0x1<<3)
 
 /**
  * @name    USB peripherals specific SYS1 operations
diff --git a/os/hal/ports/SN32/SN32F240B/sn32_sys1.h b/os/hal/ports/SN32/SN32F240B/sn32_sys1.h
index f7a82f64f3..d4612385ff 100644
--- a/os/hal/ports/SN32/SN32F240B/sn32_sys1.h
+++ b/os/hal/ports/SN32/SN32F240B/sn32_sys1.h
@@ -88,80 +88,91 @@
 }
 
 /** @} */
+/**
+ * @name    Dummy peripherals specific SYS1 operations
+ * @{
+ */
+/**
+ * @brief   Resets the CT16 peripherals.
+ *
+ * @api
+ */
+#define sys1ResetCT16B0()
+#define sys1ResetCT16B1()
 
 /**
- * @name    P0 peripherals specific SYS1 operations
+ * @name    GPIO0 peripherals specific SYS1 operations
  * @{
  */
 /**
- * @brief   Enables the P0 peripheral clock.
+ * @brief   Enables the GPIO0 peripheral clock.
  *
 
  *
  * @api
  */
-#define sys1EnableP0() sys1EnableAHB(0x1<<0)
+#define sys1EnableGPIO0() sys1EnableAHB(0x1<<0)
 
 /**
- * @brief   Disables the P0 peripheral clock.
+ * @brief   Disables the GPIO0 peripheral clock.
  *
  * @api
  */
-#define sys1DisableP0() sys1DisableAHB(0x1<<0)
+#define sys1DisableGPIO0() sys1DisableAHB(0x1<<0)
 
 /**
- * @name    P1 peripherals specific SYS1 operations
+ * @name    GPIO1 peripherals specific SYS1 operations
  * @{
  */
 /**
- * @brief   Enables the P1 peripheral clock.
+ * @brief   Enables the GPIO1 peripheral clock.
  *
  * @api
  */
-#define sys1EnableP1() sys1EnableAHB(0x1<<1)
+#define sys1EnableGPIO1() sys1EnableAHB(0x1<<1)
 
 /**
- * @brief   Disables the P1 peripheral clock.
+ * @brief   Disables the GPIO1 peripheral clock.
  *
  * @api
  */
-#define sys1DisableP1() sys1DisableAHB(0x1<<1)
+#define sys1DisableGPIO1() sys1DisableAHB(0x1<<1)
 
 /**
- * @name    P2 peripherals specific SYS1 operations
+ * @name    GPIO2 peripherals specific SYS1 operations
  * @{
  */
 /**
- * @brief   Enables the P2 peripheral clock.
+ * @brief   Enables the GPIO2 peripheral clock.
  *
  * @api
  */
-#define sys1EnableP2() sys1EnableAHB(0x1<<2)
+#define sys1EnableGPIO2() sys1EnableAHB(0x1<<2)
 
 /**
- * @brief   Disables the P2 peripheral clock.
+ * @brief   Disables the GPIO2 peripheral clock.
  *
  * @api
  */
-#define sys1DisableP2() sys1DisableAHB(0x1<<2)
+#define sys1DisableGPIO2() sys1DisableAHB(0x1<<2)
 
 /**
- * @name    P3 peripherals specific SYS1 operations
+ * @name    GPIO3 peripherals specific SYS1 operations
  * @{
  */
 /**
- * @brief   Enables the P3 peripheral clock.
+ * @brief   Enables the GPIO3 peripheral clock.
  *
  * @api
  */
-#define sys1EnableP3() sys1EnableAHB(0x1<<3)
+#define sys1EnableGPIO3() sys1EnableAHB(0x1<<3)
 
 /**
- * @brief   Disables the P3 peripheral clock.
+ * @brief   Disables the GPIO3 peripheral clock.
  *
  * @api
  */
-#define sys1DisableP3() sys1DisableAHB(0x1<<3)
+#define sys1DisableGPIO3() sys1DisableAHB(0x1<<3)
 
 /**
  * @name    USB peripherals specific SYS1 operations
diff --git a/os/hal/ports/SN32/SN32F240C/sn32_sys1.h b/os/hal/ports/SN32/SN32F240C/sn32_sys1.h
index 4dc5e56220..4e5a324fd1 100644
--- a/os/hal/ports/SN32/SN32F240C/sn32_sys1.h
+++ b/os/hal/ports/SN32/SN32F240C/sn32_sys1.h
@@ -99,9 +99,22 @@
   (void)SN_SYS1->APBCP1;                                                  \
 }
 
+/**
+ * @brief   Resets one or more peripheral.
+ *
+ * @param[in] mask      Reset peripherals mask
+ *
+ * @api
+ */
+#define sys1Reset(mask) {                                                   \
+  SN_SYS1->PRST |= (mask);                                                  \
+  SN_SYS1->PRST &= ~(mask);                                                 \
+  (void)SN_SYS1->PRST;                                                      \
+}
+
 /** @} */
 /**
- * @name    Dummy GPIO peripherals specific SYS1 operations
+ * @name    Dummy peripherals specific SYS1 operations
  * @{
  */
 /**
@@ -109,19 +122,51 @@
  *
  * @api
  */
-#define sys1EnableP0()
-#define sys1EnableP1()
-#define sys1EnableP2()
-#define sys1EnableP3()
+#define sys1EnableGPIO0()
+#define sys1EnableGPIO1()
+#define sys1EnableGPIO2()
+#define sys1EnableGPIO3()
 /**
  * @brief   Disables the GPIO peripherals clock.
  *
  * @api
  */
-#define sys1DisableP0()
-#define sys1DisableP1()
-#define sys1DisableP2()
-#define sys1DisableP3()
+#define sys1DisableGPIO0()
+#define sys1DisableGPIO1()
+#define sys1DisableGPIO2()
+#define sys1DisableGPIO3()
+
+/**
+ * @name    GPIO peripherals specific SYS1 operations
+ * @{
+ */
+/**
+ * @brief   Resets the GPIO0 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetGPIO0() sys1Reset(0x1<<0)
+
+/**
+ * @brief   Resets the GPIO1 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetGPIO1() sys1Reset(0x1<<1)
+
+/**
+ * @brief   Resets the GPIO2 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetGPIO2() sys1Reset(0x1<<2)
+
+/**
+ * @brief   Resets the GPIO3 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetGPIO3() sys1Reset(0x1<<3)
 
 /**
  * @name    USB peripherals specific SYS1 operations
@@ -141,6 +186,13 @@
  */
 #define sys1DisableUSB() sys1DisableAHB(0x1<<4)
 
+/**
+ * @brief   Resets the USB peripheral.
+ *
+ * @api
+ */
+#define sys1ResetUSB() sys1Reset(0x1<<27)
+
 /**
  * @name    CT16B0 peripherals specific SYS1 operations
  * @{
@@ -159,6 +211,13 @@
  */
 #define sys1DisableCT16B0() sys1DisableAHB(0x1<<6)
 
+/**
+ * @brief   Resets the CT16B0 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetCT16B0() sys1Reset(0x1<<6)
+
 /**
  * @name    CT16B1 peripherals specific SYS1 operations
  * @{
@@ -177,6 +236,13 @@
  */
 #define sys1DisableCT16B1() sys1DisableAHB(0x1<<7)
 
+/**
+ * @brief   Resets the CT16B1 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetCT16B1() sys1Reset(0x1<<7)
+
 /**
  * @name    ADC peripherals specific SYS1 operations
  * @{
@@ -195,6 +261,13 @@
  */
 #define sys1DisableADC() sys1DisableAHB(0x1<<11)
 
+/**
+ * @brief   Resets the ADC peripheral.
+ *
+ * @api
+ */
+#define sys1ResetADC() sys1Reset(0x1<<11)
+
 /**
  * @name    SPI0 peripherals specific SYS1 operations
  * @{
@@ -213,6 +286,13 @@
  */
 #define sys1DisableSPI0() sys1DisableAHB(0x1<<12)
 
+/**
+ * @brief   Resets the SPI0 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetSPI0() sys1Reset(0x1<<12)
+
 /**
  * @name    SPI1 peripherals specific SYS1 operations
  * @{
@@ -230,6 +310,14 @@
  * @api
  */
 #define sys1DisableSPI1() sys1DisableAHB(0x1<<13)
+
+/**
+ * @brief   Resets the SPI1 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetSPI1() sys1Reset(0x1<<13)
+
 /**
  * @name    UART0 peripherals specific SYS1 operations
  * @{
@@ -248,6 +336,13 @@
  */
 #define sys1DisableUART0() sys1DisableAHB(0x1<<16)
 
+/**
+ * @brief   Resets the UART0 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetUART0() sys1Reset(0x1<<16)
+
 /**
  * @name    UART1 peripherals specific SYS1 operations
  * @{
@@ -266,6 +361,13 @@
  */
 #define sys1DisableUART1() sys1DisableAHB(0x1<<17)
 
+/**
+ * @brief   Resets the UART1 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetUART1() sys1Reset(0x1<<17)
+
 /**
  * @name    UART2 peripherals specific SYS1 operations
  * @{
@@ -284,6 +386,13 @@
  */
 #define sys1DisableUART2() sys1DisableAHB(0x1<<18)
 
+/**
+ * @brief   Resets the UART2 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetUART2() sys1Reset(0x1<<18)
+
 /**
  * @name    I2C0 peripherals specific SYS1 operations
  * @{
@@ -302,6 +411,13 @@
  */
 #define sys1DisableI2C0() sys1DisableAHB(0x1<<21)
 
+/**
+ * @brief   Resets the I2C0 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetI2C0() sys1Reset(0x1<<21)
+
 /**
  * @name    I2C1 peripherals specific SYS1 operations
  * @{
@@ -320,6 +436,13 @@
  */
 #define sys1DisableI2C1() sys1DisableAHB(0x1<<20)
 
+/**
+ * @brief   Resets the I2C1 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetI2C1() sys1Reset(0x1<<20)
+
 /**
  * @name    WDT peripherals specific SYS1 operations
  * @{
@@ -338,6 +461,13 @@
  */
 #define sys1DisableWDT() sys1DisableAHB(0x1<<24)
 
+/**
+ * @brief   Resets the WDT peripheral.
+ *
+ * @api
+ */
+#define sys1ResetWDT() sys1Reset(0x1<<24)
+
 /**
  * @name    CRC peripherals specific SYS1 operations
  * @{
@@ -356,6 +486,13 @@
  */
 #define sys1DisableCRC() sys1DisableAHB(0x1<<27)
 
+/**
+ * @brief   Resets the CRC peripheral.
+ *
+ * @api
+ */
+#define sys1ResetCRC() sys1Reset(0x1<<26)
+
 /**
  * @name    CLKOUT peripherals specific SYS1 operations
  * @{
diff --git a/os/hal/ports/SN32/SN32F260/sn32_sys1.h b/os/hal/ports/SN32/SN32F260/sn32_sys1.h
index 7e7559e152..5c9d06b67e 100644
--- a/os/hal/ports/SN32/SN32F260/sn32_sys1.h
+++ b/os/hal/ports/SN32/SN32F260/sn32_sys1.h
@@ -88,80 +88,91 @@
 }
 
 /** @} */
+/**
+ * @name    Dummy peripherals specific SYS1 operations
+ * @{
+ */
+/**
+ * @brief   Resets the CT16 peripherals.
+ *
+ * @api
+ */
+#define sys1ResetCT16B0()
+#define sys1ResetCT16B1()
 
 /**
- * @name    P0 peripherals specific SYS1 operations
+ * @name    GPIO0 peripherals specific SYS1 operations
  * @{
  */
 /**
- * @brief   Enables the P0 peripheral clock.
+ * @brief   Enables the GPIO0 peripheral clock.
  *
 
  *
  * @api
  */
-#define sys1EnableP0() sys1EnableAHB(0x1<<0)
+#define sys1EnableGPIO0() sys1EnableAHB(0x1<<0)
 
 /**
- * @brief   Disables the P0 peripheral clock.
+ * @brief   Disables the GPIO0 peripheral clock.
  *
  * @api
  */
-#define sys1DisableP0() sys1DisableAHB(0x1<<0)
+#define sys1DisableGPIO0() sys1DisableAHB(0x1<<0)
 
 /**
- * @name    P1 peripherals specific SYS1 operations
+ * @name    GPIO1 peripherals specific SYS1 operations
  * @{
  */
 /**
- * @brief   Enables the P1 peripheral clock.
+ * @brief   Enables the GPIO1 peripheral clock.
  *
  * @api
  */
-#define sys1EnableP1() sys1EnableAHB(0x1<<1)
+#define sys1EnableGPIO1() sys1EnableAHB(0x1<<1)
 
 /**
- * @brief   Disables the P1 peripheral clock.
+ * @brief   Disables the GPIO1 peripheral clock.
  *
  * @api
  */
-#define sys1DisableP1() sys1DisableAHB(0x1<<1)
+#define sys1DisableGPIO1() sys1DisableAHB(0x1<<1)
 
 /**
- * @name    P2 peripherals specific SYS1 operations
+ * @name    GPIO2 peripherals specific SYS1 operations
  * @{
  */
 /**
- * @brief   Enables the P2 peripheral clock.
+ * @brief   Enables the GPIO2 peripheral clock.
  *
  * @api
  */
-#define sys1EnableP2() sys1EnableAHB(0x1<<2)
+#define sys1EnableGPIO2() sys1EnableAHB(0x1<<2)
 
 /**
- * @brief   Disables the P2 peripheral clock.
+ * @brief   Disables the GPIO2 peripheral clock.
  *
  * @api
  */
-#define sys1DisableP2() sys1DisableAHB(0x1<<2)
+#define sys1DisableGPIO2() sys1DisableAHB(0x1<<2)
 
 /**
- * @name    P3 peripherals specific SYS1 operations
+ * @name    GPIO3 peripherals specific SYS1 operations
  * @{
  */
 /**
- * @brief   Enables the P3 peripheral clock.
+ * @brief   Enables the GPIO3 peripheral clock.
  *
  * @api
  */
-#define sys1EnableP3() sys1EnableAHB(0x1<<3)
+#define sys1EnableGPIO3() sys1EnableAHB(0x1<<3)
 
 /**
- * @brief   Disables the P3 peripheral clock.
+ * @brief   Disables the GPIO3 peripheral clock.
  *
  * @api
  */
-#define sys1DisableP3() sys1DisableAHB(0x1<<3)
+#define sys1DisableGPIO3() sys1DisableAHB(0x1<<3)
 
 /**
  * @name    USB peripherals specific SYS1 operations
diff --git a/os/hal/ports/SN32/SN32F290/sn32_sys1.h b/os/hal/ports/SN32/SN32F290/sn32_sys1.h
index 239fbc0fee..cf43806fc5 100644
--- a/os/hal/ports/SN32/SN32F290/sn32_sys1.h
+++ b/os/hal/ports/SN32/SN32F290/sn32_sys1.h
@@ -75,6 +75,19 @@
   (void)SN_SYS1->AHBCLKEN;                                                  \
 }
 
+/**
+ * @brief   Resets one or more peripheral.
+ *
+ * @param[in] mask      Reset peripherals mask
+ *
+ * @api
+ */
+#define sys1Reset(mask) {                                                   \
+  SN_SYS1->PRST |= (mask);                                                  \
+  SN_SYS1->PRST &= ~(mask);                                                 \
+  (void)SN_SYS1->PRST;                                                      \
+}
+
 /**
  * @brief   Selects the clock prescaler of one or more peripheral on the APB0 bus.
  *
@@ -101,7 +114,7 @@
 
 /** @} */
 /**
- * @name    Dummy GPIO peripherals specific SYS1 operations
+ * @name    Dummy peripherals specific SYS1 operations
  * @{
  */
 /**
@@ -109,22 +122,54 @@
  *
  * @api
  */
-#define sys1EnableP0()
-#define sys1EnableP1()
-#define sys1EnableP2()
-#define sys1EnableP3()
+#define sys1EnableGPIO0()
+#define sys1EnableGPIO1()
+#define sys1EnableGPIO2()
+#define sys1EnableGPIO3()
 /**
  * @brief   Disables the GPIO peripherals clock.
  *
  * @api
  */
-#define sys1DisableP0()
-#define sys1DisableP1()
-#define sys1DisableP2()
-#define sys1DisableP3()
+#define sys1DisableGPIO0()
+#define sys1DisableGPIO1()
+#define sys1DisableGPIO2()
+#define sys1DisableGPIO3()
 
 /** @} */
 
+/**
+ * @name    GPIO peripherals specific SYS1 operations
+ * @{
+ */
+/**
+ * @brief   Resets the GPIO0 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetGPIO0() sys1Reset(0x1<<0)
+
+/**
+ * @brief   Resets the GPIO1 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetGPIO1() sys1Reset(0x1<<1)
+
+/**
+ * @brief   Resets the GPIO2 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetGPIO2() sys1Reset(0x1<<2)
+
+/**
+ * @brief   Resets the GPIO3 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetGPIO3() sys1Reset(0x1<<3)
+
 /**
  * @name    OPA peripherals specific SYS1 operations
  * @{
@@ -145,6 +190,13 @@
  */
 #define sys1DisableOPA() sys1DisableAHB(0x1<<3)
 
+/**
+ * @brief   Resets the OPA peripheral.
+ *
+ * @api
+ */
+#define sys1ResetOPA() sys1Reset(0x1<<28)
+
 /**
  * @name    USB peripherals specific SYS1 operations
  * @{
@@ -181,6 +233,13 @@
  */
 #define sys1DisableCT16B0() sys1DisableAHB(0x1<<5)
 
+/**
+ * @brief   Resets the CT16B0 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetCT16B0() sys1Reset(0x1<<5)
+
 /**
  * @name    CT16B1 peripherals specific SYS1 operations
  * @{
@@ -199,6 +258,13 @@
  */
 #define sys1DisableCT16B1() sys1DisableAHB(0x1<<6)
 
+/**
+ * @brief   Resets the CT16B1 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetCT16B1() sys1Reset(0x1<<6)
+
 /**
  * @name    CT16B2 peripherals specific SYS1 operations
  * @{
@@ -217,6 +283,13 @@
  */
 #define sys1DisableCT16B2() sys1DisableAHB(0x1<<7)
 
+/**
+ * @brief   Resets the CT16B2 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetCT16B2() sys1Reset(0x1<<7)
+
 /**
  * @name    CT16B3 peripherals specific SYS1 operations
  * @{
@@ -235,6 +308,13 @@
  */
 #define sys1DisableCT16B3() sys1DisableAHB(0x1<<8)
 
+/**
+ * @brief   Resets the CT16B3 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetCT16B3() sys1Reset(0x1<<8)
+
 /**
  * @name    CT16B4 peripherals specific SYS1 operations
  * @{
@@ -253,6 +333,13 @@
  */
 #define sys1DisableCT16B4() sys1DisableAHB(0x1<<9)
 
+/**
+ * @brief   Resets the CT16B4 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetCT16B4() sys1Reset(0x1<<9)
+
 /**
  * @name    CT16B5 peripherals specific SYS1 operations
  * @{
@@ -271,6 +358,13 @@
  */
 #define sys1DisableCT16B5() sys1DisableAHB(0x1<<10)
 
+/**
+ * @brief   Resets the CT16B5 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetCT16B5() sys1Reset(0x1<<10)
+
 /**
  * @name    ADC peripherals specific SYS1 operations
  * @{
@@ -289,6 +383,13 @@
  */
 #define sys1DisableADC() sys1DisableAHB(0x1<<11)
 
+/**
+ * @brief   Resets the ADC peripheral.
+ *
+ * @api
+ */
+#define sys1ResetADC() sys1Reset(0x1<<11)
+
 /**
  * @name    SPI0 peripherals specific SYS1 operations
  * @{
@@ -307,6 +408,13 @@
  */
 #define sys1DisableSPI0() sys1DisableAHB(0x1<<12)
 
+/**
+ * @brief   Resets the SPI0 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetSPI0() sys1Reset(0x1<<12)
+
 /**
  * @name    SPI1 peripherals specific SYS1 operations
  * @{
@@ -325,6 +433,13 @@
  */
 #define sys1DisableSPI1() sys1DisableAHB(0x1<<13)
 
+/**
+ * @brief   Resets the SPI1 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetSPI1() sys1Reset(0x1<<13)
+
 /**
  * @name    CMP peripherals specific SYS1 operations
  * @{
@@ -343,6 +458,13 @@
  */
 #define sys1DisableCMP() sys1DisableAHB(0x1<<14)
 
+/**
+ * @brief   Resets the CMP peripheral.
+ *
+ * @api
+ */
+#define sys1ResetCMP() sys1Reset(0x1<<14)
+
 /**
  * @name    EBI peripherals specific SYS1 operations
  * @{
@@ -361,6 +483,13 @@
  */
 #define sys1DisableEBI() sys1DisableAHB(0x1<<15)
 
+/**
+ * @brief   Resets the EBI peripheral.
+ *
+ * @api
+ */
+#define sys1ResetEBI() sys1Reset(0x1<<4)
+
 /**
  * @name    UART0 peripherals specific SYS1 operations
  * @{
@@ -379,6 +508,13 @@
  */
 #define sys1DisableUART0() sys1DisableAHB(0x1<<16)
 
+/**
+ * @brief   Resets the UART0 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetUART0() sys1Reset(0x1<<16)
+
 /**
  * @name    UART1 peripherals specific SYS1 operations
  * @{
@@ -397,6 +533,13 @@
  */
 #define sys1DisableUART1() sys1DisableAHB(0x1<<17)
 
+/**
+ * @brief   Resets the UART1 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetUART1() sys1Reset(0x1<<17)
+
 /**
  * @name    UART2 peripherals specific SYS1 operations
  * @{
@@ -415,6 +558,13 @@
  */
 #define sys1DisableUART2() sys1DisableAHB(0x1<<18)
 
+/**
+ * @brief   Resets the UART2 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetUART2() sys1Reset(0x1<<18)
+
 /**
  * @name    UART3 peripherals specific SYS1 operations
  * @{
@@ -426,6 +576,13 @@
  */
 #define sys1EnableUART3() sys1EnableAHB(0x1<<19)
 
+/**
+ * @brief   Resets the UART3 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetUART3() sys1Reset(0x1<<19)
+
 /**
  * @brief   Disables the UART3 peripheral clock.
  *
@@ -451,6 +608,13 @@
  */
 #define sys1DisableI2C0() sys1DisableAHB(0x1<<21)
 
+/**
+ * @brief   Resets the I2C0 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetI2C0() sys1Reset(0x1<<21)
+
 /**
  * @name    I2C1 peripherals specific SYS1 operations
  * @{
@@ -469,6 +633,13 @@
  */
 #define sys1DisableI2C1() sys1DisableAHB(0x1<<20)
 
+/**
+ * @brief   Resets the I2C1 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetI2C1() sys1Reset(0x1<<20)
+
 /**
  * @name    I2S0 peripherals specific SYS1 operations
  * @{
@@ -487,6 +658,13 @@
  */
 #define sys1DisableI2S0() sys1DisableAHB(0x1<<22)
 
+/**
+ * @brief   Resets the I2S0 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetI2S0() sys1Reset(0x1<<22)
+
 /**
  * @name    RTC peripherals specific SYS1 operations
  * @{
@@ -505,6 +683,13 @@
  */
 #define sys1DisableRTC() sys1DisableAHB(0x1<<23)
 
+/**
+ * @brief   Resets the RTC peripheral.
+ *
+ * @api
+ */
+#define sys1ResetRTC() sys1Reset(0x1<<23)
+
 /**
  * @name    WDT peripherals specific SYS1 operations
  * @{
@@ -523,6 +708,13 @@
  */
 #define sys1DisableWDT() sys1DisableAHB(0x1<<24)
 
+/**
+ * @brief   Resets the WDT peripheral.
+ *
+ * @api
+ */
+#define sys1ResetWDT() sys1Reset(0x1<<24)
+
 /**
  * @name    I2S1 peripherals specific SYS1 operations
  * @{
@@ -541,6 +733,13 @@
  */
 #define sys1DisableI2S1() sys1DisableAHB(0x1<<25)
 
+/**
+ * @brief   Resets the I2S1 peripheral.
+ *
+ * @api
+ */
+#define sys1ResetI2S1() sys1Reset(0x1<<25)
+
 /**
  * @name    LCD peripherals specific SYS1 operations
  * @{
@@ -559,6 +758,13 @@
  */
 #define sys1DisableLCD() sys1DisableAHB(0x1<<26)
 
+/**
+ * @brief   Resets the LCD peripheral.
+ *
+ * @api
+ */
+#define sys1ResetLCD() sys1Reset(0x1<<15)
+
 /**
  * @name    CRC peripherals specific SYS1 operations
  * @{
@@ -577,6 +783,13 @@
  */
 #define sys1DisableCRC() sys1DisableAHB(0x1<<27)
 
+/**
+ * @brief   Resets the CRC peripheral.
+ *
+ * @api
+ */
+#define sys1ResetCRC() sys1Reset(0x1<<26)
+
 /**
  * @name    CLKOUT peripherals specific SYS1 operations
  * @{