occasionally an erroneously incorrect clock enable state is generated, reason unknown

[weatherhead99]

The following WDL code:
`
SLOT 1 driverx {
DRVX 1 [PCLK_fast,PCLK_slow,1] "PCLK_B3_2";
DRVX 2 [PCLK_fast,PCLK_slow,1] "PCLK_A3_2";
DRVX 3 [PCLK_fast,PCLK_slow,1] "PCLK_B2_2";
DRVX 4 [PCLK_fast,PCLK_slow,1] "PCLK_A2_2";
DRVX 5 [PCLK_fast,PCLK_slow,1] "PCLK_B1_2";
DRVX 6 [PCLK_fast,PCLK_slow,1] "PCLK_A1_2";
DRVX 7 [PCLK_fast,PCLK_slow,1] "PCLK_B1_1";
DRVX 8 [PCLK_fast,PCLK_slow,1] "PCLK_A2_1";
DRVX 9 [PCLK_fast,PCLK_slow,1] "PCLK_A2_1";
DRVX 10 [PCLK_fast,PCLK_slow,1] "PCLK_B2_1";
DRVX 11 [PCLK_fast,PCLK_slow,1] "PCLK_A3_1";
DRVX 12 [PCLK_fast,PCLK_slow,1] "PCLK_B3_1";
}

`

appears to erroneously produce an unset "enable" state on the first clock DRV1, see screenshot:

(note unticked enable box, despite [,,1] statement in the "PCLK_B3_2" line definition).

I have no time right now to investigate this. The only special thing I can see about this statement is that it is the first statement in the entire file.

[weatherhead99]

ok, had to investigate this because it finally became a blocker for all of DEIMOS. Turns out it's actually just that the first statement generated after the "[CONFIG]" sigil is always ignored, because existing WDL generates it on the same line as that. Then when ini2acf.pl or ini2acf.py parses that line it throws the rest of the line away, hence always discarding precisely the very first archon config line. This is fixed by explicitly making sure the generator for modules puts an empty line after [CONFIG]