JSJZCYL_Quartus-CPU/cpu_core.bsf at master · CQUT-OpenProject/JSJZCYL_Quartus-CPU · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
	(rect 16 16 224 224)
	(text "cpu_core" (rect 5 0 42 12)(font "Arial" ))
	(text "inst" (rect 8 192 20 204)(font "Arial" ))
	(port
		(pt 0 32)
		(input)
		(text "clk" (rect 0 0 10 12)(font "Arial" ))
		(text "clk" (rect 21 27 31 39)(font "Arial" ))
		(line (pt 0 32)(pt 16 32)(line_width 1))
	)
	(port
		(pt 0 48)
		(input)
		(text "reset_n" (rect 0 0 30 12)(font "Arial" ))
		(text "reset_n" (rect 21 43 51 55)(font "Arial" ))
		(line (pt 0 48)(pt 16 48)(line_width 1))
	)
	(port
		(pt 208 32)
		(output)
		(text "pc_out[15..0]" (rect 0 0 50 12)(font "Arial" ))
		(text "pc_out[15..0]" (rect 137 27 187 39)(font "Arial" ))
		(line (pt 208 32)(pt 192 32)(line_width 3))
	)
	(port
		(pt 208 48)
		(output)
		(text "ir_out[15..0]" (rect 0 0 46 12)(font "Arial" ))
		(text "ir_out[15..0]" (rect 141 43 187 55)(font "Arial" ))
		(line (pt 208 48)(pt 192 48)(line_width 3))
	)
	(port
		(pt 208 64)
		(output)
		(text "r0_out[15..0]" (rect 0 0 49 12)(font "Arial" ))
		(text "r0_out[15..0]" (rect 138 59 187 71)(font "Arial" ))
		(line (pt 208 64)(pt 192 64)(line_width 3))
	)
	(port
		(pt 208 80)
		(output)
		(text "r1_out[15..0]" (rect 0 0 48 12)(font "Arial" ))
		(text "r1_out[15..0]" (rect 139 75 187 87)(font "Arial" ))
		(line (pt 208 80)(pt 192 80)(line_width 3))
	)
	(port
		(pt 208 96)
		(output)
		(text "r2_out[15..0]" (rect 0 0 49 12)(font "Arial" ))
		(text "r2_out[15..0]" (rect 138 91 187 103)(font "Arial" ))
		(line (pt 208 96)(pt 192 96)(line_width 3))
	)
	(port
		(pt 208 112)
		(output)
		(text "r3_out[15..0]" (rect 0 0 49 12)(font "Arial" ))
		(text "r3_out[15..0]" (rect 138 107 187 119)(font "Arial" ))
		(line (pt 208 112)(pt 192 112)(line_width 3))
	)
	(port
		(pt 208 128)
		(output)
		(text "alu_out[15..0]" (rect 0 0 51 12)(font "Arial" ))
		(text "alu_out[15..0]" (rect 136 123 187 135)(font "Arial" ))
		(line (pt 208 128)(pt 192 128)(line_width 3))
	)
	(port
		(pt 208 144)
		(output)
		(text "mem_q_out[15..0]" (rect 0 0 73 12)(font "Arial" ))
		(text "mem_q_out[15..0]" (rect 114 139 187 151)(font "Arial" ))
		(line (pt 208 144)(pt 192 144)(line_width 3))
	)
	(port
		(pt 208 160)
		(output)
		(text "disp_out[15..0]" (rect 0 0 56 12)(font "Arial" ))
		(text "disp_out[15..0]" (rect 131 155 187 167)(font "Arial" ))
		(line (pt 208 160)(pt 192 160)(line_width 3))
	)
	(port
		(pt 208 176)
		(output)
		(text "halted" (rect 0 0 22 12)(font "Arial" ))
		(text "halted" (rect 165 171 187 183)(font "Arial" ))
		(line (pt 208 176)(pt 192 176)(line_width 1))
	)
	(drawing
		(rectangle (rect 16 16 192 192)(line_width 1))
	)
)