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Refactor polyhal with multi modules (#9)
* refactor project structure * feat: use a new boot design * opt: init the boot design for these arch * feat: using new ph-ctor design * opt: make boot and polyhal more fluent * feat: use standalone trap design * feat: pass partial trap support * faet: pass basic support * opt: clean unneeded code * opt: using fdt-parser as default dtb parser * opt: append tips * opt: fix some for clippy and format * opt: merge arch and consts mod * feat: optimize for percpu * feat: support boot multicore * opt: optimize for multicore * feat: support x86_64 acpi * feat: optimize pci support * feat: add graphic support * feat: optimize x86_64 console support * feat: support x86_64 MultiCore * feat: publish to crates.io * cargo: fixed x86_64 version * opt: optimize for partial code * feat: support print and Duration * feat: init timer and prevent time overflow * bump: bump to 0.2.3 * feat: bump to 0.2.4 * using x86_64 port of crates.io
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.cargo/config.toml

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.gitignore

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target
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output.log
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qemu.log
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qemu-*.log
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*.iso
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!example/iso/grub/*
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example/iso/*
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example/qemu-*.log
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example/*.lds
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!example/linker.lds
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mount.img
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example/virt.out
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qemu.dtb

.vscode/settings.json

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{
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"rust-analyzer.check.allTargets": false,
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"rust-analyzer.check.targets": [
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"riscv64gc-unknown-none-elf",
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"aarch64-unknown-none-softfloat",
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"x86_64-unknown-none",
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"loongarch64-unknown-none",
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],
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"rust-analyzer.check.features": "all",
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"rust-analyzer.check.extraArgs": [],
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// "rust-analyzer.cargo.target": "aarch64-unknown-none-softfloat",
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"rust-analyzer.cargo.target": "riscv64gc-unknown-none-elf",
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// "rust-analyzer.cargo.target": "loongarch64-unknown-none",
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// "rust-analyzer.cargo.target": "x86_64-unknown-none",
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"rust-analyzer.check.targets": [
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"riscv64gc-unknown-none-elf",
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"aarch64-unknown-none-softfloat",
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"x86_64-unknown-none",
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"loongarch64-unknown-none"
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],
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"rust-analyzer.check.features": "all",
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"rust-analyzer.check.extraArgs": []
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}

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