GPU.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:40:57 06/03/2025 
-- Design Name: 
-- Module Name:    GPU - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity GPU is port(
GPUClk : in  std_logic;
HSync  : out std_logic;
VSync  : out std_logic;
color  : out std_logic_vector(7 downto 0));
end GPU;

architecture Behavioral of GPU is

signal x, y, nx, ny : integer range 0 to 1023;

begin process (GPUClk) begin
	if rising_edge(GPUClk) then
		
		-- Newline
		if (nx=799) then
			nx <= 0;
			if (ny=525) then
				ny <= 0;
			else ny <= ny+1;
			end if;
		else nx <= nx+1;
		end if;
		
		-- VSync signal
		if (y>=490) and (y<492) then vsync <= '0';
		else vsync <= '1';
		end if;
		
		-- HSync signal
		if (x>=656) and (x<752) then hsync <= '0';
		else hsync <= '1';
		end if;
		
		x <= nx;
		y <= ny;
	end if;
end process;

GUI : entity GUI port map(
GPUClk => GPUClk,
x => nx,
y => ny,
color => color);

end Behavioral;