3232#include "shared-bindings/microcontroller/Pin.h"
3333
3434#include "max32_port.h"
35- #include "spi_reva1.h"
3635
3736// Note that any bugs introduced in this file can cause crashes
3837// at startupfor chips using external SPI flash.
@@ -72,25 +71,11 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self,
7271 self -> spi_regs = MXC_SPI_GET_SPI (spi_id );
7372 }
7473
75- // Other pins default to true
76- mxc_spi_pins_t spi_pins = {
77- .clock = TRUE,
78- .mosi = TRUE,
79- .miso = TRUE,
80- .ss0 = FALSE,
81- .ss1 = FALSE,
82- .ss2 = FALSE,
83- .vddioh = true,
84- .drvstr = MXC_GPIO_DRVSTR_0
85- };
86-
8774 assert ((self -> spi_id >= 0 ) && (self -> spi_id < NUM_SPI ));
8875
8976 // Init SPI controller
9077 if ((mosi != NULL ) && (miso != NULL ) && (sck != NULL )) {
91- // spi, mastermode, quadModeUsed, numSubs, ssPolarity, frequency
92- err = MXC_SPI_Init (self -> spi_regs , MXC_SPI_TYPE_CONTROLLER , MXC_SPI_INTERFACE_STANDARD ,
93- 1 , 0x01 , 1000000 , spi_pins );
78+ err = spi_init (self -> spi_regs , 1000000 );
9479 MXC_GPIO_SetVSSEL (MXC_GPIO_GET_GPIO (sck -> port ), MXC_GPIO_VSSEL_VDDIOH , (sck -> mask | miso -> mask | mosi -> mask | MXC_GPIO_PIN_0 ));
9580 if (err ) {
9681 // NOTE: Reuse existing messages from locales/circuitpython.pot to save space
@@ -154,7 +139,7 @@ bool common_hal_busio_spi_configure(busio_spi_obj_t *self,
154139 uint8_t phase ,
155140 uint8_t bits ) {
156141
157- mxc_spi_clkmode_t clk_mode ;
142+ mxc_spi_mode_t spi_mode ;
158143 int ret ;
159144
160145 self -> baudrate = baudrate ;
@@ -164,16 +149,16 @@ bool common_hal_busio_spi_configure(busio_spi_obj_t *self,
164149
165150 switch ((polarity << 1 ) | (phase )) {
166151 case 0b00 :
167- clk_mode = MXC_SPI_CLKMODE_0 ;
152+ spi_mode = SPI_MODE_0 ;
168153 break ;
169154 case 0b01 :
170- clk_mode = MXC_SPI_CLKMODE_1 ;
155+ spi_mode = SPI_MODE_1 ;
171156 break ;
172157 case 0b10 :
173- clk_mode = MXC_SPI_CLKMODE_2 ;
158+ spi_mode = SPI_MODE_2 ;
174159 break ;
175160 case 0b11 :
176- clk_mode = MXC_SPI_CLKMODE_3 ;
161+ spi_mode = SPI_MODE_3 ;
177162 break ;
178163 default :
179164 // should not be reachable; validated in shared-bindings/busio/SPI.c
@@ -192,7 +177,7 @@ bool common_hal_busio_spi_configure(busio_spi_obj_t *self,
192177 } else if (ret == E_BAD_STATE ) {
193178 mp_raise_RuntimeError (MP_ERROR_TEXT ("Invalid state" ));
194179 }
195- ret = MXC_SPI_SetMode (self -> spi_regs , clk_mode );
180+ ret = MXC_SPI_SetMode (self -> spi_regs , spi_mode );
196181 if (ret ) {
197182 mp_raise_ValueError (MP_ERROR_TEXT ("Failed to set SPI Clock Mode" ));
198183 return false;
@@ -226,6 +211,8 @@ bool common_hal_busio_spi_write(busio_spi_obj_t *self,
226211 size_t len ) {
227212 int ret = 0 ;
228213
214+ MXC_SPI_SetDefaultTXData (self -> spi_regs , 0xFF );
215+
229216 mxc_spi_req_t wr_req = {
230217 .spi = self -> spi_regs ,
231218 .ssIdx = 0 ,
@@ -237,7 +224,6 @@ bool common_hal_busio_spi_write(busio_spi_obj_t *self,
237224 .rxLen = 0 ,
238225 .ssDeassert = 1 ,
239226 .completeCB = NULL ,
240- .txDummyValue = 0xFF ,
241227 };
242228 ret = MXC_SPI_MasterTransaction (& wr_req );
243229 if (ret ) {
@@ -254,6 +240,8 @@ bool common_hal_busio_spi_read(busio_spi_obj_t *self,
254240
255241 int ret = 0 ;
256242
243+ MXC_SPI_SetDefaultTXData (self -> spi_regs , write_value );
244+
257245 mxc_spi_req_t rd_req = {
258246 .spi = self -> spi_regs ,
259247 .ssIdx = 0 ,
@@ -265,7 +253,6 @@ bool common_hal_busio_spi_read(busio_spi_obj_t *self,
265253 .rxLen = len ,
266254 .ssDeassert = 1 ,
267255 .completeCB = NULL ,
268- .txDummyValue = write_value ,
269256 };
270257 ret = MXC_SPI_MasterTransaction (& rd_req );
271258 if (ret ) {
@@ -284,7 +271,9 @@ bool common_hal_busio_spi_transfer(busio_spi_obj_t *self,
284271
285272 int ret = 0 ;
286273
287- mxc_spi_req_t rd_req = {
274+ MXC_SPI_SetDefaultTXData (self -> spi_regs , 0xFF );
275+
276+ mxc_spi_req_t transfer_req = {
288277 .spi = self -> spi_regs ,
289278 .ssIdx = 0 ,
290279 .txCnt = 0 ,
@@ -295,9 +284,8 @@ bool common_hal_busio_spi_transfer(busio_spi_obj_t *self,
295284 .rxLen = len ,
296285 .ssDeassert = 1 ,
297286 .completeCB = NULL ,
298- .txDummyValue = 0xFF ,
299287 };
300- ret = MXC_SPI_MasterTransaction (& rd_req );
288+ ret = MXC_SPI_MasterTransaction (& transfer_req );
301289 if (ret ) {
302290 return false;
303291 } else {
0 commit comments