diff --git a/edg/abstract_parts/AbstractCapacitor.py b/edg/abstract_parts/AbstractCapacitor.py index 940b3c211..498ef4882 100644 --- a/edg/abstract_parts/AbstractCapacitor.py +++ b/edg/abstract_parts/AbstractCapacitor.py @@ -264,15 +264,16 @@ def add_derated_row(row: PartsTableRow) -> Optional[Dict[PartsTableColumn, Any]] )) def _row_generate(self, row: PartsTableRow) -> None: + """This one is weird. Because this is the last in the class order, this is called last. + So the top subclass needs explicit logic to handle parallel capacitors.""" + super()._row_generate(row) if row[self.PARALLEL_COUNT] == 1: - super()._row_generate(row) # creates the footprint self.assign(self.actual_derated_capacitance, row[self.DERATED_CAPACITANCE]) else: self.assign(self.actual_part, f"{row[self.PARALLEL_COUNT]}x {row[self.PART_NUMBER_COL]}") self.assign(self.actual_voltage_rating, row[self.VOLTAGE_RATING]) self.assign(self.actual_capacitance, row[self.PARALLEL_CAPACITANCE]) self.assign(self.actual_derated_capacitance, row[self.PARALLEL_DERATED_CAPACITANCE]) - self._make_parallel_footprints(row) @abstractmethod def _make_parallel_footprints(self, row: PartsTableRow) -> None: diff --git a/edg/abstract_parts/AbstractComparator.py b/edg/abstract_parts/AbstractComparator.py index 5f44cd070..2d06f6ce8 100644 --- a/edg/abstract_parts/AbstractComparator.py +++ b/edg/abstract_parts/AbstractComparator.py @@ -1,9 +1,10 @@ from typing import Mapping +from ..abstract_parts import Analog from ..electronics_model import * -class Comparator(KiCadInstantiableBlock, Block): +class Comparator(KiCadInstantiableBlock, Analog): """Abstract comparator interface, output goes high when inp > inn.""" def symbol_pinning(self, symbol_name: str) -> Mapping[str, BasePort]: assert symbol_name in ('Simulation_SPICE:OPAMP', 'edg_importable:Opamp') diff --git a/edg/abstract_parts/AbstractFuse.py b/edg/abstract_parts/AbstractFuse.py index 1629b1a14..2307b3079 100644 --- a/edg/abstract_parts/AbstractFuse.py +++ b/edg/abstract_parts/AbstractFuse.py @@ -1,5 +1,7 @@ from typing import Optional, cast +from deprecated import deprecated + from ..electronics_model import * from .Categories import * from .PartsTable import PartsTableColumn, PartsTableRow @@ -132,5 +134,6 @@ def _row_generate(self, row: PartsTableRow) -> None: self.assign(self.actual_voltage_rating, row[self.VOLTAGE_RATING]) +@deprecated("Use SeriesPowerFuse and a top-level refinement to specify a PPTC fuse") class SeriesPowerPptcFuse(SeriesPowerFuse): FUSE_TYPE = PptcFuse diff --git a/edg/abstract_parts/AbstractLedDriver.py b/edg/abstract_parts/AbstractLedDriver.py index 9958b675d..fcc1b1ce4 100644 --- a/edg/abstract_parts/AbstractLedDriver.py +++ b/edg/abstract_parts/AbstractLedDriver.py @@ -1,4 +1,5 @@ from ..abstract_parts import * +from deprecated import deprecated @abstract_block @@ -18,6 +19,7 @@ def __init__(self, max_current: RangeLike): self.max_current = self.ArgParameter(max_current) +@deprecated("ripple should be an internal parameter") class LedDriverSwitchingConverter(BlockInterfaceMixin[LedDriver]): """LED driver mixin indicating that the LED driver is a switching converter and with a peak-peak ripple limit.""" @init_in_parent diff --git a/edg/abstract_parts/Categories.py b/edg/abstract_parts/Categories.py index 6c4d93497..7d3a3fb06 100644 --- a/edg/abstract_parts/Categories.py +++ b/edg/abstract_parts/Categories.py @@ -32,6 +32,12 @@ class AnalogFilter(Filter): pass +@abstract_block +class RfFilter(AnalogFilter): + """RF signal conditioning subcircuit.""" + pass + + @abstract_block class DigitalFilter(Filter): """Digital signal conditioning block.""" diff --git a/edg/abstract_parts/I2cBitBang.py b/edg/abstract_parts/I2cBitBang.py index 2535599c2..d98c2e888 100644 --- a/edg/abstract_parts/I2cBitBang.py +++ b/edg/abstract_parts/I2cBitBang.py @@ -6,19 +6,6 @@ class I2cControllerBitBang(BitBangAdapter, Block): """Bit-bang adapter for I2C controller""" - @staticmethod - def digital_external_from_link(link_port: DigitalBidir) -> DigitalBidir: - """Creates a DigitalBidir model that is the external-facing port that exports from - an internal-facing (link-side) port. The internal-facing port should be ideal. - These are basically the semantics of a DigitalBidir bridge. - TODO: unify code w/ DigitalBidir bridge?""" - return DigitalBidir( - voltage_out=link_port.link().voltage, current_draw=link_port.link().current_drawn, - voltage_limits=link_port.link().voltage_limits, current_limits=link_port.link().current_limits, - output_thresholds=link_port.link().output_thresholds, input_thresholds=link_port.link().input_thresholds, - pulldown_capable=link_port.link().pulldown_capable, pullup_capable=link_port.link().pullup_capable - ) - def __init__(self) -> None: super().__init__() self.i2c = self.Port(I2cController.empty(), [Output]) diff --git a/edg/abstract_parts/IoController.py b/edg/abstract_parts/IoController.py index fb734ee80..6bf26ec2b 100644 --- a/edg/abstract_parts/IoController.py +++ b/edg/abstract_parts/IoController.py @@ -8,6 +8,7 @@ from .Categories import ProgrammableController +@non_library @abstract_block class BaseIoController(PinMappable, Block): """An abstract IO controller block, that takes power input and provides a grab-bag of common IOs. diff --git a/edg/abstract_parts/RfNetworks.py b/edg/abstract_parts/RfNetworks.py index 9ed1cfb8c..bbec2d761 100644 --- a/edg/abstract_parts/RfNetworks.py +++ b/edg/abstract_parts/RfNetworks.py @@ -56,7 +56,7 @@ def _calculate_values(cls, freq: float, z1: complex, z2: complex) -> Tuple[float PiLowPassFilter._reactance_to_capacitance(freq, xp) -class LLowPassFilterWith2HNotch(AnalogFilter, GeneratorBlock): +class LLowPassFilterWith2HNotch(GeneratorBlock, RfFilter): """L filter for impedance matching for RF with an overlaid second-harmonic LC notch filter. The target reactance is given by the L filter. Then, the L and C values are from the simultaneous solution of: @@ -143,7 +143,7 @@ def _calculate_values(cls, freq: float, z1: complex, z2: complex) -> Tuple[float PiLowPassFilter._reactance_to_capacitance(freq, net_xs - xs2) -class PiLowPassFilter(AnalogFilter, GeneratorBlock): +class PiLowPassFilter(GeneratorBlock, RfFilter): """Passive-typed pi impedance matching network. Based on equations from https://www.silabs.com/documents/public/application-notes/an1275-imp-match-for-network-arch.pdf and also referencing https://www.electronicdesign.com/technologies/communications/article/21801154/back-to-basics-impedance-matching-part-3 diff --git a/edg/abstract_parts/__init__.py b/edg/abstract_parts/__init__.py index a6c1fedc3..725ff44dc 100644 --- a/edg/abstract_parts/__init__.py +++ b/edg/abstract_parts/__init__.py @@ -9,7 +9,7 @@ from .Categories import DiscreteComponent, DiscreteSemiconductor, PassiveComponent from .Categories import DiscreteApplication from .Categories import Analog, OpampApplication -from .Categories import Filter, AnalogFilter, DigitalFilter +from .Categories import Filter, AnalogFilter, RfFilter, DigitalFilter from .Categories import Microcontroller, Fpga, Memory, RealtimeClock, Radiofrequency from .Categories import Interface, AnalogToDigital, DigitalToAnalog, SpeakerDriver, IoExpander, BitBangAdapter from .Categories import PowerConditioner, PowerSwitch, MotorDriver, BrushedMotorDriver, BldcDriver diff --git a/edg/electronics_model/CircuitBlock.py b/edg/electronics_model/CircuitBlock.py index 2acb4fa5f..ab1f9f4e5 100644 --- a/edg/electronics_model/CircuitBlock.py +++ b/edg/electronics_model/CircuitBlock.py @@ -91,6 +91,7 @@ def footprint(self, refdes: StringLike, footprint: StringLike, pinning: Mapping[ self.assign(self.fp_datasheet, '') +@non_library class WrapperFootprintBlock(FootprintBlock): """Block that has a footprint and optional internal contents, but the netlister ignores internal components. Useful for, for example, a breakout board where the modelling details are provided by internal chip blocks, diff --git a/edg/jlcparts/JlcPartsBjt.py b/edg/jlcparts/JlcPartsBjt.py index 3564970d9..5fe5ba887 100644 --- a/edg/jlcparts/JlcPartsBjt.py +++ b/edg/jlcparts/JlcPartsBjt.py @@ -4,7 +4,7 @@ from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes -class JlcPartsBjt(TableBjt, PartsTableSelectorFootprint, JlcPartsBase): +class JlcPartsBjt(PartsTableSelectorFootprint, JlcPartsBase, TableBjt): _JLC_PARTS_FILE_NAMES = ["TransistorsBipolar_Transistors___BJT"] _CHANNEL_MAP = { 'NPN': 'NPN', diff --git a/edg/jlcparts/JlcPartsDiode.py b/edg/jlcparts/JlcPartsDiode.py index 4e9a4ba25..af7d2a65c 100644 --- a/edg/jlcparts/JlcPartsDiode.py +++ b/edg/jlcparts/JlcPartsDiode.py @@ -4,7 +4,7 @@ from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes -class JlcPartsDiode(TableDiode, PartsTableSelectorFootprint, JlcPartsBase): +class JlcPartsDiode(PartsTableSelectorFootprint, JlcPartsBase, TableDiode): _JLC_PARTS_FILE_NAMES = [ "DiodesSchottky_Barrier_Diodes__SBD_", "DiodesDiodes___Fast_Recovery_Rectifiers", diff --git a/edg/jlcparts/JlcPartsElectrolyticCapacitor.py b/edg/jlcparts/JlcPartsElectrolyticCapacitor.py index c6650b68a..e6a805420 100644 --- a/edg/jlcparts/JlcPartsElectrolyticCapacitor.py +++ b/edg/jlcparts/JlcPartsElectrolyticCapacitor.py @@ -4,7 +4,7 @@ from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes -class JlcPartsElectrolyticCapacitor(TableCapacitor, AluminumCapacitor, PartsTableSelectorFootprint, JlcPartsBase): +class JlcPartsElectrolyticCapacitor(PartsTableSelectorFootprint, JlcPartsBase, TableCapacitor, AluminumCapacitor): _JLC_PARTS_FILE_NAMES = ["CapacitorsAluminum_Electrolytic_Capacitors___SMD"] _PACKAGE_PARSER = re.compile(r"^SMD,D([\d.]+)xL([\d.]+)mm$") diff --git a/edg/jlcparts/JlcPartsFerriteBead.py b/edg/jlcparts/JlcPartsFerriteBead.py index 6d7a5ea64..38f094de5 100644 --- a/edg/jlcparts/JlcPartsFerriteBead.py +++ b/edg/jlcparts/JlcPartsFerriteBead.py @@ -4,7 +4,7 @@ from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes -class JlcPartsFerriteBead(TableFerriteBead, PartsTableSelectorFootprint, JlcPartsBase): +class JlcPartsFerriteBead(PartsTableSelectorFootprint, JlcPartsBase, TableFerriteBead): _JLC_PARTS_FILE_NAMES = ["FiltersakaEMI_OptimizationFerrite_Beads"] @classmethod diff --git a/edg/jlcparts/JlcPartsFet.py b/edg/jlcparts/JlcPartsFet.py index 8adee387e..5b666b4cf 100644 --- a/edg/jlcparts/JlcPartsFet.py +++ b/edg/jlcparts/JlcPartsFet.py @@ -53,11 +53,11 @@ def _entry_to_table_row(cls, row_dict: Dict[PartsTableColumn, Any], filename: st return None -class JlcPartsFet(TableFet, PartsTableSelectorFootprint, JlcPartsBaseFet): +class JlcPartsFet(PartsTableSelectorFootprint, JlcPartsBaseFet, TableFet): pass -class JlcPartsSwitchFet(TableSwitchFet, PartsTableSelectorFootprint, JlcPartsBaseFet): +class JlcPartsSwitchFet(PartsTableSelectorFootprint, JlcPartsBaseFet, TableSwitchFet): @init_in_parent def __init__(self, *args, manual_gate_charge: RangeLike = RangeExpr.ZERO, **kwargs): super().__init__(*args, **kwargs) diff --git a/edg/jlcparts/JlcPartsLed.py b/edg/jlcparts/JlcPartsLed.py index 8d3db8fd7..5d2f264bc 100644 --- a/edg/jlcparts/JlcPartsLed.py +++ b/edg/jlcparts/JlcPartsLed.py @@ -4,7 +4,7 @@ from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes -class JlcPartsLed(TableLed, PartsTableSelectorFootprint, JlcPartsBase): +class JlcPartsLed(PartsTableSelectorFootprint, JlcPartsBase, TableLed): _JLC_PARTS_FILE_NAMES = [ "OptoelectronicsLight_Emitting_Diodes__LED_", "OptoelectronicsLED_Indication___Discrete", diff --git a/edg/jlcparts/JlcPartsMlcc.py b/edg/jlcparts/JlcPartsMlcc.py index a759dfa40..267293d38 100644 --- a/edg/jlcparts/JlcPartsMlcc.py +++ b/edg/jlcparts/JlcPartsMlcc.py @@ -4,7 +4,7 @@ from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes -class JlcPartsMlcc(TableDeratingCapacitor, CeramicCapacitor, PartsTableSelectorFootprint, JlcPartsBase): +class JlcPartsMlcc(PartsTableSelectorFootprint, JlcPartsBase, TableDeratingCapacitor, CeramicCapacitor): _JLC_PARTS_FILE_NAMES = ["CapacitorsMultilayer_Ceramic_Capacitors_MLCC___SMDakaSMT"] @init_in_parent @@ -63,6 +63,15 @@ def filter_minimum_size(row: PartsTableRow) -> Optional[Dict[PartsTableColumn, A def _row_sort_by(cls, row: PartsTableRow) -> Any: return [row[cls.PARALLEL_COUNT], super(JlcPartsMlcc, cls)._row_sort_by(row)] + def _row_generate(self, row: PartsTableRow) -> None: + # see comment in TableCapacitor._row_generate for why this needs to be here + if row[self.PARALLEL_COUNT] == 1: + super()._row_generate(row) # creates the footprint + else: + TableCapacitor._row_generate(self, row) # skips creating the footprint in PartsTableSelectorFootprint + self.assign(self.actual_basic_part, True) # dummy value + self._make_parallel_footprints(row) + def _make_parallel_footprints(self, row: PartsTableRow) -> None: cap_model = JlcDummyCapacitor(set_lcsc_part=row[self.LCSC_COL], set_basic_part=row[self.BASIC_PART_COL], @@ -77,8 +86,5 @@ def _make_parallel_footprints(self, row: PartsTableRow) -> None: self.connect(self.c[i].pos, self.pos) self.connect(self.c[i].neg, self.neg) - self.assign(self.lcsc_part, row[self.LCSC_COL]) - self.assign(self.actual_basic_part, row[self.BASIC_PART_COL]) - lambda: JlcPartsMlcc() # ensure class is instantiable (non-abstract) diff --git a/edg/jlcparts/JlcPartsPptcFuse.py b/edg/jlcparts/JlcPartsPptcFuse.py index 7f946dbf4..405c20ed4 100644 --- a/edg/jlcparts/JlcPartsPptcFuse.py +++ b/edg/jlcparts/JlcPartsPptcFuse.py @@ -4,7 +4,7 @@ from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes -class JlcPartsPptcFuse(TableFuse, PptcFuse, PartsTableSelectorFootprint, JlcPartsBase): +class JlcPartsPptcFuse(PartsTableSelectorFootprint, JlcPartsBase, TableFuse, PptcFuse): _JLC_PARTS_FILE_NAMES = ["Circuit_ProtectionResettable_Fuses"] @classmethod diff --git a/edg/jlcparts/JlcPartsResistorSmd.py b/edg/jlcparts/JlcPartsResistorSmd.py index 88d5429a5..1f22e6061 100644 --- a/edg/jlcparts/JlcPartsResistorSmd.py +++ b/edg/jlcparts/JlcPartsResistorSmd.py @@ -4,7 +4,7 @@ from .JlcPartsBase import JlcPartsBase, JlcPartsAttributes -class JlcPartsResistorSmd(TableResistor, PartsTableSelectorFootprint, JlcPartsBase): +class JlcPartsResistorSmd(PartsTableSelectorFootprint, JlcPartsBase, TableResistor): _JLC_PARTS_FILE_NAMES = ["ResistorsChip_Resistor___Surface_Mount"] @classmethod diff --git a/edg/parts/JlcAntenna.py b/edg/parts/JlcAntenna.py index c56d671ca..736646db5 100644 --- a/edg/parts/JlcAntenna.py +++ b/edg/parts/JlcAntenna.py @@ -4,7 +4,7 @@ from .JlcPart import JlcTableSelector -class JlcAntenna(TableAntenna, JlcTableSelector, FootprintBlock): +class JlcAntenna(JlcTableSelector, TableAntenna, FootprintBlock): # abstract Antenna does not define standard footprints, so we cannot mix in PartsTableSelectorFootprint # to do footprint generation diff --git a/edg/parts/JlcBjt.py b/edg/parts/JlcBjt.py index 2772a4959..aa4ec5022 100644 --- a/edg/parts/JlcBjt.py +++ b/edg/parts/JlcBjt.py @@ -5,7 +5,7 @@ from .JlcPart import DescriptionParser, JlcTableSelector -class JlcBjt(TableBjt, PartsTableSelectorFootprint, JlcTableSelector): +class JlcBjt(PartsTableSelectorFootprint, JlcTableSelector, TableBjt): PACKAGE_FOOTPRINT_MAP = { 'SOT-23': 'Package_TO_SOT_SMD:SOT-23', 'SOT-23-3': 'Package_TO_SOT_SMD:SOT-23', diff --git a/edg/parts/JlcCapacitor.py b/edg/parts/JlcCapacitor.py index ddbd9128f..d01687648 100644 --- a/edg/parts/JlcCapacitor.py +++ b/edg/parts/JlcCapacitor.py @@ -5,7 +5,7 @@ from .JlcPart import JlcPart, JlcTableSelector -class JlcCapacitor(TableDeratingCapacitor, CeramicCapacitor, PartsTableSelectorFootprint, JlcTableSelector): +class JlcCapacitor(JlcTableSelector, PartsTableSelectorFootprint, TableDeratingCapacitor, CeramicCapacitor): PACKAGE_FOOTPRINT_MAP = { '0201': 'Capacitor_SMD:C_0201_0603Metric', '0402': 'Capacitor_SMD:C_0402_1005Metric', @@ -104,6 +104,15 @@ def filter_minimum_size(row: PartsTableRow) -> Optional[Dict[PartsTableColumn, A def _row_sort_by(cls, row: PartsTableRow) -> Any: return [row[cls.PARALLEL_COUNT], super(JlcCapacitor, cls)._row_sort_by(row)] + def _row_generate(self, row: PartsTableRow) -> None: + # see comment in TableCapacitor._row_generate for why this needs to be here + if row[self.PARALLEL_COUNT] == 1: + super()._row_generate(row) # creates the footprint + else: + TableCapacitor._row_generate(self, row) # skips creating the footprint in PartsTableSelectorFootprint + self.assign(self.actual_basic_part, True) # dummy value + self._make_parallel_footprints(row) + def _make_parallel_footprints(self, row: PartsTableRow) -> None: cap_model = JlcDummyCapacitor(set_lcsc_part=row[self.LCSC_PART_HEADER], set_basic_part=row[self.BASIC_PART_HEADER] == self.BASIC_PART_VALUE, @@ -118,18 +127,16 @@ def _make_parallel_footprints(self, row: PartsTableRow) -> None: self.connect(self.c[i].pos, self.pos) self.connect(self.c[i].neg, self.neg) - self.assign(self.lcsc_part, row[self.LCSC_PART_HEADER]) - self.assign(self.actual_basic_part, row[self.BASIC_PART_HEADER] == self.BASIC_PART_VALUE) - -class JlcDummyCapacitor(DummyCapacitorFootprint, JlcPart): +class JlcDummyCapacitor(JlcPart, DummyCapacitorFootprint): """Dummy capacitor that additionally has JLC part fields """ @init_in_parent def __init__(self, set_lcsc_part: StringLike = "", set_basic_part: BoolLike = False, footprint: StringLike = "", manufacturer: StringLike = "", part_number: StringLike = "", value: StringLike = "", *args, **kwargs) -> None: - super().__init__(footprint, manufacturer, part_number, value, *args, **kwargs) + super().__init__(footprint=footprint, manufacturer=manufacturer, part_number=part_number, + value=value, *args, **kwargs) self.assign(self.lcsc_part, set_lcsc_part) self.assign(self.actual_basic_part, set_basic_part) diff --git a/edg/parts/JlcCrystal.py b/edg/parts/JlcCrystal.py index 002184f74..ad1ba4a5a 100644 --- a/edg/parts/JlcCrystal.py +++ b/edg/parts/JlcCrystal.py @@ -4,7 +4,7 @@ from .JlcPart import JlcTableSelector, DescriptionParser -class JlcCrystal(TableCrystal, PartsTableSelectorFootprint, JlcTableSelector): +class JlcCrystal(PartsTableSelectorFootprint, JlcTableSelector, TableCrystal): SERIES_PACKAGE_FOOTPRINT_MAP = { ('X3225', 'SMD-3225_4P'): 'Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm', ('TXM', 'SMD-2520_4P'): 'Crystal:Crystal_SMD_2520-4Pin_2.5x2.0mm', diff --git a/edg/parts/JlcDiode.py b/edg/parts/JlcDiode.py index 0cf5648f1..704b2cfed 100644 --- a/edg/parts/JlcDiode.py +++ b/edg/parts/JlcDiode.py @@ -18,7 +18,7 @@ class JlcBaseDiode: } -class JlcDiode(TableDiode, PartsTableSelectorFootprint, JlcTableSelector, JlcBaseDiode): +class JlcDiode(PartsTableSelectorFootprint, JlcTableSelector, JlcBaseDiode, TableDiode): DESCRIPTION_PARSERS: List[DescriptionParser] = [ (re.compile("(\S+V) (\S+V)@\S+A (\S+A) .* Schottky Barrier Diodes \(SBD\).*"), lambda match: { @@ -75,7 +75,7 @@ def parse_row(row: PartsTableRow) -> Optional[Dict[PartsTableColumn, Any]]: return cls._jlc_table().map_new_columns(parse_row) -class JlcZenerDiode(TableZenerDiode, PartsTableSelectorFootprint, JlcTableSelector, JlcBaseDiode): +class JlcZenerDiode(PartsTableSelectorFootprint, JlcTableSelector, JlcBaseDiode, TableZenerDiode): DESCRIPTION_PARSERS: List[DescriptionParser] = [ (re.compile("\S+A@\S+V (±\S+%) \S+Ω (?:Single )?(\S+W) (\S+V).* Zener Diodes.*"), lambda match: { diff --git a/edg/parts/JlcElectrolyticCapacitor.py b/edg/parts/JlcElectrolyticCapacitor.py index 686723655..1882dbf11 100644 --- a/edg/parts/JlcElectrolyticCapacitor.py +++ b/edg/parts/JlcElectrolyticCapacitor.py @@ -5,7 +5,7 @@ from .JlcPart import DescriptionParser, JlcTableSelector -class JlcAluminumCapacitor(TableCapacitor, AluminumCapacitor, PartsTableSelectorFootprint, JlcTableSelector): +class JlcAluminumCapacitor(PartsTableSelectorFootprint, JlcTableSelector, TableCapacitor, AluminumCapacitor): DESCRIPTION_PARSERS: List[DescriptionParser] = [ (re.compile(".* (\S+F).* (\S+V).* (±\S+%).*([\d\.]+x[\d\.]+)mm Aluminum Electrolytic Capacitors.*"), lambda match: { # discard the HF impedance parameter diff --git a/edg/parts/JlcFerriteBead.py b/edg/parts/JlcFerriteBead.py index 1450d8744..2f6402fe5 100644 --- a/edg/parts/JlcFerriteBead.py +++ b/edg/parts/JlcFerriteBead.py @@ -5,7 +5,7 @@ from .JlcPart import DescriptionParser, JlcTableSelector -class JlcFerriteBead(TableFerriteBead, PartsTableSelectorFootprint, JlcTableSelector): +class JlcFerriteBead(PartsTableSelectorFootprint, JlcTableSelector, TableFerriteBead): PACKAGE_FOOTPRINT_MAP = { '0402': 'Inductor_SMD:L_0402_1005Metric', '0603': 'Inductor_SMD:L_0603_1608Metric', diff --git a/edg/parts/JlcFet.py b/edg/parts/JlcFet.py index 1d83e0482..dcea7cc26 100644 --- a/edg/parts/JlcFet.py +++ b/edg/parts/JlcFet.py @@ -80,11 +80,11 @@ def parse_row(row: PartsTableRow) -> Optional[Dict[PartsTableColumn, Any]]: return cls._jlc_table().map_new_columns(parse_row) -class JlcFet(TableFet, PartsTableSelectorFootprint, JlcBaseFet): +class JlcFet(PartsTableSelectorFootprint, JlcBaseFet, TableFet): pass -class JlcSwitchFet(TableSwitchFet, PartsTableSelectorFootprint, JlcBaseFet): +class JlcSwitchFet(PartsTableSelectorFootprint, JlcBaseFet, TableSwitchFet): @init_in_parent def __init__(self, *args, manual_gate_charge: RangeLike = RangeExpr.ZERO, **kwargs): super().__init__(*args, **kwargs) diff --git a/edg/parts/JlcLed.py b/edg/parts/JlcLed.py index bc18c513d..f5d284b3b 100644 --- a/edg/parts/JlcLed.py +++ b/edg/parts/JlcLed.py @@ -4,7 +4,7 @@ from .JlcPart import JlcTableSelector -class JlcLed(TableLed, PartsTableSelectorFootprint, JlcTableSelector): +class JlcLed(PartsTableSelectorFootprint, JlcTableSelector, TableLed): PACKAGE_FOOTPRINT_MAP = { # 0201 not in parts table, LED_0201_0603Metric diff --git a/edg/parts/JlcOscillator.py b/edg/parts/JlcOscillator.py index 743bcfe8d..b60a0ac65 100644 --- a/edg/parts/JlcOscillator.py +++ b/edg/parts/JlcOscillator.py @@ -60,7 +60,7 @@ class Sg8101ce_Device(Sg8101_Base_Device): FOOTPRINT = 'Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm' # doesn't perfectly match datasheet recommended geometry -class JlcOscillator(TableOscillator, JlcTableSelector): +class JlcOscillator(JlcTableSelector, TableOscillator): SERIES_DEVICE_MAP = { 'SG-8101CG': Sg8101cg_Device, 'SG-8101CE': Sg8101ce_Device, diff --git a/edg/parts/JlcPptcFuse.py b/edg/parts/JlcPptcFuse.py index 3fa3baac8..bc4d3a8a5 100644 --- a/edg/parts/JlcPptcFuse.py +++ b/edg/parts/JlcPptcFuse.py @@ -5,7 +5,7 @@ from .JlcPart import DescriptionParser, JlcTableSelector -class JlcPptcFuse(TableFuse, PptcFuse, PartsTableSelectorFootprint, JlcTableSelector): +class JlcPptcFuse(PartsTableSelectorFootprint, JlcTableSelector, TableFuse, PptcFuse): PACKAGE_FOOTPRINT_MAP = { '0402': 'Resistor_SMD:R_0402_1005Metric', '0603': 'Resistor_SMD:R_0603_1608Metric', diff --git a/edg/parts/JlcResistor.py b/edg/parts/JlcResistor.py index a3c0a5d5d..f6d4bb832 100644 --- a/edg/parts/JlcResistor.py +++ b/edg/parts/JlcResistor.py @@ -4,7 +4,7 @@ from .JlcPart import JlcTableSelector -class JlcResistor(TableResistor, PartsTableSelectorFootprint, JlcTableSelector): +class JlcResistor(PartsTableSelectorFootprint, JlcTableSelector, TableResistor): PACKAGE_FOOTPRINT_MAP = { # 0201 not in parts table, R_0201_0603Metric diff --git a/edg/parts/JlcResistorArray.py b/edg/parts/JlcResistorArray.py index b6041fe9a..86bacfc86 100644 --- a/edg/parts/JlcResistorArray.py +++ b/edg/parts/JlcResistorArray.py @@ -4,7 +4,7 @@ from .JlcPart import DescriptionParser, JlcTableSelector -class JlcResistorArray(TableResistorArray, PartsTableSelectorFootprint, JlcTableSelector): +class JlcResistorArray(PartsTableSelectorFootprint, JlcTableSelector, TableResistorArray): SERIES_PACKAGE_FOOTPRINT_MAP = { ('4D03', '0603_x4'): 'Resistor_SMD:R_Array_Concave_4x0603', # 1206 overall size ('4D03', 'RES-ARRAY-SMD'): 'Resistor_SMD:R_Array_Concave_4x0603', # same as above, but inconsistent footprint field diff --git a/edg/parts/Joystick_Xbox.py b/edg/parts/Joystick_Xbox.py index 1134f62dd..eb623cf20 100644 --- a/edg/parts/Joystick_Xbox.py +++ b/edg/parts/Joystick_Xbox.py @@ -1,7 +1,7 @@ from ..abstract_parts import * -class XboxElite2Joystick(FootprintBlock): +class XboxElite2Joystick(FootprintBlock, HumanInterface): """Joystick assembly (X/Y analog axes + switch) from the XBox Elite 2 controller. Proper polarity for compatibility with hall effect sensors.""" def __init__(self): diff --git a/edg/parts/LedDriver_Al8861.py b/edg/parts/LedDriver_Al8861.py index 354387a74..eaf271d47 100644 --- a/edg/parts/LedDriver_Al8861.py +++ b/edg/parts/LedDriver_Al8861.py @@ -64,6 +64,7 @@ def __init__(self, diode_voltage_drop: RangeLike = Range.all()): def generate(self): super().contents() + # TODO replace with BuckConverterPowerPath, though the 33uH minimum inductance is very high self.require(self.max_current.within((0, 1.5)*Amp)) # for MSOP and SOT89 packages isense_ref = Range(0.096, 0.104) diff --git a/edg/parts/MagneticSensor_A1304.py b/edg/parts/MagneticSensor_A1304.py index 8ce65205b..5eee00965 100644 --- a/edg/parts/MagneticSensor_A1304.py +++ b/edg/parts/MagneticSensor_A1304.py @@ -31,7 +31,7 @@ def contents(self): self.assign(self.actual_basic_part, False) -class A1304(MagneticSwitch, Block): +class A1304(Magnetometer, Block): """Linear hall-effect sensor with analog output, sometimes used in game controllers as trigger detectors. Typ 4 mV / Gauss with full scale range of +/-375 Gauss.""" def __init__(self): diff --git a/edg/parts/MagneticSwitch_Ah1806.py b/edg/parts/MagneticSwitch_Ah1806.py index 0f4bebb1f..69fad3f6d 100644 --- a/edg/parts/MagneticSwitch_Ah1806.py +++ b/edg/parts/MagneticSwitch_Ah1806.py @@ -19,9 +19,9 @@ def contents(self): self.footprint( 'U', 'Package_TO_SOT_SMD:SOT-23', { - '1': self.vdd, - '2': self.gnd, - '3': self.output, + '1': self.vdd, # note, kicad pin numbers differs from datasheet pin numbers + '3': self.gnd, + '2': self.output, }, mfr="Diodes Incorporated", part='AH1806-W-7', datasheet='https://www.diodes.com/assets/Datasheets/AH1806.pdf') diff --git a/edg/parts/Microcontroller_Esp32c3.py b/edg/parts/Microcontroller_Esp32c3.py index 2307d0c12..df17f9542 100644 --- a/edg/parts/Microcontroller_Esp32c3.py +++ b/edg/parts/Microcontroller_Esp32c3.py @@ -60,7 +60,7 @@ def _io_pinmap(self) -> PinMapUtil: # PinResource('GPIO2', {'GPIO2': dio_model, 'ADC1_CH2': adc_model}), # boot pin, non-allocatable PinResource('GPIO3', {'GPIO3': dio_model, 'ADC1_CH3': adc_model}), PinResource('MTMS', {'GPIO4': dio_model, 'ADC1_CH4': adc_model}), - PinResource('MTDI', {'GPIO5': dio_model, 'ADC2_CH0': adc_model}), + PinResource('MTDI', {'GPIO5': dio_model}), # also ADC2_CH0, but unusable with WiFi PinResource('MTCK', {'GPIO6': dio_model}), PinResource('MTDO', {'GPIO7': dio_model}), # PinResource('GPIO8', {'GPIO8': dio_model}), # boot pin, non-allocatable diff --git a/edg/parts/PassiveConnector_Header.py b/edg/parts/PassiveConnector_Header.py index 202c1fca4..c4db3c172 100644 --- a/edg/parts/PassiveConnector_Header.py +++ b/edg/parts/PassiveConnector_Header.py @@ -121,7 +121,7 @@ def part_footprint_mfr_name(self, length: int) -> Tuple[str, str, str]: "JST", f"B{length}B-PH-SM4-TB") -class JstPhSmVerticalJlc(JstPh, JlcPart): +class JstPhSmVerticalJlc(JlcPart, JstPhSmVertical): """JST PH connector in SMD, with JLC part numbers for what parts are stocked (JST or clones, since JLC's inventory of PH SMD connectors is pretty spotty).""" PART_NUMBERS = { # in order of decreasing stock, on 2022-08-23 diff --git a/edg/parts/Rf_Pn7160.py b/edg/parts/Rf_Pn7160.py index a2e79f07e..6f1e2980e 100644 --- a/edg/parts/Rf_Pn7160.py +++ b/edg/parts/Rf_Pn7160.py @@ -11,7 +11,7 @@ # TODO: maybe have a RfPort / DifferentialRfPort bidirectional type modeling impedances # TODO: use actual component values in calculations, to account for tolerance stackup -class NfcAntenna(FootprintBlock, GeneratorBlock): +class NfcAntenna(FootprintBlock, GeneratorBlock, Interface): """NFC antenna, also calculates the complex impedance from series-LRC parameters. In this model, the L and R are in series, and the C is in parallel with the LR stack. As in https://www.nxp.com/docs/en/application-note/AN13219.pdf @@ -54,7 +54,7 @@ def generate(self): self.footprint('ANT', self.ant_footprint, {'1': self.ant1, '2': self.ant2}) -class NfcAntennaDampening(GeneratorBlock): +class NfcAntennaDampening(InternalSubcircuit, GeneratorBlock): """Differential antenna dampening circuit, two inline resistors to achieve some target Q """ @classmethod @@ -94,7 +94,7 @@ def generate(self): self.assign(self.z_imag, self.ant_x) -class DifferentialLcLowpassFilter(GeneratorBlock): +class DifferentialLcLowpassFilter(GeneratorBlock, RfFilter): """Differential LC lowpass filter, commonly used as an EMC filter in the NFC analog frontend Input resistance is used to calculate the output impedance""" @classmethod @@ -145,7 +145,7 @@ def generate(self): self.assign(self.z_imag, impedance.imag) -class DifferentialLLowPassFilter(GeneratorBlock): +class DifferentialLLowPassFilter(GeneratorBlock, RfFilter): @classmethod def _calculate_se_values(cls, freq: float, z1: complex, z2: complex) -> Tuple[float, float]: # calculate single-ended values from single-ended filter @@ -191,7 +191,7 @@ def generate(self): self.connect(self.cp1.neg.adapt_to(Ground()), self.cp2.neg.adapt_to(Ground()), self.gnd) -class Pn7160RxFilter(Block): +class Pn7160RxFilter(InternalSubcircuit, Block): @init_in_parent def __init__(self, resistance: RangeLike, capacitance: RangeLike, voltage: RangeLike): super().__init__() @@ -219,7 +219,7 @@ def contents(self): self.connect(self.crx2.neg, self.out2) -class Pn7160_Device(FootprintBlock, JlcPart): +class Pn7160_Device(InternalSubcircuit, FootprintBlock, JlcPart): def __init__(self) -> None: super().__init__() self.vss = self.Port(Ground(), [Common]) diff --git a/edg/parts/Rf_Sx1262.py b/edg/parts/Rf_Sx1262.py index 665b3de1a..7b2c903a5 100644 --- a/edg/parts/Rf_Sx1262.py +++ b/edg/parts/Rf_Sx1262.py @@ -139,7 +139,7 @@ def generate(self) -> None: self.connect(self.gnd, self.c_p.neg.adapt_to(Ground())) -class Sx1262_Device(FootprintBlock, JlcPart): +class Sx1262_Device(InternalSubcircuit, FootprintBlock, JlcPart): def __init__(self) -> None: super().__init__() self.gnd = self.Port(Ground(), [Common]) diff --git a/edg/parts/StepperDriver_A4988.py b/edg/parts/StepperDriver_A4988.py index 716cd4b15..0ba7e843a 100644 --- a/edg/parts/StepperDriver_A4988.py +++ b/edg/parts/StepperDriver_A4988.py @@ -205,7 +205,7 @@ def generate(self) -> None: self.connect(self.pwr_logic.as_digital_source(), self.ic.sleep) -class PololuA4988(WrapperFootprintBlock, GeneratorBlock): +class PololuA4988(BrushedMotorDriver, WrapperFootprintBlock, GeneratorBlock): """Pololu breakout board for the A4988 stepper driver. Adjustable current limit with onboard trimpot.""" @init_in_parent def __init__(self, step_resolution: IntLike = 16): diff --git a/examples/CanAdapter/CanAdapter.net b/examples/CanAdapter/CanAdapter.net index da5cdbe39..24b657ac5 100644 --- a/examples/CanAdapter/CanAdapter.net +++ b/examples/CanAdapter/CanAdapter.net @@ -441,7 +441,7 @@ (node (ref OU3) (pin 14)) (node (ref OD4) (pin 2))) (net (code 12) (name "Ovobd_sense.output") - (node (ref OU3) (pin 4)) + (node (ref OU3) (pin 3)) (node (ref OR8) (pin 2)) (node (ref OR9) (pin 1))) (net (code 13) (name "Oreg_3v3.fb.output") diff --git a/examples/CanAdapter/CanAdapter.svgpcb.js b/examples/CanAdapter/CanAdapter.svgpcb.js index 314979ea8..28bcc8e50 100644 --- a/examples/CanAdapter/CanAdapter.svgpcb.js +++ b/examples/CanAdapter/CanAdapter.svgpcb.js @@ -168,7 +168,7 @@ board.setNetlist([ {name: "Omcu.program_boot_node", pads: [["OR5", "2"], ["OU3", "8"], ["OJ1", "2"]]}, {name: "Oledg.signal", pads: [["OU3", "13"], ["OD3", "2"]]}, {name: "Oledw.signal", pads: [["OU3", "14"], ["OD4", "2"]]}, - {name: "Ovobd_sense.output", pads: [["OU3", "4"], ["OR8", "2"], ["OR9", "1"]]}, + {name: "Ovobd_sense.output", pads: [["OU3", "3"], ["OR8", "2"], ["OR9", "1"]]}, {name: "Oreg_3v3.fb.output", pads: [["OU2", "4"], ["OR1", "2"], ["OR2", "1"]]}, {name: "Oreg_3v3.boot_cap.neg", pads: [["OC2", "2"], ["OU2", "2"], ["OL1", "1"]]}, {name: "Oreg_3v3.boot_cap.pos", pads: [["OC2", "1"], ["OU2", "6"]]}, diff --git a/examples/IotCurtainCrawler/IotCurtainCrawler.net b/examples/IotCurtainCrawler/IotCurtainCrawler.net index 648984ec8..b08cc1caa 100644 --- a/examples/IotCurtainCrawler/IotCurtainCrawler.net +++ b/examples/IotCurtainCrawler/IotCurtainCrawler.net @@ -613,8 +613,8 @@ (node (ref RD1) (pin 2)) (node (ref RU2) (pin 9)) (node (ref RU2) (pin 19)) - (node (ref RU3) (pin 2)) - (node (ref RU4) (pin 2)) + (node (ref RU3) (pin 3)) + (node (ref RU4) (pin 3)) (node (ref RU5) (pin 2)) (node (ref RU5) (pin 3)) (node (ref RSW1) (pin 2)) @@ -683,14 +683,14 @@ (node (ref RU2) (pin 8)) (node (ref RJ3) (pin 2))) (net (code 7) (name "Rvin_sense.output") - (node (ref RU2) (pin 4)) + (node (ref RU2) (pin 17)) (node (ref RR6) (pin 2)) (node (ref RR7) (pin 1))) (net (code 8) (name "Renca.out") - (node (ref RU3) (pin 3)) + (node (ref RU3) (pin 2)) (node (ref RU2) (pin 13))) (net (code 9) (name "Rencb.out") - (node (ref RU4) (pin 3)) + (node (ref RU4) (pin 2)) (node (ref RU2) (pin 10))) (net (code 10) (name "Ri2c_chain_0.scl") (node (ref RU2) (pin 6)) diff --git a/examples/IotCurtainCrawler/IotCurtainCrawler.svgpcb.js b/examples/IotCurtainCrawler/IotCurtainCrawler.svgpcb.js index 1083c21a4..02cba817d 100644 --- a/examples/IotCurtainCrawler/IotCurtainCrawler.svgpcb.js +++ b/examples/IotCurtainCrawler/IotCurtainCrawler.svgpcb.js @@ -253,14 +253,14 @@ const RR11 = board.add(R_1206_3216Metric, { board.setNetlist([ {name: "Rvin_raw", pads: [["RJ1", "2"], ["RJ2", "2"], ["RF1", "1"]]}, - {name: "Rgnd", pads: [["RJ1", "1"], ["RJ2", "1"], ["RTP1", "1"], ["RU1", "1"], ["RD1", "2"], ["RU2", "9"], ["RU2", "19"], ["RU3", "2"], ["RU4", "2"], ["RU5", "2"], ["RU5", "3"], ["RSW1", "2"], ["RJ4", "1"], ["RU6", "1"], ["RU6", "9"], ["RR7", "2"], ["RC12", "2"], ["RC1", "2"], ["RC6", "2"], ["RC7", "2"], ["RJ3", "5"], ["RC9", "2"], ["RC10", "2"], ["RC11", "2"], ["RC13", "2"], ["RC14", "2"], ["RR2", "2"], ["RC8", "2"], ["RR11", "1"], ["RC5", "2"], ["RC3", "2"], ["RC4", "2"]]}, + {name: "Rgnd", pads: [["RJ1", "1"], ["RJ2", "1"], ["RTP1", "1"], ["RU1", "1"], ["RD1", "2"], ["RU2", "9"], ["RU2", "19"], ["RU3", "3"], ["RU4", "3"], ["RU5", "2"], ["RU5", "3"], ["RSW1", "2"], ["RJ4", "1"], ["RU6", "1"], ["RU6", "9"], ["RR7", "2"], ["RC12", "2"], ["RC1", "2"], ["RC6", "2"], ["RC7", "2"], ["RJ3", "5"], ["RC9", "2"], ["RC10", "2"], ["RC11", "2"], ["RC13", "2"], ["RC14", "2"], ["RR2", "2"], ["RC8", "2"], ["RR11", "1"], ["RC5", "2"], ["RC3", "2"], ["RC4", "2"]]}, {name: "Rvin", pads: [["RFB1", "2"], ["RTP2", "1"], ["RU1", "3"], ["RU6", "5"], ["RR6", "1"], ["RR3", "1"], ["RC1", "1"], ["RC13", "1"], ["RC14", "1"], ["RC3", "1"], ["RC4", "1"]]}, {name: "Rv3v3", pads: [["RU6", "4"], ["RTP3", "1"], ["RD1", "1"], ["RU2", "1"], ["RD2", "2"], ["RU3", "1"], ["RU4", "1"], ["RU5", "1"], ["RJ4", "2"], ["RR1", "1"], ["RU2", "7"], ["RU2", "16"], ["RR10", "1"], ["RC6", "1"], ["RC7", "1"], ["RJ3", "1"], ["RC9", "1"], ["RC10", "1"], ["RR8", "1"], ["RR9", "1"], ["RC11", "1"], ["RR4", "1"], ["RL1", "2"], ["RC5", "1"]]}, {name: "Rfuse.pwr_out", pads: [["RF1", "2"], ["RFB1", "1"]]}, {name: "Rmcu.program_boot_node", pads: [["RR5", "2"], ["RU2", "8"], ["RJ3", "2"]]}, - {name: "Rvin_sense.output", pads: [["RU2", "4"], ["RR6", "2"], ["RR7", "1"]]}, - {name: "Renca.out", pads: [["RU3", "3"], ["RU2", "13"]]}, - {name: "Rencb.out", pads: [["RU4", "3"], ["RU2", "10"]]}, + {name: "Rvin_sense.output", pads: [["RU2", "17"], ["RR6", "2"], ["RR7", "1"]]}, + {name: "Renca.out", pads: [["RU3", "2"], ["RU2", "13"]]}, + {name: "Rencb.out", pads: [["RU4", "2"], ["RU2", "10"]]}, {name: "Ri2c_chain_0.scl", pads: [["RU2", "6"], ["RU5", "6"], ["RR8", "2"], ["RTP4", "1"], ["RJ4", "4"]]}, {name: "Ri2c_chain_0.sda", pads: [["RU2", "5"], ["RU5", "4"], ["RJ4", "3"], ["RR9", "2"], ["RTP5", "1"]]}, {name: "Rsw.out", pads: [["RU2", "3"], ["RSW1", "1"]]}, diff --git a/examples/IotRollerBlinds/IotRollerBlinds.net b/examples/IotRollerBlinds/IotRollerBlinds.net index fe6259fb4..8ec8e1762 100644 --- a/examples/IotRollerBlinds/IotRollerBlinds.net +++ b/examples/IotRollerBlinds/IotRollerBlinds.net @@ -537,7 +537,7 @@ (node (ref BU2) (pin 8)) (node (ref BJ4) (pin 2))) (net (code 7) (name "Bvin_sense.output") - (node (ref BU2) (pin 4)) + (node (ref BU2) (pin 3)) (node (ref BR6) (pin 2)) (node (ref BR7) (pin 1))) (net (code 8) (name "Bconn.enca") diff --git a/examples/IotRollerBlinds/IotRollerBlinds.svgpcb.js b/examples/IotRollerBlinds/IotRollerBlinds.svgpcb.js index 0803524af..1fea93acf 100644 --- a/examples/IotRollerBlinds/IotRollerBlinds.svgpcb.js +++ b/examples/IotRollerBlinds/IotRollerBlinds.svgpcb.js @@ -203,7 +203,7 @@ board.setNetlist([ {name: "Bv3v3", pads: [["BU3", "4"], ["BTP3", "1"], ["BD1", "1"], ["BU2", "1"], ["BD2", "2"], ["BJ5", "2"], ["BR1", "1"], ["BU2", "7"], ["BU2", "16"], ["BC6", "1"], ["BC7", "1"], ["BJ4", "1"], ["BR8", "1"], ["BR9", "1"], ["BR4", "1"], ["BL1", "2"], ["BC5", "1"]]}, {name: "Bfuse.pwr_out", pads: [["BF1", "2"], ["BFB1", "1"]]}, {name: "Bmcu.program_boot_node", pads: [["BR5", "2"], ["BU2", "8"], ["BJ4", "2"]]}, - {name: "Bvin_sense.output", pads: [["BU2", "4"], ["BR6", "2"], ["BR7", "1"]]}, + {name: "Bvin_sense.output", pads: [["BU2", "3"], ["BR6", "2"], ["BR7", "1"]]}, {name: "Bconn.enca", pads: [["BU2", "13"], ["BJ3", "2"]]}, {name: "Bconn.encb", pads: [["BU2", "10"], ["BJ3", "3"]]}, {name: "Bqwiic_pull.i2c.scl", pads: [["BU2", "5"], ["BR8", "2"], ["BJ5", "4"]]}, diff --git a/examples/test_can_adapter.py b/examples/test_can_adapter.py index db2b37e34..e1d7c525a 100644 --- a/examples/test_can_adapter.py +++ b/examples/test_can_adapter.py @@ -80,7 +80,7 @@ def refinements(self) -> Refinements: 'ledw=14', 'can.txd=6', 'can.rxd=5', - 'vobd_sense=4', + 'vobd_sense=3', # 4 as sent to fabrication before ADC2 removed from model, blue-wire to 3 ]), (['mcu', 'programming'], 'uart-auto'), diff --git a/examples/test_datalogger.py b/examples/test_datalogger.py index 926d87495..2c42d1854 100644 --- a/examples/test_datalogger.py +++ b/examples/test_datalogger.py @@ -175,7 +175,7 @@ def refinements(self) -> Refinements: (['buffer', 'fet', 'footprint_spec'], 'Package_TO_SOT_SMD:SOT-223-3_TabPin2'), ], class_refinements=[ - (PptcFuse, CanFuse) + (Fuse, CanFuse) ], ) diff --git a/examples/test_high_switch.py b/examples/test_high_switch.py index 89df26b32..4b0c644d8 100644 --- a/examples/test_high_switch.py +++ b/examples/test_high_switch.py @@ -28,7 +28,7 @@ def contents(self): self.conn = self.Block(CalSolCanConnector()) self.connect(self.can, self.conn.differential) - self.can_fuse = self.Block(SeriesPowerPptcFuse(150 * mAmp(tol=0.1))) + self.can_fuse = self.Block(SeriesPowerFuse(150 * mAmp(tol=0.1))) self.connect(self.conn.pwr, self.can_fuse.pwr_in) with self.implicit_connect( @@ -352,7 +352,7 @@ def refinements(self) -> Refinements: (['light[5]', 'drv[1]', 'drv', 'footprint_spec'], ParamValue(['light[0]', 'drv[0]', 'drv', 'footprint_spec'])), ], class_refinements=[ - (PptcFuse, CanFuse) + (Fuse, CanFuse) ], ) diff --git a/examples/test_iot_blinds.py b/examples/test_iot_blinds.py index bd155b8d9..774c94a6b 100644 --- a/examples/test_iot_blinds.py +++ b/examples/test_iot_blinds.py @@ -135,7 +135,7 @@ def refinements(self) -> Refinements: (['refdes_prefix'], 'B'), # unique refdes for panelization (['mcu', 'pin_assigns'], [ 'led=_GPIO9_STRAP', # force using the strapping / boot mode pin - 'vin_sense=4', + 'vin_sense=3', # 4 as sent to fabrication before ADC2 removed from model, blue-wire to 3 'motor1=15', 'motor2=14', 'enca=13', @@ -268,7 +268,7 @@ def refinements(self) -> Refinements: (['refdes_prefix'], 'R'), # unique refdes for panelization (['mcu', 'pin_assigns'], [ 'led=_GPIO9_STRAP', # force using the strapping / boot mode pin - 'vin_sense=4', + 'vin_sense=17', # 4 as sent to fabrication before ADC2 removed from model, blue-wire to 17 'motor1=14', 'motor2=15', 'enca=13', diff --git a/examples/test_pcbbot.py b/examples/test_pcbbot.py index 293ebf7c0..ca17cf28a 100644 --- a/examples/test_pcbbot.py +++ b/examples/test_pcbbot.py @@ -47,7 +47,7 @@ def contents(self) -> None: ) as imp: (self.fuse, self.gate, self.prot_batt, self.tp_batt), _ = self.chain( self.batt.pwr, - imp.Block(SeriesPowerPptcFuse((2, 4)*Amp)), + imp.Block(SeriesPowerFuse((2, 4)*Amp)), imp.Block(SoftPowerSwitch()), imp.Block(ProtectionZenerDiode(voltage=(4.5, 6.0)*Volt)), self.Block(VoltageTestPoint())) @@ -174,7 +174,7 @@ def refinements(self) -> Refinements: (['reg_1v2'], Xc6206p), (['rgb', 'package'], ThtRgbLed), (['npx_key'], Sk6812Mini_E), - + (['fuse', 'fuse'], PptcFuse), ], instance_values=[ (['mcu', 'pin_assigns'], [