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Unify Port and Bundle by merging Bundle functionality into Ports (#453)
On the path to compositional passive. Also simplifies a bunch of code. Refactors the libraries to use Port instead of Bundle, but retains Bundle with a deprecation warning. Changes Bundle.with_elt_initializers to be private. It is an API with only one consumer in the pinmap util and a better solution will need to be found for it. Updates the proto version.
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‎compiler/src/main/scala/edg/ElemBuilder.scala‎

Lines changed: 2 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -219,33 +219,18 @@ object ElemBuilder {
219219
)
220220

221221
def Port(
222-
selfClass: String,
223-
params: SeqMap[String, init.ValInit] = SeqMap(),
224-
constraints: SeqMap[String, expr.ValueExpr] = SeqMap(),
225-
): elem.PortLike = elem.PortLike(`is` =
226-
elem.PortLike.Is.Port(elem.Port(
227-
params = params.toPb,
228-
constraints = constraints.toPb,
229-
selfClass = selfClass match {
230-
case "" => None
231-
case selfClass => Some(LibraryPath(selfClass))
232-
}
233-
))
234-
)
235-
236-
def Bundle(
237222
selfClass: String,
238223
params: SeqMap[String, init.ValInit] = SeqMap(),
239224
ports: SeqMap[String, elem.PortLike] = SeqMap(),
240225
constraints: SeqMap[String, expr.ValueExpr] = SeqMap(),
241226
): elem.PortLike = elem.PortLike(`is` =
242-
elem.PortLike.Is.Bundle(elem.Bundle(
227+
elem.PortLike.Is.Port(elem.Port(
243228
params = params.toPb,
244229
ports = ports.toPb,
245230
constraints = constraints.toPb,
246231
selfClass = selfClass match {
247232
case "" => None
248-
case superclass => Some(LibraryPath(superclass))
233+
case selfClass => Some(LibraryPath(selfClass))
249234
}
250235
))
251236
)
@@ -306,10 +291,6 @@ object ElemBuilder {
306291
_.`is` match {
307292
case elem.PortLike.Is.Port(port) =>
308293
port.getSelfClass.toFullString -> schema.Library.NS.Val(`type` = schema.Library.NS.Val.Type.Port(port))
309-
case elem.PortLike.Is.Bundle(bundle) =>
310-
bundle.getSelfClass.toFullString -> schema.Library.NS.Val(`type` =
311-
schema.Library.NS.Val.Type.Bundle(bundle)
312-
)
313294
case port => throw new NotImplementedError(s"Unknown PortLike in library $port")
314295
}
315296
}.toMap

‎compiler/src/main/scala/edg/Wrappers.scala‎

Lines changed: 0 additions & 9 deletions
This file was deleted.

‎compiler/src/main/scala/edg/compiler/Compiler.scala‎

Lines changed: 9 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -117,7 +117,7 @@ class AssignNamer() {
117117
}
118118

119119
object Compiler {
120-
final val kExpectedProtoVersion = 7
120+
final val kExpectedProtoVersion = 8
121121
}
122122

123123
/** Compiler for a particular design, with an associated library to elaborate references from.
@@ -289,7 +289,7 @@ class Compiler private (
289289

290290
// Add sub-ports to the elaboration dependency graph, as appropriate
291291
toLinkPort match {
292-
case toLinkPort: wir.Bundle =>
292+
case toLinkPort: wir.Port =>
293293
for (portName <- toLinkPort.getPorts.keys) {
294294
elaboratePending.addNode(
295295
ElaborateRecord.Connect(
@@ -320,7 +320,7 @@ class Compiler private (
320320
// Returns the deepest applicable postfix, starting from a port
321321
def resolveRecursive(portPath: DesignPath, port: wir.PortLike, postfix: Seq[String]): Seq[String] = {
322322
port match {
323-
case _: wir.Port | _: wir.Bundle | _: wir.PortLibrary => // don't recurse into these
323+
case _: wir.Port | _: wir.PortLibrary => // don't recurse into these
324324
// note that libraries in arrays may not yet have been elaborated
325325
Seq()
326326
case port: wir.PortArray =>
@@ -416,12 +416,11 @@ class Compiler private (
416416
val portPb = library.getPort(libraryPath) match {
417417
case Errorable.Success(portPb) => portPb
418418
case Errorable.Error(err) =>
419-
import edg.IrPort
420419
import edgir.elem.elem
421420
errors += CompilerError.LibraryError(path, libraryPath, err)
422-
IrPort.Port(elem.Port())
421+
elem.Port()
423422
}
424-
val newPort = wir.PortLike.fromIrPort(portPb)
423+
val newPort = new wir.Port(portPb)
425424
container.elaborate(path.lastString, newPort)
426425
newPort
427426
case port: wir.PortArray => port // no instantiation needed
@@ -434,9 +433,6 @@ class Compiler private (
434433
case port: wir.Port =>
435434
constProp.addAssignValue(path.asIndirect + IndirectStep.Name, TextValue(path.toString), containerPath, "name")
436435
processParamDeclarations(path, port)
437-
case port: wir.Bundle =>
438-
constProp.addAssignValue(path.asIndirect + IndirectStep.Name, TextValue(path.toString), containerPath, "name")
439-
processParamDeclarations(path, port)
440436
for ((childPortName, childPort) <- port.getPorts) {
441437
elaboratePort(path + childPortName, containerPath, port, childPort)
442438
}
@@ -1135,7 +1131,7 @@ class Compiler private (
11351131

11361132
case connects => throw new IllegalArgumentException(s"invalid connections to array $connects")
11371133
}
1138-
case _ => // non-array, eg Port or Bundle
1134+
case _ => // non-array, eg Port
11391135
connectedConstraints.connectionsByLinkPort(portPostfix, false) match {
11401136
case PortConnections.ArrayConnect(constrName, constr) => constr.expr match {
11411137
case expr.ValueExpr.Expr.ConnectedArray(connected) =>
@@ -1196,7 +1192,7 @@ class Compiler private (
11961192

11971193
// TODO refactor this out, ConnectedLink needs to be centralized
11981194
def setConnectedLink(portPath: DesignPath, port: PortLike): Unit = (port: @unchecked) match {
1199-
case _: wir.Port | _: wir.Bundle =>
1195+
case _: wir.Port =>
12001196
constProp.setConnectedLink(path, portPath)
12011197
case port: wir.PortArray =>
12021198
port.getPorts.foreach { case (subPortName, subPort) =>
@@ -1404,7 +1400,7 @@ class Compiler private (
14041400
link.getModelPorts(portPostfix(1)) match {
14051401
case _: wir.PortArray =>
14061402
(portPostfix.init, (constrName, constr)) // drop the array index
1407-
case _ => // non-array like Port and Bundle
1403+
case _ => // non-array like Port
14081404
(portPostfix, (constrName, constr))
14091405
}
14101406
}.groupBy(_._1).foreach { case (portPostfix, elts) => // actually resolve (delayed if array)
@@ -1420,7 +1416,7 @@ class Compiler private (
14201416
ElaborateRecord.ElaboratePortArray(path ++ portPostfix)
14211417
)
14221418
)
1423-
case _ => // non-array like Port and Bundle
1419+
case _ => // non-array like Port
14241420
val Seq((constrName, constr)) = constrNamesConstrs // can only be one element
14251421
resolvePortConnectivity(path, portPostfix, Some(constrName, constr))
14261422
}

‎compiler/src/main/scala/edg/compiler/DesignAssertionCheck.scala‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -33,9 +33,8 @@ class DesignAssertionCheck(compiler: Compiler)
3333
}
3434
}
3535

36-
override def mapPort(path: DesignPath, port: elem.Port): Unit = {}
36+
override def mapPort(path: DesignPath, port: elem.Port, ports: SeqMap[String, Unit]): Unit = {}
3737
override def mapPortArray(path: DesignPath, port: elem.PortArray, ports: SeqMap[String, Unit]): Unit = {}
38-
override def mapBundle(path: DesignPath, port: elem.Bundle, ports: SeqMap[String, Unit]): Unit = {}
3938
override def mapPortLibrary(path: DesignPath, port: ref.LibraryPath): Unit = {}
4039

4140
override def mapBlock(

‎compiler/src/main/scala/edg/compiler/DesignMap.scala‎

Lines changed: 5 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -16,15 +16,12 @@ trait DesignMap[PortType, BlockType, LinkType] {
1616

1717
// These methods handle how nodes are processed must be overridden by the user where appropriate
1818
// (left default, they will exception out, which may be desired behavior on unexpected node types)
19-
def mapPort(path: DesignPath, port: elem.Port): PortType = {
19+
def mapPort(path: DesignPath, port: elem.Port, ports: SeqMap[String, PortType]): PortType = {
2020
throw new NotImplementedError(s"Undefined mapPort at $path")
2121
}
2222
def mapPortArray(path: DesignPath, port: elem.PortArray, ports: SeqMap[String, PortType]): PortType = {
2323
throw new NotImplementedError(s"Undefined mapPortArray at $path")
2424
}
25-
def mapBundle(path: DesignPath, port: elem.Bundle, ports: SeqMap[String, PortType]): PortType = {
26-
throw new NotImplementedError(s"Undefined mapBundle at $path")
27-
}
2825
def mapPortLibrary(path: DesignPath, port: ref.LibraryPath): PortType = {
2926
throw new NotImplementedError(s"Undefined mapPortLibrary at $path")
3027
}
@@ -64,11 +61,11 @@ trait DesignMap[PortType, BlockType, LinkType] {
6461

6562
// These methods provide default recursive processing functionality for child sub-tree elements,
6663
// and may be (but are not required to be) optionally overridden
67-
def wrapBundle(path: DesignPath, port: elem.Bundle): PortType = {
64+
def wrapPort(path: DesignPath, port: elem.Port): PortType = {
6865
val ports = port.ports.toSeqMap.map { case (name, elt) =>
6966
name -> wrapPortlike(path + name, elt)
7067
}
71-
mapBundle(path, port, ports)
68+
mapPort(path, port, ports)
7269
}
7370

7471
def wrapPortArray(path: DesignPath, port: elem.PortArray): PortType = {
@@ -80,8 +77,7 @@ trait DesignMap[PortType, BlockType, LinkType] {
8077

8178
def wrapPortlike(path: DesignPath, portLike: elem.PortLike): PortType = {
8279
portLike.is match {
83-
case elem.PortLike.Is.Port(port) => mapPort(path, port)
84-
case elem.PortLike.Is.Bundle(port) => wrapBundle(path, port)
80+
case elem.PortLike.Is.Port(port) => wrapPort(path, port)
8581
case elem.PortLike.Is.Array(port) => wrapPortArray(path, port)
8682
case elem.PortLike.Is.LibElem(port) => mapPortLibrary(path, port)
8783
case block => throw new NotImplementedError(s"Unknown BlockLike type at $path: $block")
@@ -150,9 +146,8 @@ trait DesignBlockMap[BlockType] extends DesignMap[Unit, BlockType, Unit] {
150146

151147
// These methods handle how nodes are processed must be overridden by the user where appropriate
152148
// (left default, they will exception out, which may be desired behavior on unexpected node types)
153-
final override def mapPort(path: DesignPath, port: elem.Port): Unit = {}
149+
final override def mapPort(path: DesignPath, port: elem.Port, ports: SeqMap[String, Unit]): Unit = {}
154150
final override def mapPortArray(path: DesignPath, port: elem.PortArray, ports: SeqMap[String, Unit]): Unit = {}
155-
final override def mapBundle(path: DesignPath, port: elem.Bundle, ports: SeqMap[String, Unit]): Unit = {}
156151
final override def mapPortLibrary(path: DesignPath, port: ref.LibraryPath): Unit = {}
157152

158153
final override def mapBlock(

‎compiler/src/main/scala/edg/compiler/DesignRefsValidate.scala‎

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -144,17 +144,13 @@ class DesignRefsValidate extends DesignMap[Unit, Unit, Unit] {
144144
}
145145
}
146146

147-
override def mapPort(path: DesignPath, port: elem.Port): Unit = {
147+
override def mapPort(path: DesignPath, port: elem.Port, ports: SeqMap[String, Unit]): Unit = {
148148
port.params.asPairs.foreach { case (name, _) => paramDefs.add(path + name) }
149149
portDefs.add(path)
150150
}
151151
override def mapPortArray(path: DesignPath, port: elem.PortArray, ports: SeqMap[String, Unit]): Unit = {
152152
// do nothing
153153
}
154-
override def mapBundle(path: DesignPath, port: elem.Bundle, ports: SeqMap[String, Unit]): Unit = {
155-
port.params.asPairs.foreach { case (name, _) => paramDefs.add(path + name) }
156-
portDefs.add(path)
157-
}
158154
override def mapPortLibrary(path: DesignPath, port: ref.LibraryPath): Unit = {
159155
Seq(CompilerError.LibraryElement(path, port))
160156
}

‎compiler/src/main/scala/edg/compiler/DesignStructuralValidate.scala‎

Lines changed: 6 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,12 @@ import scala.collection.SeqMap
1212
* - unelaborated library elements
1313
*/
1414
class DesignStructuralValidate extends DesignMap[Seq[CompilerError], Seq[CompilerError], Seq[CompilerError]] {
15-
override def mapPort(path: DesignPath, port: elem.Port): Seq[CompilerError] = {
16-
Seq()
15+
override def mapPort(
16+
path: DesignPath,
17+
port: elem.Port,
18+
ports: SeqMap[String, Seq[CompilerError]]
19+
): Seq[CompilerError] = {
20+
ports.values.flatten.toSeq
1721
}
1822
override def mapPortArray(
1923
path: DesignPath,
@@ -27,13 +31,6 @@ class DesignStructuralValidate extends DesignMap[Seq[CompilerError], Seq[Compile
2731
}
2832
undefinedError ++ ports.values.flatten.toSeq
2933
}
30-
override def mapBundle(
31-
path: DesignPath,
32-
port: elem.Bundle,
33-
ports: SeqMap[String, Seq[CompilerError]]
34-
): Seq[CompilerError] = {
35-
ports.values.flatten.toSeq
36-
}
3734
override def mapPortLibrary(path: DesignPath, port: ref.LibraryPath): Seq[CompilerError] = {
3835
Seq(CompilerError.LibraryElement(path, port))
3936
}

‎compiler/src/main/scala/edg/compiler/PythonInterface.scala‎

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,6 @@
11
package edg.compiler
22

33
import edg.EdgirUtils.SimpleLibraryPath
4-
import edg.IrPort
54
import edg.util.{Errorable, QueueStream, timeExec}
65
import edg.wir.{DesignPath, IndirectDesignPath, Library}
76
import edgir.elem.elem
@@ -393,9 +392,8 @@ class PythonInterfaceLibrary() extends Library {
393392
case (path, schema.Library.NS.Val.Type.HierarchyBlock(block)) => (path, block)
394393
}.toMap
395394

396-
override def allPorts: Map[ref.LibraryPath, IrPort] = elts.collect {
397-
case (path, schema.Library.NS.Val.Type.Port(port)) => (path, IrPort.Port(port))
398-
case (path, schema.Library.NS.Val.Type.Bundle(port)) => (path, IrPort.Bundle(port))
395+
override def allPorts: Map[ref.LibraryPath, elem.Port] = elts.collect {
396+
case (path, schema.Library.NS.Val.Type.Port(port)) => (path, port)
399397
}.toMap
400398

401399
override def allLinks: Map[ref.LibraryPath, elem.Link] = elts.collect {
@@ -417,10 +415,9 @@ class PythonInterfaceLibrary() extends Library {
417415
case schema.Library.NS.Val.Type.Link(member) => member
418416
}
419417
}
420-
override def getPort(path: ref.LibraryPath): Errorable[IrPort] = {
418+
override def getPort(path: ref.LibraryPath): Errorable[elem.Port] = {
421419
getLibraryPartialMapped(path, "port") {
422-
case schema.Library.NS.Val.Type.Port(member) => IrPort.Port(member)
423-
case schema.Library.NS.Val.Type.Bundle(member) => IrPort.Bundle(member)
420+
case schema.Library.NS.Val.Type.Port(member) => member
424421
}
425422
}
426423

‎compiler/src/main/scala/edg/wir/BlockConnectivityAnalysis.scala‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,6 @@ object BlockConnectivityAnalysis {
3636
def typeOfPortLike(portLike: elem.PortLike): ref.LibraryPath = portLike.is match {
3737
case elem.PortLike.Is.LibElem(lib) => lib
3838
case elem.PortLike.Is.Port(port) => port.getSelfClass
39-
case elem.PortLike.Is.Bundle(port) => port.getSelfClass
4039
case elem.PortLike.Is.Array(port) => port.getSelfClass
4140
case other => throw new IllegalArgumentException(s"Unexpected PortLike ${other.getClass}")
4241
}

‎compiler/src/main/scala/edg/wir/Library.scala‎

Lines changed: 6 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,6 @@
11
package edg.wir
22

33
import edg.EdgirUtils.SimpleLibraryPath
4-
import edg.IrPort
54
import edg.compiler.ExprValue
65
import edg.util.Errorable
76
import edg.wir.ProtoUtil.{
@@ -30,11 +29,11 @@ trait Library {
3029
// subclass relations
3130
def getBlock(path: ref.LibraryPath, ignoreRefinements: Boolean = false): Errorable[elem.HierarchyBlock]
3231
def getLink(path: ref.LibraryPath): Errorable[elem.Link]
33-
def getPort(path: ref.LibraryPath): Errorable[IrPort]
32+
def getPort(path: ref.LibraryPath): Errorable[elem.Port]
3433

3534
// Returns all elements of the specified type and their path.
3635
// If the library has a mutable backing, this may change over time.
37-
def allPorts: Map[ref.LibraryPath, IrPort]
36+
def allPorts: Map[ref.LibraryPath, elem.Port]
3837
def allBlocks: Map[ref.LibraryPath, elem.HierarchyBlock]
3938
def allLinks: Map[ref.LibraryPath, elem.Link]
4039

@@ -85,7 +84,6 @@ class EdgirLibrary(pb: schema.Library) extends Library {
8584
val libraryPath = ref.LibraryPath(target = Some(ref.LocalStep(step = ref.LocalStep.Step.Name(name))))
8685
member.`type` match {
8786
case schema.Library.NS.Val.Type.Port(_) => libraryPath -> member.`type`
88-
case schema.Library.NS.Val.Type.Bundle(_) => libraryPath -> member.`type`
8987
case schema.Library.NS.Val.Type.HierarchyBlock(_) => libraryPath -> member.`type`
9088
case schema.Library.NS.Val.Type.Link(_) => libraryPath -> member.`type`
9189
case schema.Library.NS.Val.Type.Namespace(_) =>
@@ -98,9 +96,8 @@ class EdgirLibrary(pb: schema.Library) extends Library {
9896
case (path, schema.Library.NS.Val.Type.HierarchyBlock(block)) => (path, block)
9997
}
10098

101-
override def allPorts: Map[ref.LibraryPath, IrPort] = elts.collect {
102-
case (path, schema.Library.NS.Val.Type.Port(port)) => (path, IrPort.Port(port))
103-
case (path, schema.Library.NS.Val.Type.Bundle(port)) => (path, IrPort.Bundle(port))
99+
override def allPorts: Map[ref.LibraryPath, elem.Port] = elts.collect {
100+
case (path, schema.Library.NS.Val.Type.Port(port)) => (path, port)
104101
}
105102

106103
override def allLinks: Map[ref.LibraryPath, elem.Link] = elts.collect {
@@ -121,9 +118,8 @@ class EdgirLibrary(pb: schema.Library) extends Library {
121118
case None => Errorable.Error(s"Library does not contain $path")
122119
}
123120

124-
override def getPort(path: ref.LibraryPath): Errorable[IrPort] = elts.get(path) match {
125-
case Some(schema.Library.NS.Val.Type.Port(member)) => Errorable.Success(IrPort.Port(member))
126-
case Some(schema.Library.NS.Val.Type.Bundle(member)) => Errorable.Success(IrPort.Bundle(member))
121+
override def getPort(path: ref.LibraryPath): Errorable[elem.Port] = elts.get(path) match {
122+
case Some(schema.Library.NS.Val.Type.Port(member)) => Errorable.Success(member)
127123
case Some(member) => Errorable.Error(s"Library element at $path not a port-like, got ${member.getClass}")
128124
case None => Errorable.Error(s"Library does not contain $path")
129125
}

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