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Use this import button to open the solution in Keil Studio Cloud: [](https://studio.keil.arm.com/?import=https://github.com/Arm-Examples/mlek-cmsis-pack-examples.git)
@@ -224,17 +224,18 @@ Note that most applications will redirect their standard output and error stream
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Keil Sudio Cloud has an option to open a serial connection that can be used to monitor these
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streams.
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For the Alif Semiconductor's Ensemble DevKit boards, the output over UART is not wired though any
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USB. A 1.8V FTDI USART cable is recommended to view the serial output. By default, the high
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performance core uses UART device 4, and the high efficiency core uses UART device 2. Check the
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board schematic to see which pins these modules use. For the Rev1 version of the board the pins
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are:
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For the Alif Semiconductor™ Ensemble™ AI/ML kit boards, the output over UART is wired though port
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J2 (maked PRG_USB). This port exposes two UARTs - one for SE (Secure Enclave) and the other is
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confirable to pass through either UART2 or UART4 using jumpers on J15. For the applications built,
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the high performance core uses UART4, and the high efficiency core uses UART2.
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J15 setup is shown below:
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```
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UART2 RX_B on J413 pin 13 (P3_16) ↔ FTDI TX
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UART2 TX_B on J413 pin 14 (P3_17) ↔ FTDI RX
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UART4 RX_B on J412 pin 11 (P3_1) ↔ FTDI TX
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UART4 TX_B on J412 pin 12 (P3_2) ↔ FTDI RX
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J15-1-3 & 2-4: SE UART
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J15-3-5 & 4-6: UART2
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J15-5-7 & 6-8: UART2
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J15-7-9 & 8-10: UART4
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```
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For all other targets, serial is available over USB from primary debug/connection port.
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