hal.s

;--=========================--
;|          Used Pins        |
;|                           |
;|          Data Port        |
;|           B High          |
;|          CTRL Port        |
;|          RST  PA8         |
;|          CS   PA9         |
;|          RS   PA10        |
;|          WR   PA11        |
;|          RD   PA12        |
;|           INPUT           |
;|         PA0 - PA5         |
;|                           |
;--=========================--

    AREA MYDATA, DATA, READWRITE
	; This file contains the HAL layer for the STM32F103C8T6 microcontroller.
	;GPIO
GPIOA_BASE EQU 0x40010800
GPIOB_BASE EQU 0x40010C00
GPIOC_BASE EQU 0x40011000
GPIOx_CRL_OFFSET EQU 0x00
GPIOx_CRH_OFFSET EQU 0x04
GPIOx_IDR_OFFSET EQU 0x08
GPIOx_ODR_OFFSET EQU 0x0C
GPIOx_BSRR_OFFSET EQU 0x10
GPIOx_BRR_OFFSET EQU 0x14
GPIOx_LCKR_OFFSET EQU 0x18
;AFIO
AFIO_BASE EQU 0x40010000
AFIO_EVCR_OFFSET EQU 0x00
AFIO_MAPR_OFFSET EQU 0x04
AFIO_EXTICR1_OFFSET EQU 0x08
AFIO_EXTICR2_OFFSET EQU 0x0C
AFIO_EXTICR3_OFFSET EQU 0x10
AFIO_EXTICR4_OFFSET EQU 0x14
AFIO_MAPR2_OFFSET EQU 0x1C
;EXTI
EXTI_BASE EQU 0x40010400
EXTI_IMR_OFFSET EQU 0x00
EXTI_EMR_OFFSET EQU 0x04
EXTI_RTSR_OFFSET EQU 0x08
EXTI_FTSR_OFFSET EQU 0x0C
EXTI_SWIER_OFFSET EQU 0x10
EXTI_PR_OFFSET EQU 0x14
;RCC
RCC_BASE EQU 0x40021000
RCC_CR_OFFSET EQU 0x00
RCC_CFGR_OFFSET EQU 0x04
RCC_CIR_OFFSET EQU 0x08
RCC_APB2RSTR_OFFSET EQU 0x0C
RCC_APB1RSTR_OFFSET EQU 0x10
RCC_AHBENR_OFFSET EQU 0x14
RCC_APB2ENR_OFFSET EQU 0x18
RCC_APB1ENR_OFFSET EQU 0x1C
RCC_BDCR_OFFSET EQU 0x20
RCC_CSR_OFFSET EQU 0x24
;.equ RCC_AHBSTR_OFFSET, 0x28
;.equ RCC_CFGR2_OFFSET, 0x2C
;ADC
ADC1_BASE EQU 0x40012400
ADC1_SR_OFFSET EQU 0x00
ADC1_CR1_OFFSET EQU 0x04
ADC1_CR2_OFFSET EQU 0x08
ADC1_SMPR1_OFFSET EQU 0x0C
ADC1_SMPR2_OFFSET EQU 0x10
ADC1_JOFR1_OFFSET EQU 0x14
ADC1_JOFR2_OFFSET EQU 0x18
ADC1_JOFR3_OFFSET EQU 0x1C
ADC1_JOFR4_OFFSET EQU 0x20
ADC1_HTR_OFFSET EQU 0x24
ADC1_LTR_OFFSET EQU 0x28
ADC1_SQR1_OFFSET EQU 0x2C
ADC1_SQR2_OFFSET EQU 0x30
ADC1_SQR3_OFFSET EQU 0x34
ADC1_JSQR_OFFSET EQU 0x38
ADC1_JDR1_OFFSET EQU 0x3C
ADC1_JDR2_OFFSET EQU 0x40
ADC1_JDR3_OFFSET EQU 0x44
ADC1_JDR4_OFFSET EQU 0x48
ADC1_DR_OFFSET EQU 0x4C

; ADC_CR1 bits
ADC_CR1_SCAN         EQU     (1 << 8) ; Scan mode
ADC_CR1_EOCIE        EQU     (1 << 5) ; Interrupt enable for EOC

; ADC_CR2 bits
ADC_CR2_ADON         EQU     (1 << 0)  ; A/D Converter ON / OFF
ADC_CR2_CONT         EQU     (1 << 1)  ; Continuous conversion
ADC_CR2_CAL          EQU     (1 << 2)  ; A/D Calibration
ADC_CR2_RSTCAL       EQU     (1 << 3)  ; Reset calibration
ADC_CR2_ALIGN        EQU     (1 << 11) ; Data alignment (0: right, 1: left)
ADC_CR2_SWSTART      EQU     (1 << 22) ; Start conversion of regular channels

; ADC_SR bits
ADC_SR_EOC           EQU     (1 << 1)  ; End of conversion

; ADC Channels (for PA6, PA7)
ADC_CHANNEL_8        EQU     8
ADC_CHANNEL_9        EQU     9

;RTC
RTC_BASE EQU 0x40002800
RTC_CRH_OFFSET EQU 0x00
RTC_CRL_OFFSET EQU 0x04
RTC_PRLH_OFFSET EQU 0x08
RTC_PRLL_OFFSET EQU 0x0C
RTC_DIVH_OFFSET EQU 0x10
RTC_DIVL_OFFSET EQU 0x14
RTC_CNTH_OFFSET EQU 0x18
RTC_CNTL_OFFSET EQU 0x1C
RTC_ALRH_OFFSET EQU 0x20
RTC_ALRL_OFFSET EQU 0x24
;PWR
PWR_BASE EQU 0x40007000
PWR_CR_OFFSET EQU 0x00
PWR_CSR_OFFSET EQU 0x04
;System Control Space (SCS)
SCS_BASE EQU 0xE000E000
;SysTick
SysTick_BASE EQU 0xE000E010
SysTick_CTRL_OFFSET EQU 0x00
SysTick_RELOAD_VALUE_OFFSET EQU 0x04
SysTick_CURRENT_VALUE_OFFSET EQU 0x08
SysTick_CALIB_OFFSET EQU 0x0C
;NVIC
NVIC_BASE EQU 0xE000E100
;Set Enable register , each register controls 32 interrupts
NVIC_ISER_ONE_OFFSET EQU 0x00
NVIC_ISER_TWO_OFFSET EQU 0x04
NVIC_ISER_THREE_OFFSET EQU 0x08
NVIC_ISER_FOUR_OFFSET EQU 0x0C
NVIC_ISER_FIVE_OFFSET EQU 0x10
NVIC_ISER_SIX_OFFSET EQU 0x14
NVIC_ISER_SEVEN_OFFSET EQU 0x18
NVIC_ISER_EIGHT_OFFSET EQU 0x1C
;Set Clear register
NVIC_ICER_OFFSET EQU 0x80
NVIC_ICER_ONE_OFFSET EQU 0x00
NVIC_ICER_TWO_OFFSET EQU 0x04
NVIC_ICER_THREE_OFFSET EQU 0x08
NVIC_ICER_FOUR_OFFSET EQU 0x0C
NVIC_ICER_FIVE_OFFSET EQU 0x10
NVIC_ICER_SIX_OFFSET EQU 0x14
NVIC_ICER_SEVEN_OFFSET EQU 0x18
NVIC_ICER_EIGHT_OFFSET EQU 0x1C
;Set pending register
NVIC_ISPR_OFFSET EQU 0x100
NVIC_ISPR_ONE_OFFSET EQU 0x00
NVIC_ISPR_TWO_OFFSET EQU 0x04
NVIC_ISPR_THREE_OFFSET EQU 0x08
NVIC_ISPR_FOUR_OFFSET EQU 0x0C
NVIC_ISPR_FIVE_OFFSET EQU 0x10
NVIC_ISPR_SIX_OFFSET EQU 0x14
NVIC_ISPR_SEVEN_OFFSET EQU 0x18
NVIC_ISPR_EIGHT_OFFSET EQU 0x1C
;Clear pending register
NVIC_ICPR_OFFSET EQU 0x180
NVIC_ICPR_ONE_OFFSET EQU 0x00
NVIC_ICPR_TWO_OFFSET EQU 0x04
NVIC_ICPR_THREE_OFFSET EQU 0x08
NVIC_ICPR_FOUR_OFFSET EQU 0x0C
NVIC_ICPR_FIVE_OFFSET EQU 0x10
NVIC_ICPR_SIX_OFFSET EQU 0x14
NVIC_ICPR_SEVEN_OFFSET EQU 0x18
NVIC_ICPR_EIGHT_OFFSET EQU 0x1C
;Active bit register
NVIC_IABR_OFFSET EQU 0x200
NVIC_IABR_ONE_OFFSET EQU 0x00
NVIC_IABR_TWO_OFFSET EQU 0x04
NVIC_IABR_THREE_OFFSET EQU 0x08
NVIC_IABR_FOUR_OFFSET EQU 0x0C
NVIC_IABR_FIVE_OFFSET EQU 0x10
NVIC_IABR_SIX_OFFSET EQU 0x14
NVIC_IABR_SEVEN_OFFSET EQU 0x18
NVIC_IABR_EIGHT_OFFSET EQU 0x1C
;Priority register
NVIC_IPR_OFFSET EQU 0x300 ;Check interrupt number => File: RM0008, page 204/1134
NVIC_IPR_ONE_OFFSET EQU 0x00
NVIC_IPR_TWO_OFFSET EQU 0x04
NVIC_IPR_THREE_OFFSET EQU 0x08
NVIC_IPR_FOUR_OFFSET EQU 0x0C
NVIC_IPR_FIVE_OFFSET EQU 0x10
NVIC_IPR_SIX_OFFSET EQU 0x14
NVIC_IPR_SEVEN_OFFSET EQU 0x18
NVIC_IPR_EIGHT_OFFSET EQU 0x1C

;Interrupt Control and State Register (ICSR)
NVIC_ICSR_OFFSET EQU 0xC04
;Vector table OFFSET, register (VTOR)
NVIC_VTOR_OFFSET EQU 0xC08
;Application Interrupt and Reset Control Register (AIRCR)
NVIC_AIRCR_OFFSET EQU 0xC0C
		; END HAL LAYER
; TFT PIN DEFINITIONS
TFT_RST         EQU     (1 << 8) ; Reset pin (PA0)
TFT_CS          EQU     (1 << 9) ; Chip select pin (PA1)
TFT_RS          EQU     (1 << 10) ; Data/command select pin (PA2)
TFT_WR          EQU     (1 << 11) ; Write pin (PA3)
TFT_RD          EQU     (1 << 12) ; Read pin (PA5)
	
	END