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Add SCB SFSR/SFAR bit field definitions and deprecate SAU duplicates (#278)
## Problem SFSR and SFAR registers were incorrectly duplicated in both SCB and SAU structures. Per ARM reference manuals, these belong to SCB at offset 0x0E4/0x0E8, not SAU. ## Changes ### Added SCB bit field definitions - `SCB_SFSR_LSERR`, `SCB_SFSR_SFARVALID`, `SCB_SFSR_LSPERR`, `SCB_SFSR_INVTRAN`, `SCB_SFSR_AUVIOL`, `SCB_SFSR_INVER`, `SCB_SFSR_INVIS`, `SCB_SFSR_INVEP` - Both `_Pos` and `_Msk` variants, matching existing SAU definitions ### Deprecated SAU definitions - SAU structure members: `SAU->SFSR`, `SAU->SFAR` marked with deprecation comments - SAU bit fields: `SAU_SFSR_*` definitions marked deprecated ### Files affected `core_cm33.h`, `core_cm35p.h`, `core_cm52.h`, `core_cm55.h`, `core_cm85.h`, `core_starmc1.h`, `core_starmc3.h` ## Usage ```c // New: Use SCB namespace (correct) uint32_t fault_status = SCB->SFSR; if (fault_status & SCB_SFSR_SFARVALID_Msk) { uint32_t fault_addr = SCB->SFAR; } // Old: SAU namespace (deprecated, still works) uint32_t fault_status = SAU->SFSR; // deprecated: use SCB->SFSR if (fault_status & SAU_SFSR_SFARVALID_Msk) { // deprecated: use SCB_SFSR_SFARVALID_Msk uint32_t fault_addr = SAU->SFAR; // deprecated: use SCB->SFAR } ``` All SAU definitions remain functional for backward compatibility. <!-- START COPILOT CODING AGENT TIPS --> --- ✨ Let Copilot coding agent [set things up for you](https://github.com/ARM-software/CMSIS_6/issues/new?title=✨+Set+up+Copilot+instructions&body=Configure%20instructions%20for%20this%20repository%20as%20documented%20in%20%5BBest%20practices%20for%20Copilot%20coding%20agent%20in%20your%20repository%5D%28https://gh.io/copilot-coding-agent-tips%29%2E%0A%0A%3COnboard%20this%20repo%3E&assignees=copilot) — coding agent works faster and does higher quality work when set up for your repo. --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: JonatanAntoni <25795816+JonatanAntoni@users.noreply.github.com>
1 parent 769813f commit fdbbc52

8 files changed

Lines changed: 204 additions & 21 deletions

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‎CMSIS/Core/Include/core_cm33.h‎

Lines changed: 29 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -864,6 +864,31 @@ typedef struct
864864
#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
865865
#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
866866

867+
/** \brief SCB Secure Fault Status Register Definitions */
868+
#define SCB_SFSR_LSERR_Pos 7U /*!< SCB SFSR: LSERR Position */
869+
#define SCB_SFSR_LSERR_Msk (1UL << SCB_SFSR_LSERR_Pos) /*!< SCB SFSR: LSERR Mask */
870+
871+
#define SCB_SFSR_SFARVALID_Pos 6U /*!< SCB SFSR: SFARVALID Position */
872+
#define SCB_SFSR_SFARVALID_Msk (1UL << SCB_SFSR_SFARVALID_Pos) /*!< SCB SFSR: SFARVALID Mask */
873+
874+
#define SCB_SFSR_LSPERR_Pos 5U /*!< SCB SFSR: LSPERR Position */
875+
#define SCB_SFSR_LSPERR_Msk (1UL << SCB_SFSR_LSPERR_Pos) /*!< SCB SFSR: LSPERR Mask */
876+
877+
#define SCB_SFSR_INVTRAN_Pos 4U /*!< SCB SFSR: INVTRAN Position */
878+
#define SCB_SFSR_INVTRAN_Msk (1UL << SCB_SFSR_INVTRAN_Pos) /*!< SCB SFSR: INVTRAN Mask */
879+
880+
#define SCB_SFSR_AUVIOL_Pos 3U /*!< SCB SFSR: AUVIOL Position */
881+
#define SCB_SFSR_AUVIOL_Msk (1UL << SCB_SFSR_AUVIOL_Pos) /*!< SCB SFSR: AUVIOL Mask */
882+
883+
#define SCB_SFSR_INVER_Pos 2U /*!< SCB SFSR: INVER Position */
884+
#define SCB_SFSR_INVER_Msk (1UL << SCB_SFSR_INVER_Pos) /*!< SCB SFSR: INVER Mask */
885+
886+
#define SCB_SFSR_INVIS_Pos 1U /*!< SCB SFSR: INVIS Position */
887+
#define SCB_SFSR_INVIS_Msk (1UL << SCB_SFSR_INVIS_Pos) /*!< SCB SFSR: INVIS Mask */
888+
889+
#define SCB_SFSR_INVEP_Pos 0U /*!< SCB SFSR: INVEP Position */
890+
#define SCB_SFSR_INVEP_Msk (1UL /*<< SCB_SFSR_INVEP_Pos*/) /*!< SCB SFSR: INVEP Mask */
891+
867892
/** \brief SCB Cache Level ID Register Definitions */
868893
#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
869894
#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
@@ -1586,8 +1611,8 @@ typedef struct
15861611
#else
15871612
uint32_t RESERVED0[3];
15881613
#endif
1589-
__IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
1590-
__IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
1614+
__IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register (deprecated: use SCB->SFSR) */
1615+
__IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register (deprecated: use SCB->SFAR) */
15911616
} SAU_Type;
15921617

15931618
/** \brief SAU Control Register Definitions */
@@ -1622,7 +1647,8 @@ typedef struct
16221647

16231648
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
16241649

1625-
/** \brief SAU Secure Fault Status Register Definitions */
1650+
/** \brief SAU Secure Fault Status Register Definitions
1651+
\deprecated Use SCB_SFSR_* definitions instead which correctly map to SCB->SFSR */
16261652
#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
16271653
#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
16281654

‎CMSIS/Core/Include/core_cm35p.h‎

Lines changed: 29 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -864,6 +864,31 @@ typedef struct
864864
#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
865865
#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
866866

867+
/** \brief SCB Secure Fault Status Register Definitions */
868+
#define SCB_SFSR_LSERR_Pos 7U /*!< SCB SFSR: LSERR Position */
869+
#define SCB_SFSR_LSERR_Msk (1UL << SCB_SFSR_LSERR_Pos) /*!< SCB SFSR: LSERR Mask */
870+
871+
#define SCB_SFSR_SFARVALID_Pos 6U /*!< SCB SFSR: SFARVALID Position */
872+
#define SCB_SFSR_SFARVALID_Msk (1UL << SCB_SFSR_SFARVALID_Pos) /*!< SCB SFSR: SFARVALID Mask */
873+
874+
#define SCB_SFSR_LSPERR_Pos 5U /*!< SCB SFSR: LSPERR Position */
875+
#define SCB_SFSR_LSPERR_Msk (1UL << SCB_SFSR_LSPERR_Pos) /*!< SCB SFSR: LSPERR Mask */
876+
877+
#define SCB_SFSR_INVTRAN_Pos 4U /*!< SCB SFSR: INVTRAN Position */
878+
#define SCB_SFSR_INVTRAN_Msk (1UL << SCB_SFSR_INVTRAN_Pos) /*!< SCB SFSR: INVTRAN Mask */
879+
880+
#define SCB_SFSR_AUVIOL_Pos 3U /*!< SCB SFSR: AUVIOL Position */
881+
#define SCB_SFSR_AUVIOL_Msk (1UL << SCB_SFSR_AUVIOL_Pos) /*!< SCB SFSR: AUVIOL Mask */
882+
883+
#define SCB_SFSR_INVER_Pos 2U /*!< SCB SFSR: INVER Position */
884+
#define SCB_SFSR_INVER_Msk (1UL << SCB_SFSR_INVER_Pos) /*!< SCB SFSR: INVER Mask */
885+
886+
#define SCB_SFSR_INVIS_Pos 1U /*!< SCB SFSR: INVIS Position */
887+
#define SCB_SFSR_INVIS_Msk (1UL << SCB_SFSR_INVIS_Pos) /*!< SCB SFSR: INVIS Mask */
888+
889+
#define SCB_SFSR_INVEP_Pos 0U /*!< SCB SFSR: INVEP Position */
890+
#define SCB_SFSR_INVEP_Msk (1UL /*<< SCB_SFSR_INVEP_Pos*/) /*!< SCB SFSR: INVEP Mask */
891+
867892
/** \brief SCB Cache Level ID Register Definitions */
868893
#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
869894
#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
@@ -1586,8 +1611,8 @@ typedef struct
15861611
#else
15871612
uint32_t RESERVED0[3];
15881613
#endif
1589-
__IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
1590-
__IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
1614+
__IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register (deprecated: use SCB->SFSR) */
1615+
__IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register (deprecated: use SCB->SFAR) */
15911616
} SAU_Type;
15921617

15931618
/** \brief SAU Control Register Definitions */
@@ -1622,7 +1647,8 @@ typedef struct
16221647

16231648
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
16241649

1625-
/** \brief SAU Secure Fault Status Register Definitions */
1650+
/** \brief SAU Secure Fault Status Register Definitions
1651+
\deprecated Use SCB_SFSR_* definitions instead which correctly map to SCB->SFSR */
16261652
#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
16271653
#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
16281654

‎CMSIS/Core/Include/core_cm52.h‎

Lines changed: 29 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1054,6 +1054,31 @@ typedef struct
10541054
#define SCB_DCCISW_UC_SET_Msk (0x3FFUL << SCB_DCCISW_UC_SET_Pos) /*!< SCB DCCISW: Set Mask */
10551055

10561056

1057+
/** \brief SCB Secure Fault Status Register Definitions */
1058+
#define SCB_SFSR_LSERR_Pos 7U /*!< SCB SFSR: LSERR Position */
1059+
#define SCB_SFSR_LSERR_Msk (1UL << SCB_SFSR_LSERR_Pos) /*!< SCB SFSR: LSERR Mask */
1060+
1061+
#define SCB_SFSR_SFARVALID_Pos 6U /*!< SCB SFSR: SFARVALID Position */
1062+
#define SCB_SFSR_SFARVALID_Msk (1UL << SCB_SFSR_SFARVALID_Pos) /*!< SCB SFSR: SFARVALID Mask */
1063+
1064+
#define SCB_SFSR_LSPERR_Pos 5U /*!< SCB SFSR: LSPERR Position */
1065+
#define SCB_SFSR_LSPERR_Msk (1UL << SCB_SFSR_LSPERR_Pos) /*!< SCB SFSR: LSPERR Mask */
1066+
1067+
#define SCB_SFSR_INVTRAN_Pos 4U /*!< SCB SFSR: INVTRAN Position */
1068+
#define SCB_SFSR_INVTRAN_Msk (1UL << SCB_SFSR_INVTRAN_Pos) /*!< SCB SFSR: INVTRAN Mask */
1069+
1070+
#define SCB_SFSR_AUVIOL_Pos 3U /*!< SCB SFSR: AUVIOL Position */
1071+
#define SCB_SFSR_AUVIOL_Msk (1UL << SCB_SFSR_AUVIOL_Pos) /*!< SCB SFSR: AUVIOL Mask */
1072+
1073+
#define SCB_SFSR_INVER_Pos 2U /*!< SCB SFSR: INVER Position */
1074+
#define SCB_SFSR_INVER_Msk (1UL << SCB_SFSR_INVER_Pos) /*!< SCB SFSR: INVER Mask */
1075+
1076+
#define SCB_SFSR_INVIS_Pos 1U /*!< SCB SFSR: INVIS Position */
1077+
#define SCB_SFSR_INVIS_Msk (1UL << SCB_SFSR_INVIS_Pos) /*!< SCB SFSR: INVIS Mask */
1078+
1079+
#define SCB_SFSR_INVEP_Pos 0U /*!< SCB SFSR: INVEP Position */
1080+
#define SCB_SFSR_INVEP_Msk (1UL /*<< SCB_SFSR_INVEP_Pos*/) /*!< SCB SFSR: INVEP Mask */
1081+
10571082
/*@} end of group CMSIS_SCB */
10581083

10591084

@@ -3088,8 +3113,8 @@ typedef struct
30883113
#else
30893114
uint32_t RESERVED0[3];
30903115
#endif
3091-
__IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
3092-
__IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
3116+
__IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register (deprecated: use SCB->SFSR) */
3117+
__IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register (deprecated: use SCB->SFAR) */
30933118
} SAU_Type;
30943119

30953120
/** \brief SAU Control Register Definitions */
@@ -3124,7 +3149,8 @@ typedef struct
31243149

31253150
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
31263151

3127-
/** \brief SAU Secure Fault Status Register Definitions */
3152+
/** \brief SAU Secure Fault Status Register Definitions
3153+
\deprecated Use SCB_SFSR_* definitions instead which correctly map to SCB->SFSR */
31283154
#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
31293155
#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
31303156

‎CMSIS/Core/Include/core_cm55.h‎

Lines changed: 29 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1002,6 +1002,31 @@ typedef struct
10021002
#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
10031003
#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
10041004

1005+
/** \brief SCB Secure Fault Status Register Definitions */
1006+
#define SCB_SFSR_LSERR_Pos 7U /*!< SCB SFSR: LSERR Position */
1007+
#define SCB_SFSR_LSERR_Msk (1UL << SCB_SFSR_LSERR_Pos) /*!< SCB SFSR: LSERR Mask */
1008+
1009+
#define SCB_SFSR_SFARVALID_Pos 6U /*!< SCB SFSR: SFARVALID Position */
1010+
#define SCB_SFSR_SFARVALID_Msk (1UL << SCB_SFSR_SFARVALID_Pos) /*!< SCB SFSR: SFARVALID Mask */
1011+
1012+
#define SCB_SFSR_LSPERR_Pos 5U /*!< SCB SFSR: LSPERR Position */
1013+
#define SCB_SFSR_LSPERR_Msk (1UL << SCB_SFSR_LSPERR_Pos) /*!< SCB SFSR: LSPERR Mask */
1014+
1015+
#define SCB_SFSR_INVTRAN_Pos 4U /*!< SCB SFSR: INVTRAN Position */
1016+
#define SCB_SFSR_INVTRAN_Msk (1UL << SCB_SFSR_INVTRAN_Pos) /*!< SCB SFSR: INVTRAN Mask */
1017+
1018+
#define SCB_SFSR_AUVIOL_Pos 3U /*!< SCB SFSR: AUVIOL Position */
1019+
#define SCB_SFSR_AUVIOL_Msk (1UL << SCB_SFSR_AUVIOL_Pos) /*!< SCB SFSR: AUVIOL Mask */
1020+
1021+
#define SCB_SFSR_INVER_Pos 2U /*!< SCB SFSR: INVER Position */
1022+
#define SCB_SFSR_INVER_Msk (1UL << SCB_SFSR_INVER_Pos) /*!< SCB SFSR: INVER Mask */
1023+
1024+
#define SCB_SFSR_INVIS_Pos 1U /*!< SCB SFSR: INVIS Position */
1025+
#define SCB_SFSR_INVIS_Msk (1UL << SCB_SFSR_INVIS_Pos) /*!< SCB SFSR: INVIS Mask */
1026+
1027+
#define SCB_SFSR_INVEP_Pos 0U /*!< SCB SFSR: INVEP Position */
1028+
#define SCB_SFSR_INVEP_Msk (1UL /*<< SCB_SFSR_INVEP_Pos*/) /*!< SCB SFSR: INVEP Mask */
1029+
10051030
/*@} end of group CMSIS_SCB */
10061031

10071032

@@ -3038,8 +3063,8 @@ typedef struct
30383063
#else
30393064
uint32_t RESERVED0[3];
30403065
#endif
3041-
__IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
3042-
__IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
3066+
__IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register (deprecated: use SCB->SFSR) */
3067+
__IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register (deprecated: use SCB->SFAR) */
30433068
} SAU_Type;
30443069

30453070
/** \brief SAU Control Register Definitions */
@@ -3074,7 +3099,8 @@ typedef struct
30743099

30753100
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
30763101

3077-
/** \brief SAU Secure Fault Status Register Definitions */
3102+
/** \brief SAU Secure Fault Status Register Definitions
3103+
\deprecated Use SCB_SFSR_* definitions instead which correctly map to SCB->SFSR */
30783104
#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
30793105
#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
30803106

‎CMSIS/Core/Include/core_cm85.h‎

Lines changed: 29 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1023,6 +1023,31 @@ typedef struct
10231023
#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
10241024
#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
10251025

1026+
/** \brief SCB Secure Fault Status Register Definitions */
1027+
#define SCB_SFSR_LSERR_Pos 7U /*!< SCB SFSR: LSERR Position */
1028+
#define SCB_SFSR_LSERR_Msk (1UL << SCB_SFSR_LSERR_Pos) /*!< SCB SFSR: LSERR Mask */
1029+
1030+
#define SCB_SFSR_SFARVALID_Pos 6U /*!< SCB SFSR: SFARVALID Position */
1031+
#define SCB_SFSR_SFARVALID_Msk (1UL << SCB_SFSR_SFARVALID_Pos) /*!< SCB SFSR: SFARVALID Mask */
1032+
1033+
#define SCB_SFSR_LSPERR_Pos 5U /*!< SCB SFSR: LSPERR Position */
1034+
#define SCB_SFSR_LSPERR_Msk (1UL << SCB_SFSR_LSPERR_Pos) /*!< SCB SFSR: LSPERR Mask */
1035+
1036+
#define SCB_SFSR_INVTRAN_Pos 4U /*!< SCB SFSR: INVTRAN Position */
1037+
#define SCB_SFSR_INVTRAN_Msk (1UL << SCB_SFSR_INVTRAN_Pos) /*!< SCB SFSR: INVTRAN Mask */
1038+
1039+
#define SCB_SFSR_AUVIOL_Pos 3U /*!< SCB SFSR: AUVIOL Position */
1040+
#define SCB_SFSR_AUVIOL_Msk (1UL << SCB_SFSR_AUVIOL_Pos) /*!< SCB SFSR: AUVIOL Mask */
1041+
1042+
#define SCB_SFSR_INVER_Pos 2U /*!< SCB SFSR: INVER Position */
1043+
#define SCB_SFSR_INVER_Msk (1UL << SCB_SFSR_INVER_Pos) /*!< SCB SFSR: INVER Mask */
1044+
1045+
#define SCB_SFSR_INVIS_Pos 1U /*!< SCB SFSR: INVIS Position */
1046+
#define SCB_SFSR_INVIS_Msk (1UL << SCB_SFSR_INVIS_Pos) /*!< SCB SFSR: INVIS Mask */
1047+
1048+
#define SCB_SFSR_INVEP_Pos 0U /*!< SCB SFSR: INVEP Position */
1049+
#define SCB_SFSR_INVEP_Msk (1UL /*<< SCB_SFSR_INVEP_Pos*/) /*!< SCB SFSR: INVEP Mask */
1050+
10261051
/*@} end of group CMSIS_SCB */
10271052

10281053

@@ -3062,8 +3087,8 @@ typedef struct
30623087
#else
30633088
uint32_t RESERVED0[3];
30643089
#endif
3065-
__IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
3066-
__IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
3090+
__IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register (deprecated: use SCB->SFSR) */
3091+
__IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register (deprecated: use SCB->SFAR) */
30673092
} SAU_Type;
30683093

30693094
/** \brief SAU Control Register Definitions */
@@ -3098,7 +3123,8 @@ typedef struct
30983123

30993124
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
31003125

3101-
/** \brief SAU Secure Fault Status Register Definitions */
3126+
/** \brief SAU Secure Fault Status Register Definitions
3127+
\deprecated Use SCB_SFSR_* definitions instead which correctly map to SCB->SFSR */
31023128
#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
31033129
#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
31043130

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