GCC extended inline assembly in MVE kernels causes hard errors on IAR (Og005/Og006)

[Symanyshyn-IFX]

Several CMSIS-NN MVE-optimized kernel functions use GCC extended inline assembly syntax (__ASM volatile(...) .p2align GAS directives) inside #if defined(ARM_MATH_MVEI) blocks. These blocks are guarded for Helium hardware but not for the compiler. When building for Cortex-M55 with IAR, ARM_MATH_MVEI is defined but IAR cannot parse GCC inline assembly, resulting in hard compilation errors.

Affected files:

CMSIS-NN/Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c

Line 84 in 22080c6

__ASM volatile(" .p2align 2 \n"

CMSIS-NN/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c

Line 81 in 22080c6

__ASM volatile(" .p2align 2 \n"

CMSIS-NN/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c

Line 96 in 22080c6

__ASM volatile(" .p2align 2 \n"

CMSIS-NN/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c

Line 173 in 22080c6

__ASM volatile(" .p2align 2 \n"

CMSIS-NN/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s16.c

Line 101 in 22080c6

__ASM volatile(" .p2align 2 \n"

CMSIS-NN/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s16.c

Line 229 in 22080c6

__ASM volatile(" .p2align 2 \n"

CMSIS-NN/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s16.c

Line 294 in 22080c6

__ASM volatile(" .p2align 2 \n"

Compiler: IAR Compiler for Arm V9.70.1
Device: Cortex-M55, Helium - ARM_MATH_MVEI defined
Build flags: --cpu Cortex-M55 -Ol --fpu FPv5_D16 --aapcs vfp --endian=little -e --enable_restrict --no_wrap_diagnostics --no_dwarf4 --debug --dlib_config=full

Current user-side workaround:
Define ARM_MATH_AUTOVECTORIZE globally when building with IAR for Cortex-M55

[mansnils]

Ideally, the inline assembly should be replaced with intrinsics. The reason for using inline assembly was that GCC did not generate sufficiently efficient code for the intrinsics at the time. This may have improved in recent GCC releases.