From 35c2c5e5e570ff40cf2ac15682d624791c5bde66 Mon Sep 17 00:00:00 2001 From: Jen-Tse Huang Date: Thu, 30 Oct 2025 15:04:18 +0100 Subject: [PATCH 1/2] Update example for Toolbox 2.12.0 --- .gitignore | 83 ++++++++- AVH-MLOps-main/MLOps.csolution.yml | 222 ++++++++++++++---------- TFLmicrospeech/MLOps.csolution.yml | 241 ++++++++++++++++----------- TFLmicrospeech/cdefault.yml | 14 ++ mlek-kws/MLOps.csolution.yml | 57 +++++-- mlek-kws/Model/ML_Model.cproject.yml | 24 +-- mlek-kws/README.md | 20 +-- mlek-kws/Test/ML_Test.cproject.yml | 2 +- mlek-kws/cdefault.yml | 14 +- vcpkg-configuration.json | 39 ++--- 10 files changed, 472 insertions(+), 244 deletions(-) create mode 100644 TFLmicrospeech/cdefault.yml diff --git a/.gitignore b/.gitignore index 944e0c8..19d4d5f 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,84 @@ +# Prerequisites +*.d -.DS_Store +# Object files *.o +*.ko +*.obj +*.elf + +# Linker output +*.ilk +*.map +*.exp + +# Precompiled Headers +*.gch +*.pch + +# Libraries +*.lib +*.a +*.la +*.lo + +# Shared objects (inc. Windows DLLs) +*.dll +*.so +*.so.* +*.dylib + +# Executables +*.exe +*.out +*.app +*.i*86 +*.x86_64 +*.hex + +# Debug files +*.dSYM/ +*.su +*.idb +*.pdb + +# Kernel Module Compile Results +*.mod* +*.cmd +.tmp_versions/ +modules.order +Module.symvers +Mkfile.old +dkms.conf + +# Clangd +.clangd + +# uv2csolution generated log file +uv2csolution.log + +# CMSIS Solution files and folders not to be tracked +# default directory of build artifacts +**/out +# directory containing intermediate files to be regenerated +**/tmp + +# Update config files must be merged before commit +*.update@* + +# cbuild output files +*.cbuild.yml +*.cbuild-idx.yml +*.cbuild-run.yml +*.cbuild-set.yml +*.cbuild-pack.yml + +# .vscode JSON and debug adapter files generated by CMSIS Solution +.vscode/cmsis.json +.vscode/launch.json +.vscode/tasks.json +.vscode/settings.json +.cmd.jlink + +# legacy intermediate project file +*.cprj diff --git a/AVH-MLOps-main/MLOps.csolution.yml b/AVH-MLOps-main/MLOps.csolution.yml index 7778c9c..82fb4fe 100644 --- a/AVH-MLOps-main/MLOps.csolution.yml +++ b/AVH-MLOps-main/MLOps.csolution.yml @@ -1,86 +1,136 @@ -solution: - created-for: cmsis-toobox@2.0.0 - - cdefault: - - packs: - - pack: ARM::Cortex_DFP@>=1.0.0-dev0 - - pack: ARM::CMSIS@>=6.0.0-dev0 - - target-types: - - type: CM0 - device: ARMCM0 - variables: - - Target-Layer: ../Target/CM0/Target.clayer.yml - - type: CM0plus - device: ARMCM0P - variables: - - Target-Layer: ../Target/CM0plus/Target.clayer.yml - - type: CM3 - device: ARMCM3 - variables: - - Target-Layer: ../Target/CM3/Target.clayer.yml - - type: CM4 - device: ARMCM4 - processor: - fpu: off - variables: - - Target-Layer: ../Target/CM4/Target.clayer.yml - - type: CM4_FP - device: ARMCM4 - variables: - - Target-Layer: ../Target/CM4/Target.clayer.yml - - type: CM7 - device: ARMCM7 - variables: - - Target-Layer: ../Target/CM7/Target.clayer.yml - - type: CM23 - device: ARMCM23 - processor: - trustzone: off - variables: - - Target-Layer: ../Target/CM23/Target.clayer.yml - - type: CM33 - device: ARMCM33 - processor: - trustzone: off - variables: - - Target-Layer: ../Target/CM33/Target.clayer.yml - - type: CM55 - device: ARMCM55 - processor: - trustzone: off - variables: - - Target-Layer: ../Target/CM55/Target.clayer.yml - - type: CM55_Ethos - device: ARMCM55 - processor: - trustzone: off - variables: - - Target-Layer: ../Target/CM55_Ethos/Target.clayer.yml - - type: CM85 - device: ARMCM85 - processor: - trustzone: off - variables: - - Target-Layer: ../Target/CM85/Target.clayer.yml - - type: CM85_Ethos - device: ARMCM85 - processor: - trustzone: off - variables: - - Target-Layer: ../Target/CM85_Ethos/Target.clayer.yml - - build-types: - - type: balanced - optimize: balanced - debug: on - - type: size - optimize: size - debug: on - - type: speed - optimize: speed - debug: on - - projects: - - project: ./Test/ML_Test.cproject.yml +solution: + created-for: cmsis-toobox@2.0.0 + + cdefault: + + compiler: AC6 + + packs: + - pack: ARM::Cortex_DFP@>=1.0.0-dev0 + - pack: ARM::CMSIS@>=6.0.0-dev0 + + target-types: + - type: CM0 + device: ARMCM0 + variables: + - Target-Layer: ../Target/CM0/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - type: CM0plus + device: ARMCM0P + variables: + - Target-Layer: ../Target/CM0plus/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - type: CM3 + device: ARMCM3 + variables: + - Target-Layer: ../Target/CM3/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - type: CM4 + device: ARMCM4 + processor: + fpu: off + variables: + - Target-Layer: ../Target/CM4/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - type: CM4_FP + device: ARMCM4 + variables: + - Target-Layer: ../Target/CM4/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - type: CM7 + device: ARMCM7 + variables: + - Target-Layer: ../Target/CM7/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - type: CM23 + device: ARMCM23 + processor: + trustzone: off + variables: + - Target-Layer: ../Target/CM23/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - type: CM33 + device: ARMCM33 + processor: + trustzone: off + variables: + - Target-Layer: ../Target/CM33/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - type: CM55 + device: ARMCM55 + processor: + trustzone: off + variables: + - Target-Layer: ../Target/CM55/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - type: CM55_Ethos + device: ARMCM55 + processor: + trustzone: off + variables: + - Target-Layer: ../Target/CM55_Ethos/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - type: CM85 + device: ARMCM85 + processor: + trustzone: off + variables: + - Target-Layer: ../Target/CM85/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - type: CM85_Ethos + device: ARMCM85 + processor: + trustzone: off + variables: + - Target-Layer: ../Target/CM85_Ethos/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + + build-types: + - type: balanced + optimize: balanced + debug: on + - type: size + optimize: size + debug: on + - type: speed + optimize: speed + debug: on + + projects: + - project: ./Test/ML_Test.cproject.yml diff --git a/TFLmicrospeech/MLOps.csolution.yml b/TFLmicrospeech/MLOps.csolution.yml index 536a3c6..81936d8 100644 --- a/TFLmicrospeech/MLOps.csolution.yml +++ b/TFLmicrospeech/MLOps.csolution.yml @@ -1,96 +1,145 @@ -solution: - created-for: cmsis-toobox@2.0.0 - - cdefault: - misc: - - for-compiler: GCC - C-CPP: - - -ffunction-sections - - -fdata-sections - Link: - - -Wl,--gc-sections - - for-compiler: CLANG - C-CPP: - - -ffunction-sections - - -fdata-sections - Link: - - -Wl,--gc-sections - - packs: - - pack: ARM::Cortex_DFP@>=1.0.0-dev0 - - target-types: - - type: CM0 - device: ARMCM0 - variables: - - Target-Layer: ../Target/CM0/Target.clayer.yml - - type: CM0plus - device: ARMCM0P - variables: - - Target-Layer: ../Target/CM0plus/Target.clayer.yml - - type: CM3 - device: ARMCM3 - variables: - - Target-Layer: ../Target/CM3/Target.clayer.yml - - type: CM4 - device: ARMCM4 - processor: - fpu: off - variables: - - Target-Layer: ../Target/CM4/Target.clayer.yml - - type: CM4_FP - device: ARMCM4 - variables: - - Target-Layer: ../Target/CM4/Target.clayer.yml - - type: CM7 - device: ARMCM7 - variables: - - Target-Layer: ../Target/CM7/Target.clayer.yml - - type: CM23 - device: ARMCM23 - processor: - trustzone: off - variables: - - Target-Layer: ../Target/CM23/Target.clayer.yml - - type: CM33 - device: ARMCM33 - processor: - trustzone: off - variables: - - Target-Layer: ../Target/CM33/Target.clayer.yml - - type: CM55 - device: ARMCM55 - processor: - trustzone: off - variables: - - Target-Layer: ../Target/CM55/Target.clayer.yml - - type: CM55_Ethos - device: ARMCM55 - processor: - trustzone: off - variables: - - Target-Layer: ../Target/CM55_Ethos/Target.clayer.yml - - type: CM85 - device: ARMCM85 - processor: - trustzone: off - variables: - - Target-Layer: ../Target/CM85/Target.clayer.yml - - type: CM85_Ethos - device: ARMCM85 - processor: - trustzone: off - variables: - - Target-Layer: ../Target/CM85_Ethos/Target.clayer.yml - - build-types: - - type: balanced - optimize: balanced - - type: size - optimize: size - - type: speed - optimize: speed - - projects: - - project: ./Model/ML_Model.cproject.yml - - project: ./Test/ML_Test.cproject.yml +solution: + created-for: cmsis-toolbox@2.0.0 + + cdefault: + + compiler: AC6 + + packs: + - pack: ARM::Cortex_DFP@>=1.0.0-dev0 + + target-types: + - type: CM0 + device: ARMCM0 + variables: + - Target-Layer: ../Target/CM0/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - project-context: ML_Model.balanced + - type: CM0plus + device: ARMCM0P + variables: + - Target-Layer: ../Target/CM0plus/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - project-context: ML_Model.balanced + - type: CM3 + device: ARMCM3 + variables: + - Target-Layer: ../Target/CM3/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - project-context: ML_Model.balanced + - type: CM4 + device: ARMCM4 + processor: + fpu: off + variables: + - Target-Layer: ../Target/CM4/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - project-context: ML_Model.balanced + - type: CM4_FP + device: ARMCM4 + variables: + - Target-Layer: ../Target/CM4/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - project-context: ML_Model.balanced + - type: CM7 + device: ARMCM7 + variables: + - Target-Layer: ../Target/CM7/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - project-context: ML_Model.balanced + - type: CM23 + device: ARMCM23 + processor: + trustzone: off + variables: + - Target-Layer: ../Target/CM23/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - project-context: ML_Model.balanced + - type: CM33 + device: ARMCM33 + processor: + trustzone: off + variables: + - Target-Layer: ../Target/CM33/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - project-context: ML_Model.balanced + - type: CM55 + device: ARMCM55 + processor: + trustzone: off + variables: + - Target-Layer: ../Target/CM55/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - project-context: ML_Model.balanced + - type: CM55_Ethos + device: ARMCM55 + processor: + trustzone: off + variables: + - Target-Layer: ../Target/CM55_Ethos/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - project-context: ML_Model.balanced + - type: CM85 + device: ARMCM85 + processor: + trustzone: off + variables: + - Target-Layer: ../Target/CM85/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - project-context: ML_Model.balanced + - type: CM85_Ethos + device: ARMCM85 + processor: + trustzone: off + variables: + - Target-Layer: ../Target/CM85_Ethos/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - project-context: ML_Model.balanced + + build-types: + - type: balanced + optimize: balanced + - type: size + optimize: size + - type: speed + optimize: speed + + projects: + - project: ./Model/ML_Model.cproject.yml + - project: ./Test/ML_Test.cproject.yml diff --git a/TFLmicrospeech/cdefault.yml b/TFLmicrospeech/cdefault.yml new file mode 100644 index 0000000..de37d99 --- /dev/null +++ b/TFLmicrospeech/cdefault.yml @@ -0,0 +1,14 @@ +default: + misc: + - for-compiler: GCC + C-CPP: + - -ffunction-sections + - -fdata-sections + Link: + - -Wl,--gc-sections + - for-compiler: CLANG + C-CPP: + - -ffunction-sections + - -fdata-sections + Link: + - -Wl,--gc-sections diff --git a/mlek-kws/MLOps.csolution.yml b/mlek-kws/MLOps.csolution.yml index 8a4e604..4dd4288 100644 --- a/mlek-kws/MLOps.csolution.yml +++ b/mlek-kws/MLOps.csolution.yml @@ -1,20 +1,9 @@ solution: - created-for: cmsis-toobox@2.0.0 + created-for: cmsis-toolbox@2.0.0 cdefault: - misc: - - for-compiler: GCC - C-CPP: - - -ffunction-sections - - -fdata-sections - Link: - - -Wl,--gc-sections - - for-compiler: CLANG - C-CPP: - - -ffunction-sections - - -fdata-sections - Link: - - -Wl,--gc-sections + + compiler: AC6 packs: - pack: ARM::Cortex_DFP@>=1.0.0-dev0 @@ -47,14 +36,29 @@ solution: fpu: off variables: - Target-Layer: ../Target/CM4/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - project-context: ML_Model.balanced - type: CM4_FP device: ARMCM4 variables: - Target-Layer: ../Target/CM4/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - project-context: ML_Model.balanced - type: CM7 device: ARMCM7 variables: - Target-Layer: ../Target/CM7/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - project-context: ML_Model.balanced # - type: CM23 # device: ARMCM23 # processor: @@ -67,12 +71,22 @@ solution: trustzone: off variables: - Target-Layer: ../Target/CM33/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - project-context: ML_Model.balanced - type: CM55 device: ARMCM55 processor: trustzone: off variables: - Target-Layer: ../Target/CM55/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - project-context: ML_Model.balanced - type: CM55_Ethos device: ARM::SSE-300-MPS3 processor: @@ -82,12 +96,22 @@ solution: - ETHOSU55 variables: - Target-Layer: ../Target/CM55_Ethos/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - project-context: ML_Model.balanced - type: CM85 device: ARMCM85 processor: trustzone: off variables: - Target-Layer: ../Target/CM85/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - project-context: ML_Model.balanced - type: CM85_Ethos device: ARM::SSE-310-MPS3_FVP processor: @@ -97,6 +121,11 @@ solution: - ETHOSU65 variables: - Target-Layer: ../Target/CM85_Ethos/Target.clayer.yml + target-set: + - set: + images: + - project-context: ML_Test.balanced + - project-context: ML_Model.balanced build-types: - type: balanced diff --git a/mlek-kws/Model/ML_Model.cproject.yml b/mlek-kws/Model/ML_Model.cproject.yml index 49634b6..3d7fd20 100644 --- a/mlek-kws/Model/ML_Model.cproject.yml +++ b/mlek-kws/Model/ML_Model.cproject.yml @@ -34,19 +34,19 @@ project: - component: ARM::CMSIS:CORE - component: ARM::CMSIS:DSP&Source - component: ARM::CMSIS:NN Lib - - component: tensorflow::Data Exchange:Serialization:flatbuffers - - component: tensorflow::Data Processing:Math:gemmlowp fixed-point - - component: tensorflow::Data Processing:Math:kissfft - - component: tensorflow::Data Processing:Math:ruy + - component: tensorflow::Data Exchange:Serialization:flatbuffers&tensorflow + - component: tensorflow::Data Processing:Math:gemmlowp fixed-point&tensorflow + - component: tensorflow::Data Processing:Math:kissfft&tensorflow + - component: tensorflow::Data Processing:Math:ruy&tensorflow - component: tensorflow::Machine Learning:TensorFlow:Kernel&CMSIS-NN for-context: - - +CM0 - - +CM0plus - - +CM3 + # - +CM0 + # - +CM0plus + # - +CM3 - +CM4 - +CM4_FP - +CM7 - - +CM23 + # - +CM23 - +CM33 - +CM55 - +CM85 @@ -74,13 +74,13 @@ project: - file: ./src/Labels.cpp - file: ./src/kws_micronet_m.tflite.cpp for-context: - - +CM0 - - +CM0plus - - +CM3 + # - +CM0 + # - +CM0plus + # - +CM3 - +CM4 - +CM4_FP - +CM7 - - +CM23 + # - +CM23 - +CM33 - +CM55 - +CM85 diff --git a/mlek-kws/README.md b/mlek-kws/README.md index b3134d5..b2bd590 100644 --- a/mlek-kws/README.md +++ b/mlek-kws/README.md @@ -51,21 +51,21 @@ Build command syntax: Examples: -- Build Model for Cortex-M7 with AC6 (size) +- Build Model for Cortex-M4 with AC6 (size) ```sh - cbuild MLOps.csolution.yml --context ML_Model.size+CM7 --toolchain AC6 + cbuild MLOps.csolution.yml --context ML_Model.size+CM4 --toolchain AC6 ``` -- Build Test for Cortex-M7 with AC6 (size) +- Build Test for Cortex-M4 with AC6 (size) ```sh - cbuild MLOps.csolution.yml --context ML_Test.size+CM7 --toolchain AC6 + cbuild MLOps.csolution.yml --context ML_Test.size+CM4 --toolchain AC6 ``` -- Build Model and Test for Cortex-M7 with AC6 (size) +- Build Model and Test for Cortex-M4 with AC6 (size) ```sh - cbuild MLOps.csolution.yml --context .size+CM7 --toolchain AC6 + cbuild MLOps.csolution.yml --context .size+CM4 --toolchain AC6 ``` -- Build Model and Test for Cortex-M7 with AC6 (size, size, speed) +- Build Model and Test for Cortex-M4 with AC6 (size, size, speed) ```sh - cbuild MLOps.csolution.yml --context +CM7 --toolchain AC6 + cbuild MLOps.csolution.yml --context +CM4 --toolchain AC6 ``` - Build Model and Test for all cores with GCC (size, size, speed) ```sh @@ -80,9 +80,9 @@ Run command syntax: Examples: -- Run Test on model for Cortex-M7 (size) +- Run Test on model for Cortex-M4 (size) ```sh -FVP_MPS2_Cortex-M7 -f ./Target/CM7/fvp_config.txt ./out/ML_Test/CM7/size/ML_Test.axf +FVP_MPS2_Cortex-M4 -f ./Target/CM4/fvp_config.txt ./out/ML_Test/CM4/size/ML_Test.axf ``` - Run Test on model for Cortex-M55 with Ethos (size) ```sh diff --git a/mlek-kws/Test/ML_Test.cproject.yml b/mlek-kws/Test/ML_Test.cproject.yml index 7e995f0..5c175a9 100644 --- a/mlek-kws/Test/ML_Test.cproject.yml +++ b/mlek-kws/Test/ML_Test.cproject.yml @@ -22,7 +22,7 @@ project: - component: ARM::CMSIS:CORE - component: ARM::CMSIS:DSP&Source - component: CMSIS-View:Event Recorder&Semihosting - - component: tensorflow::Data Exchange:Serialization:flatbuffers + - component: tensorflow::Data Exchange:Serialization:flatbuffers&tensorflow - component: tensorflow::Machine Learning:TensorFlow:Testing - component: ARM::ML Eval Kit:Common:API - component: ARM::ML Eval Kit:Common:Log diff --git a/mlek-kws/cdefault.yml b/mlek-kws/cdefault.yml index f4832f5..de37d99 100644 --- a/mlek-kws/cdefault.yml +++ b/mlek-kws/cdefault.yml @@ -1,2 +1,14 @@ default: - compiler: AC6 + misc: + - for-compiler: GCC + C-CPP: + - -ffunction-sections + - -fdata-sections + Link: + - -Wl,--gc-sections + - for-compiler: CLANG + C-CPP: + - -ffunction-sections + - -fdata-sections + Link: + - -Wl,--gc-sections diff --git a/vcpkg-configuration.json b/vcpkg-configuration.json index 59b61c0..63f3b22 100644 --- a/vcpkg-configuration.json +++ b/vcpkg-configuration.json @@ -1,23 +1,16 @@ -{ - "registries": [ - { - "kind": "artifact", - "location": "https://aka.ms/vcpkg-ce-default", - "name": "microsoft" - }, - { - "kind": "artifact", - "location": "https://artifacts.keil.arm.com/vcpkg-ce-registry/registry.zip", - "name": "arm" - } - ], - "requires": { - "microsoft:cmake": "^3.25.2", - "microsoft:ninja": "^1.10.2", - "arm:compilers/arm/armclang":"^6.20.0", - "arm:compilers/arm/arm-none-eabi-gcc": "^12.3.1-0", - "arm:compilers/arm/llvm-embedded": "^16.0.0-0", - "arm:tools/open-cmsis-pack/cmsis-toolbox": "^2.1.0-0", - "arm:models/arm/avh-fvp": "^11.22.39" - } -} +{ + "registries": [ + { + "name": "arm", + "kind": "artifact", + "location": "https://artifacts.tools.arm.com/vcpkg-registry" + } + ], + "requires": { + "arm:compilers/arm/armclang": "6.20.0", + "arm:compilers/arm/arm-none-eabi-gcc": "^12.3.1-0", + "arm:compilers/arm/llvm-embedded": "^16.0.0-0", + "arm:tools/open-cmsis-pack/cmsis-toolbox": "^2.1.0-0", + "arm:models/arm/avh-fvp": "^11.22.39" + } +} \ No newline at end of file From 7ee0b15069c926d1b50dd1fbd9e40b24211608c6 Mon Sep 17 00:00:00 2001 From: Jen-Tse Huang Date: Wed, 5 Nov 2025 11:09:57 +0100 Subject: [PATCH 2/2] Update workflow to fix some incompatibility issues. --- .github/workflows/build_MLEK_kws.yml | 18 +- .github/workflows/build_TFLmicrospeech.yml | 25 +- .github/workflows/licensed_image_test.yml | 2 +- README.md | 29 +- .../debug_log.cpp.base@1.22.5-rc4 | 43 +++ .../micro_time.cpp.base@1.22.5-rc4 | 67 ++++ .../system_setup.cpp.base@1.22.5-rc4 | 25 ++ .../Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0 | 123 +++++++ .../ARMCM55/startup_ARMCM55.c.base@1.1.0 | 164 +++++++++ .../ARMCM55/system_ARMCM55.c.base@1.1.0 | 107 ++++++ .../RTE/Device/ARMCM55/ARMCM55_ac6.sct | 123 +++++++ .../Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0 | 123 +++++++ .../Device/ARMCM55/ac6_linker_script.sct.src | 109 ++++++ .../ARMCM55/startup_ARMCM55.c.base@1.1.0 | 164 +++++++++ .../ARMCM55/system_ARMCM55.c.base@1.1.0 | 107 ++++++ .../CMSIS-View/EventRecorderConf.h.base@1.1.0 | 47 +++ docker_base/armllvm_install.sh | 8 +- docker_base/avh-fvp_install.sh | 10 +- docker_base/cmsistoolbox_install.sh | 2 +- docker_base/vela_install.sh | 39 ++ mlek-kws/.cmsis/MLOps+CM55_Ethos.dbgconf | 13 + .../MLOps+CM55_Ethos.dbgconf.base@0.0.0 | 13 + mlek-kws/Model/ML_Model.cproject.yml | 6 +- .../debug_log.cpp.base@1.22.8 | 43 +++ .../micro_time.cpp.base@1.22.8 | 69 ++++ .../system_setup.cpp.base@1.22.8 | 25 ++ .../CM4/RTE/Device/ARMCM4/ARMCM4_ac6.sct | 80 ++++ .../Device/ARMCM4/ac6_linker_script.sct.src | 109 ++++++ .../SSE-300-MPS3/RTE_Device.h.base@1.1.0 | 84 +++++ .../cmsis_driver_config.h.base@1.1.1 | 25 ++ .../SSE-300-MPS3/device_cfg.h.base@1.1.3 | 149 ++++++++ .../fvp_sse300_mps3_s.sct.base@1.1.0 | 78 ++++ .../platform_base_address.h.base@1.1.2 | 271 ++++++++++++++ .../SSE-300-MPS3/region_defs.h.base@1.0.0 | 44 +++ .../SSE-300-MPS3/region_limits.h.base@1.0.0 | 45 +++ .../startup_fvp_sse300_mps3.c.base@1.1.1 | 344 ++++++++++++++++++ .../system_SSE300MPS3.c.base@1.1.1 | 86 +++++ .../system_SSE300MPS3.h.base@1.1.1 | 48 +++ .../Target/CM55_Ethos/Source/BoardInit.cpp | 2 +- mlek-kws/Target/CM55_Ethos/Target.clayer.yml | 4 +- .../Target/CM85_Ethos/Source/BoardInit.cpp | 2 +- mlek-kws/Target/CM85_Ethos/Target.clayer.yml | 4 +- mlek-kws/Test/ML_Test.cproject.yml | 1 + .../CMSIS-View/EventRecorderConf.h.base@1.1.0 | 47 +++ vcpkg-configuration.json | 6 +- 45 files changed, 2874 insertions(+), 59 deletions(-) create mode 100644 TFLmicrospeech/Model/RTE/Machine_Learning/debug_log.cpp.base@1.22.5-rc4 create mode 100644 TFLmicrospeech/Model/RTE/Machine_Learning/micro_time.cpp.base@1.22.5-rc4 create mode 100644 TFLmicrospeech/Model/RTE/Machine_Learning/system_setup.cpp.base@1.22.5-rc4 create mode 100644 TFLmicrospeech/Target/CM55/RTE/Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0 create mode 100644 TFLmicrospeech/Target/CM55/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 create mode 100644 TFLmicrospeech/Target/CM55/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 create mode 100644 TFLmicrospeech/Target/CM55_Ethos/RTE/Device/ARMCM55/ARMCM55_ac6.sct create mode 100644 TFLmicrospeech/Target/CM55_Ethos/RTE/Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0 create mode 100644 TFLmicrospeech/Target/CM55_Ethos/RTE/Device/ARMCM55/ac6_linker_script.sct.src create mode 100644 TFLmicrospeech/Target/CM55_Ethos/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 create mode 100644 TFLmicrospeech/Target/CM55_Ethos/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 create mode 100644 TFLmicrospeech/Test/RTE/CMSIS-View/EventRecorderConf.h.base@1.1.0 create mode 100644 mlek-kws/.cmsis/MLOps+CM55_Ethos.dbgconf create mode 100644 mlek-kws/.cmsis/MLOps+CM55_Ethos.dbgconf.base@0.0.0 create mode 100644 mlek-kws/Model/RTE/Machine_Learning/debug_log.cpp.base@1.22.8 create mode 100644 mlek-kws/Model/RTE/Machine_Learning/micro_time.cpp.base@1.22.8 create mode 100644 mlek-kws/Model/RTE/Machine_Learning/system_setup.cpp.base@1.22.8 create mode 100644 mlek-kws/Target/CM4/RTE/Device/ARMCM4/ARMCM4_ac6.sct create mode 100644 mlek-kws/Target/CM4/RTE/Device/ARMCM4/ac6_linker_script.sct.src create mode 100644 mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0 create mode 100644 mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1 create mode 100644 mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3 create mode 100644 mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct.base@1.1.0 create mode 100644 mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/platform_base_address.h.base@1.1.2 create mode 100644 mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0 create mode 100644 mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0 create mode 100644 mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c.base@1.1.1 create mode 100644 mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 create mode 100644 mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h.base@1.1.1 create mode 100644 mlek-kws/Test/RTE/CMSIS-View/EventRecorderConf.h.base@1.1.0 diff --git a/.github/workflows/build_MLEK_kws.yml b/.github/workflows/build_MLEK_kws.yml index 54e8401..b0935ba 100644 --- a/.github/workflows/build_MLEK_kws.yml +++ b/.github/workflows/build_MLEK_kws.yml @@ -32,28 +32,20 @@ jobs: # Set permissions for the working directory to avoid permission errors run: chmod 777 -R /__w - - name: Install custom CMSIS packs - # Install custom CMSIS packs required for the ML project - run: | - wget -P /home/arm_mlops_docker https://github.com/ARM-software/CMSIS_6/releases/download/dev%2Fv6.0.0-dev35/ARM.CMSIS.6.0.0-dev35+geb1d42a.pack -nv - su -l arm_mlops_docker -c "/home/arm_mlops_docker/cmsis-toolbox-linux-amd64/bin/cpackget add ARM.CMSIS.6.0.0-dev35+geb1d42a.pack --agree-embedded-license" - wget -P /home/arm_mlops_docker https://github.com/ARM-software/Cortex_DFP/releases/download/dev%2Fv1.0.0-dev15/ARM.Cortex_DFP.1.0.0-dev15+gf6802e4.pack -nv - su -l arm_mlops_docker -c "/home/arm_mlops_docker/cmsis-toolbox-linux-amd64/bin/cpackget add ARM.Cortex_DFP.1.0.0-dev15+gf6802e4.pack --agree-embedded-license" - - - name: Build Model and Test for Cortex-M4 with AC6 (size) / Corstone-300 for Community Edition + - name: Build Model and Test for Cortex-M4 with AC6 (balanced) / Corstone-300 for Community Edition run: | if [ -z "${{ secrets.ARM_UBL_LICENSE_IDENTIFIER }}" ]; then - su - arm_mlops_docker -c "/home/arm_mlops_docker/cmsis-toolbox-linux-amd64/bin/cbuild /__w/AVH-MLOps/AVH-MLOps/mlek-kws/MLOps.csolution.yml --packs --context +CM55_Ethos --toolchain AC6" + su - arm_mlops_docker -c "/home/arm_mlops_docker/cmsis-toolbox-linux-amd64/bin/cbuild /__w/AVH-MLOps/AVH-MLOps/mlek-kws/MLOps.csolution.yml --packs --active CM55_Ethos --toolchain AC6" else - su - arm_mlops_docker -c "/home/arm_mlops_docker/cmsis-toolbox-linux-amd64/bin/cbuild /__w/AVH-MLOps/AVH-MLOps/mlek-kws/MLOps.csolution.yml --packs --context +CM4 --toolchain AC6" + su - arm_mlops_docker -c "/home/arm_mlops_docker/cmsis-toolbox-linux-amd64/bin/cbuild /__w/AVH-MLOps/AVH-MLOps/mlek-kws/MLOps.csolution.yml --packs --active CM4 --toolchain AC6" fi - name: Execute Test Project on Arm Virtual Hardware FVP run: | if [ -z "${{ secrets.ARM_UBL_LICENSE_IDENTIFIER }}" ]; then - su - arm_mlops_docker -c "/home/arm_mlops_docker/avh-fvp-11.22.39/avh-linux-x86/bin/FVP_Corstone_SSE-300_Ethos-U55 -f /__w/AVH-MLOps/AVH-MLOps/mlek-kws/Target/CM55_Ethos/fvp_config.txt /__w/AVH-MLOps/AVH-MLOps/mlek-kws/out/ML_Test/CM55_Ethos/size/ML_Test.axf -C ethosu.num_macs=256 -Q 1 --simlimit 12" + su - arm_mlops_docker -c "/home/arm_mlops_docker/avh-fvp-11.29.27/bin/FVP_Corstone_SSE-300_Ethos-U55 -f /__w/AVH-MLOps/AVH-MLOps/mlek-kws/Target/CM55_Ethos/fvp_config.txt /__w/AVH-MLOps/AVH-MLOps/mlek-kws/out/ML_Test/CM55_Ethos/balanced/ML_Test.axf -C ethosu.num_macs=256 -Q 1 --simlimit 12" else - su - arm_mlops_docker -c "/home/arm_mlops_docker/avh-fvp-11.22.39/avh-linux-x86/bin/FVP_MPS2_Cortex-M4 -f /__w/AVH-MLOps/AVH-MLOps/TFLmicrospeech/Target/CM4/fvp_config.txt /__w/AVH-MLOps/AVH-MLOps/mlek-kws/out/ML_Test/CM4/size/ML_Test.axf -Q 1 --simlimit 12" + su - arm_mlops_docker -c "/home/arm_mlops_docker/avh-fvp-11.29.27/bin/FVP_MPS2_Cortex-M4 -f /__w/AVH-MLOps/AVH-MLOps/TFLmicrospeech/Target/CM4/fvp_config.txt /__w/AVH-MLOps/AVH-MLOps/mlek-kws/out/ML_Test/CM4/balanced/ML_Test.axf -Q 1 --simlimit 12" fi - name: Get timings from Event Recorder Log diff --git a/.github/workflows/build_TFLmicrospeech.yml b/.github/workflows/build_TFLmicrospeech.yml index d36bd78..da00cad 100644 --- a/.github/workflows/build_TFLmicrospeech.yml +++ b/.github/workflows/build_TFLmicrospeech.yml @@ -32,25 +32,12 @@ jobs: # Set permissions for the working directory to avoid permission errors run: chmod 777 -R /__w - - name: Install custom CMSIS packs - # Install custom CMSIS packs required for the ML project - run: | - wget -P /home/arm_mlops_docker https://github.com/ARM-software/CMSIS_6/releases/download/dev%2Fv6.0.0-dev35/ARM.CMSIS.6.0.0-dev35+geb1d42a.pack -nv - su -l arm_mlops_docker -c "/home/arm_mlops_docker/cmsis-toolbox-linux-amd64/bin/cpackget add ARM.CMSIS.6.0.0-dev35+geb1d42a.pack --agree-embedded-license" - wget -P /home/arm_mlops_docker https://github.com/ARM-software/Cortex_DFP/releases/download/dev%2Fv1.0.0-dev15/ARM.Cortex_DFP.1.0.0-dev15+gf6802e4.pack -nv - su -l arm_mlops_docker -c "/home/arm_mlops_docker/cmsis-toolbox-linux-amd64/bin/cpackget add ARM.Cortex_DFP.1.0.0-dev15+gf6802e4.pack --agree-embedded-license" - - - name: Build Model for Cortex-M55 with AC6 (size) - # Build the ML model for Cortex-M55 using AC6 toolchain and size optimization - run: | - su - arm_mlops_docker -c "/home/arm_mlops_docker/cmsis-toolbox-linux-amd64/bin/cbuild /__w/AVH-MLOps/AVH-MLOps/TFLmicrospeech/MLOps.csolution.yml --packs --context ML_Model.size+CM55 --toolchain AC6" - - - name: Build Test Project for Cortex-M55 with AC6 (size) - # Build the test project for Cortex-M55 using AC6 toolchain and size optimization + - name: Build Model and Test Project for Cortex-M55 with Ethos-U55 with AC6 (balanced) + # Build the ML model for Cortex-M55 with Ethos-U55 using AC6 toolchain run: | - su - arm_mlops_docker -c "/home/arm_mlops_docker/cmsis-toolbox-linux-amd64/bin/cbuild /__w/AVH-MLOps/AVH-MLOps/TFLmicrospeech/MLOps.csolution.yml --packs --context ML_Test.size+CM55 --toolchain AC6" + su - arm_mlops_docker -c "/home/arm_mlops_docker/cmsis-toolbox-linux-amd64/bin/cbuild /__w/AVH-MLOps/AVH-MLOps/TFLmicrospeech/MLOps.csolution.yml --packs --active CM55_Ethos --toolchain AC6" - - name: Execute Test Project on Cortex-M55 Arm Virtual Hardware FVP - # Execute the test project on Cortex-M55 Arm Virtual Hardware FVP + - name: Execute Test Project on Cortex-M55 with Ethos-U55 Arm Virtual Hardware FVP + # Execute the test project on Cortex-M55 with Ethos-U55 Arm Virtual Hardware FVP run: | - su - arm_mlops_docker -c "/home/arm_mlops_docker/avh-fvp-11.22.39/avh-linux-x86/bin/FVP_Corstone_SSE-300_Ethos-U55 -f /__w/AVH-MLOps/AVH-MLOps/TFLmicrospeech/Target/CM55_Ethos/fvp_config.txt /__w/AVH-MLOps/AVH-MLOps/TFLmicrospeech/out/ML_Test/CM55/size/ML_Test.axf --simlimit 12" + su - arm_mlops_docker -c "/home/arm_mlops_docker/avh-fvp-11.29.27/bin/FVP_Corstone_SSE-300_Ethos-U55 -f /__w/AVH-MLOps/AVH-MLOps/TFLmicrospeech/Target/CM55_Ethos/fvp_config.txt /__w/AVH-MLOps/AVH-MLOps/TFLmicrospeech/out/ML_Test/CM55_Ethos/balanced/ML_Test.axf --simlimit 12" diff --git a/.github/workflows/licensed_image_test.yml b/.github/workflows/licensed_image_test.yml index 7e57fa7..52e230c 100644 --- a/.github/workflows/licensed_image_test.yml +++ b/.github/workflows/licensed_image_test.yml @@ -37,7 +37,7 @@ jobs: - name: Run test command in Docker container for arm-llvm # Test if the clang command is working in the Docker container - run: su -l arm_mlops_docker -c "/home/arm_mlops_docker/LLVMEmbeddedToolchainForArm-16.0.0-Linux-x86_64/bin/clang --target=armv7m-none-eabi --version" + run: su -l arm_mlops_docker -c "/home/arm_mlops_docker/LLVM-ET-Arm-19.1.5-Linux-x86_64/bin/clang --target=armv7m-none-eabi --version" - name: Run test command in Docker container for GNU Compiler # Test if the arm-none-eabi-gcc command is working in the Docker container diff --git a/README.md b/README.md index 5838982..8d27af9 100644 --- a/README.md +++ b/README.md @@ -1,3 +1,12 @@ +[![License](https://img.shields.io/github/license/ARM-software/AVH-MLOps?label)](https://github.com/Arm-Examples/AVH-Hello/blob/main/LICENSE) +[![Base Docker Image - Build and Push](https://img.shields.io/github/actions/workflow/status/ARM-software/AVH-MLOps/base_image_build.yml?logo=arm&logoColor=0091bd&label=Base%20Docker%20Image%20-%20Build%20and%20Push)](https://github.com//ARM-software/AVH-MLOps/tree/main/.github/workflows/base_image_build.yml)[![Licensed Docker Image - Build and Push](https://img.shields.io/github/actions/workflow/status/ARM-software/AVH-MLOps/licensed_image_build.yml?logo=arm&logoColor=0091bd&label=Licensed%20Docker%20Image%20-%20Build%20and%20Push)](https://github.com//ARM-software/AVH-MLOps/tree/main/.github/workflows/licensed_image_build.yml) +[![Licensed Docker Image - Test](https://img.shields.io/github/actions/workflow/status/ARM-software/AVH-MLOps/licensed_image_test.yml?logo=arm&logoColor=0091bd&label=Licensed%20Docker%20Image%20-%20Test)](https://github.com//ARM-software/AVH-MLOps/tree/main/.github/workflows/licensed_image_test.yml) + + +[![MLEK_kws - Build and Run on AVH](https://img.shields.io/github/actions/workflow/status/ARM-software/AVH-MLOps/build_MLEK_kws.yml?logo=arm&logoColor=0091bd&label=MLEK_kws%20-%20Build%20and%20Run%20on%20AVH)](https://github.com//ARM-software/AVH-MLOps/tree/main/.github/workflows/build_MLEK_kws.yml) +[![QeexoAutoML - Build and Run on AVH](https://img.shields.io/github/actions/workflow/status/ARM-software/AVH-MLOps/build_QeexoML.yml?logo=arm&logoColor=0091bd&label=QeexoAutoML%20-%20Build%20and%20Run%20on%20AVH)](https://github.com//ARM-software/AVH-MLOps/tree/main/.github/workflows/build_QeexoML.yml) +[![TFLmicrospeech - Build and Run on AVH](https://img.shields.io/github/actions/workflow/status/ARM-software/AVH-MLOps/build_TFLmicrospeech.yml?logo=arm&logoColor=0091bd&label=TFLmicrospeech%20-%20Build%20and%20Run%20on%20AVH)](https://github.com//ARM-software/AVH-MLOps/tree/main/.github/workflows/build_TFLmicrospeech.yml) + # Foundation Components for MLOps Systems Arm provides a set of foundation tools and software components to enable MLOps systems and the overall development flow for machine learning applications. @@ -10,6 +19,14 @@ This repository contains: Refer to the [**ML Developers Guide for Cortex-M Processors and Ethos-U NPU**](https://developer.arm.com/documentation/109267/latest/) for more information. +## Quick Start + +1. Install [Keil Studio for VS Code](https://marketplace.visualstudio.com/items?itemName=Arm.keil-studio-pack) from the VS Code marketplace. +2. In VS Code, either clone this Git repository or (if downloaded as ZIP file) open the top-level folder. +3. Open the [CMSIS View](https://mdk-packs.github.io/vscode-cmsis-solution-docs/userinterface.html#2-main-area-of-the-cmsis-view) in VS Code and use the ... menu to choose an example via Select Active Solution from workspace. +4. The related tools and software packs are downloaded and installed. Review progress with View - Output - CMSIS Solution. +5. In the CMSIS view, use the [Action buttons](https://github.com/ARM-software/vscode-cmsis-csolution?tab=readme-ov-file#action-buttons) to build, load and debug the example on the hardware. + ## Directory Structure Directory | Description @@ -38,13 +55,17 @@ URL / Tool | Description Four workflows examplify a typical MLOps cycle with the Arm provided Foundation Components for MLOps. -**Base Docker Image - Build and Push (base_image_build.yml)**: Build a docker image that has all tools mentioned before installed and configured. It will be stored on the Github docker registry for fast access to the image. +**Base Docker Image - Build and Push (base_image_build.yml)**:
+Build a docker image that has all tools mentioned before installed and configured. It will be stored on the Github docker registry for fast access to the image. -**Licensed Docker Image - Build and Push (licensed_image_build.yml)**: Based on the Base docker image, this workflow adds your own license supplied by Arm for the commercial tools. It will also be stored on the Github docker registry. It will be build nightly and will be the image that actual container run-times will be spawned from. +**Licensed Docker Image - Build and Push (licensed_image_build.yml)**:
+Based on the Base docker image, this workflow adds your own license supplied by Arm for the commercial tools. It will also be stored on the Github docker registry. It will be build nightly and will be the image that actual container run-times will be spawned from. -**Licensed Docker Image - Test (test_licensed_image.yml)**: Test the docker image with a simplified workflow. +**Licensed Docker Image - Test (licensed_image_test.yml)**:
+Test the docker image with a simplified workflow. -**ML Project - Build and Run on Arm Virtual Hardware FVP (build_ml_library.yml)**: More complex example of a end to end workflow from building a ML Library, test project and to execute it on Arm Virtual Hardware. +**ML Project - Build and Run on Arm Virtual Hardware FVP (build_ml_library.yml)**:
+More complex example of a end to end workflow from building a ML Library, test project and to execute it on Arm Virtual Hardware. ## Customize this repository diff --git a/TFLmicrospeech/Model/RTE/Machine_Learning/debug_log.cpp.base@1.22.5-rc4 b/TFLmicrospeech/Model/RTE/Machine_Learning/debug_log.cpp.base@1.22.5-rc4 new file mode 100644 index 0000000..bc79d43 --- /dev/null +++ b/TFLmicrospeech/Model/RTE/Machine_Learning/debug_log.cpp.base@1.22.5-rc4 @@ -0,0 +1,43 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +// Implementation for the DebugLog() function that prints to the debug logger on +// an generic Cortex-M device. + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +#include "tensorflow/lite/micro/debug_log.h" + +#include "tensorflow/lite/micro/cortex_m_generic/debug_log_callback.h" + +static DebugLogCallback debug_log_callback = nullptr; + +void RegisterDebugLogCallback(void (*cb)(const char* s)) { + debug_log_callback = cb; +} + +void DebugLog(const char* s) { +#ifndef TF_LITE_STRIP_ERROR_STRINGS + if (debug_log_callback != nullptr) { + debug_log_callback(s); + } +#endif +} + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus diff --git a/TFLmicrospeech/Model/RTE/Machine_Learning/micro_time.cpp.base@1.22.5-rc4 b/TFLmicrospeech/Model/RTE/Machine_Learning/micro_time.cpp.base@1.22.5-rc4 new file mode 100644 index 0000000..023ac6d --- /dev/null +++ b/TFLmicrospeech/Model/RTE/Machine_Learning/micro_time.cpp.base@1.22.5-rc4 @@ -0,0 +1,67 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "tensorflow/lite/micro/micro_time.h" + +// DWT (Data Watchpoint and Trace) registers, only exists on ARM Cortex with a +// DWT unit. +#define KIN1_DWT_CONTROL (*((volatile uint32_t*)0xE0001000)) +/*!< DWT Control register */ + +// DWT Control register. +#define KIN1_DWT_CYCCNTENA_BIT (1UL << 0) + +// CYCCNTENA bit in DWT_CONTROL register. +#define KIN1_DWT_CYCCNT (*((volatile uint32_t*)0xE0001004)) + +// DWT Cycle Counter register. +#define KIN1_DEMCR (*((volatile uint32_t*)0xE000EDFC)) + +// DEMCR: Debug Exception and Monitor Control Register. +#define KIN1_TRCENA_BIT (1UL << 24) + +#define KIN1_LAR (*((volatile uint32_t*)0xE0001FB0)) + +#define KIN1_DWT_CONTROL (*((volatile uint32_t*)0xE0001000)) + +// Unlock access to DWT (ITM, etc.)registers. +#define KIN1_UnlockAccessToDWT() KIN1_LAR = 0xC5ACCE55; + +// TRCENA: Enable trace and debug block DEMCR (Debug Exception and Monitor +// Control Register. +#define KIN1_InitCycleCounter() KIN1_DEMCR |= KIN1_TRCENA_BIT + +#define KIN1_ResetCycleCounter() KIN1_DWT_CYCCNT = 0 +#define KIN1_EnableCycleCounter() KIN1_DWT_CONTROL |= KIN1_DWT_CYCCNTENA_BIT +#define KIN1_DisableCycleCounter() KIN1_DWT_CONTROL &= ~KIN1_DWT_CYCCNTENA_BIT +#define KIN1_GetCycleCounter() KIN1_DWT_CYCCNT + +namespace tflite { + +int32_t ticks_per_second() { return 0; } + +int32_t GetCurrentTimeTicks() { + static bool is_initialized = false; + if (!is_initialized) { + KIN1_UnlockAccessToDWT(); + KIN1_InitCycleCounter(); + KIN1_ResetCycleCounter(); + KIN1_EnableCycleCounter(); + is_initialized = true; + } + return KIN1_GetCycleCounter(); +} + +} // namespace tflite diff --git a/TFLmicrospeech/Model/RTE/Machine_Learning/system_setup.cpp.base@1.22.5-rc4 b/TFLmicrospeech/Model/RTE/Machine_Learning/system_setup.cpp.base@1.22.5-rc4 new file mode 100644 index 0000000..db4a100 --- /dev/null +++ b/TFLmicrospeech/Model/RTE/Machine_Learning/system_setup.cpp.base@1.22.5-rc4 @@ -0,0 +1,25 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "tensorflow/lite/micro/system_setup.h" + +namespace tflite { + +// To add an equivalent function for your own platform, create your own +// implementation file, and place it in a subfolder named after the target. See +// tensorflow/lite/micro/debug_log.cc for a similar example. +void InitializeTarget() {} + +} // namespace tflite diff --git a/TFLmicrospeech/Target/CM55/RTE/Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0 b/TFLmicrospeech/Target/CM55/RTE/Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0 new file mode 100644 index 0000000..6f84bd3 --- /dev/null +++ b/TFLmicrospeech/Target/CM55/RTE/Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0 @@ -0,0 +1,123 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc +; command above MUST be in first line (no comment above!) + +;Note: Add '-mcmse' to first line if your software model is "Secure Mode". +; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse + + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/*--------------------- CMSE Veneer Configuration --------------------------- +; CMSE Veneer Configuration +; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> +; + *----------------------------------------------------------------------------*/ +#define __CMSEVENEER_SIZE 0x200 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE ( 8 ) +#else +#define __STACKSEAL_SIZE ( 0 ) +#endif + + +/*---------------------------------------------------------------------------- + Region base & size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) +#define __CV_SIZE ( __CMSEVENEER_SIZE ) +#else +#define __CV_SIZE ( 0 ) +#endif + +#define __RO_BASE ( __ROM_BASE ) +#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) + +#define __RW_BASE ( __RAM_BASE ) +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) + + +/*---------------------------------------------------------------------------- + Scatter Region definition + *----------------------------------------------------------------------------*/ +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_NOINIT __RW_BASE UNINIT __RW_SIZE { + *(.bss.noinit) + } + + RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { + *(+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack + } +#endif +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers + ER_CMSE_VENEER __CV_BASE __CV_SIZE { + *(Veneer$$CMSE) + } +} +#endif diff --git a/TFLmicrospeech/Target/CM55/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 b/TFLmicrospeech/Target/CM55/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 new file mode 100644 index 0000000..0557c5f --- /dev/null +++ b/TFLmicrospeech/Target/CM55/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 @@ -0,0 +1,164 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS-Core Device Startup File for Cortex-M55 Device + * @version V1.1.0 + * @date 16. December 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint32_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/TFLmicrospeech/Target/CM55/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 b/TFLmicrospeech/Target/CM55/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 new file mode 100644 index 0000000..dc329c7 --- /dev/null +++ b/TFLmicrospeech/Target/CM55/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 @@ -0,0 +1,107 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.1.0 + * @date 28. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/TFLmicrospeech/Target/CM55_Ethos/RTE/Device/ARMCM55/ARMCM55_ac6.sct b/TFLmicrospeech/Target/CM55_Ethos/RTE/Device/ARMCM55/ARMCM55_ac6.sct new file mode 100644 index 0000000..6f84bd3 --- /dev/null +++ b/TFLmicrospeech/Target/CM55_Ethos/RTE/Device/ARMCM55/ARMCM55_ac6.sct @@ -0,0 +1,123 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc +; command above MUST be in first line (no comment above!) + +;Note: Add '-mcmse' to first line if your software model is "Secure Mode". +; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse + + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/*--------------------- CMSE Veneer Configuration --------------------------- +; CMSE Veneer Configuration +; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> +; + *----------------------------------------------------------------------------*/ +#define __CMSEVENEER_SIZE 0x200 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE ( 8 ) +#else +#define __STACKSEAL_SIZE ( 0 ) +#endif + + +/*---------------------------------------------------------------------------- + Region base & size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) +#define __CV_SIZE ( __CMSEVENEER_SIZE ) +#else +#define __CV_SIZE ( 0 ) +#endif + +#define __RO_BASE ( __ROM_BASE ) +#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) + +#define __RW_BASE ( __RAM_BASE ) +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) + + +/*---------------------------------------------------------------------------- + Scatter Region definition + *----------------------------------------------------------------------------*/ +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_NOINIT __RW_BASE UNINIT __RW_SIZE { + *(.bss.noinit) + } + + RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { + *(+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack + } +#endif +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers + ER_CMSE_VENEER __CV_BASE __CV_SIZE { + *(Veneer$$CMSE) + } +} +#endif diff --git a/TFLmicrospeech/Target/CM55_Ethos/RTE/Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0 b/TFLmicrospeech/Target/CM55_Ethos/RTE/Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0 new file mode 100644 index 0000000..6f84bd3 --- /dev/null +++ b/TFLmicrospeech/Target/CM55_Ethos/RTE/Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0 @@ -0,0 +1,123 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc +; command above MUST be in first line (no comment above!) + +;Note: Add '-mcmse' to first line if your software model is "Secure Mode". +; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse + + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/*--------------------- CMSE Veneer Configuration --------------------------- +; CMSE Veneer Configuration +; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> +; + *----------------------------------------------------------------------------*/ +#define __CMSEVENEER_SIZE 0x200 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE ( 8 ) +#else +#define __STACKSEAL_SIZE ( 0 ) +#endif + + +/*---------------------------------------------------------------------------- + Region base & size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) +#define __CV_SIZE ( __CMSEVENEER_SIZE ) +#else +#define __CV_SIZE ( 0 ) +#endif + +#define __RO_BASE ( __ROM_BASE ) +#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) + +#define __RW_BASE ( __RAM_BASE ) +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) + + +/*---------------------------------------------------------------------------- + Scatter Region definition + *----------------------------------------------------------------------------*/ +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_NOINIT __RW_BASE UNINIT __RW_SIZE { + *(.bss.noinit) + } + + RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { + *(+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack + } +#endif +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers + ER_CMSE_VENEER __CV_BASE __CV_SIZE { + *(Veneer$$CMSE) + } +} +#endif diff --git a/TFLmicrospeech/Target/CM55_Ethos/RTE/Device/ARMCM55/ac6_linker_script.sct.src b/TFLmicrospeech/Target/CM55_Ethos/RTE/Device/ARMCM55/ac6_linker_script.sct.src new file mode 100644 index 0000000..7820e1f --- /dev/null +++ b/TFLmicrospeech/Target/CM55_Ethos/RTE/Device/ARMCM55/ac6_linker_script.sct.src @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE 8 +#else +#define __STACKSEAL_SIZE 0 +#endif + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ + +LR_ROM0 __ROM0_BASE __ROM0_SIZE { + + ER_ROM0 __ROM0_BASE __ROM0_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + *(+RO +XO) + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + ER_CMSE_VENEER AlignExpr(+0, 32) (__ROM0_SIZE - AlignExpr(ImageLength(ER_ROM0), 32)) { + *(Veneer$$CMSE) + } +#endif + + RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { + *.o(.bss.noinit) + *.o(.bss.noinit.*) + } + + RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { + *(+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if __STACKSEAL_SIZE > 0 + STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack + } +#endif + +#if __RAM1_SIZE > 0 + RW_RAM1 __RAM1_BASE __RAM1_SIZE { + .ANY (+RW +ZI) + } +#endif + +#if __RAM2_SIZE > 0 + RW_RAM2 __RAM2_BASE __RAM2_SIZE { + .ANY (+RW +ZI) + } +#endif + +#if __RAM3_SIZE > 0 + RW_RAM3 __RAM3_BASE __RAM3_SIZE { + .ANY (+RW +ZI) + } +#endif +} + +#if __ROM1_SIZE > 0 +LR_ROM1 __ROM1_BASE __ROM1_SIZE { + ER_ROM1 +0 __ROM1_SIZE { + .ANY (+RO +XO) + } +} +#endif + +#if __ROM2_SIZE > 0 +LR_ROM2 __ROM2_BASE __ROM2_SIZE { + ER_ROM2 +0 __ROM2_SIZE { + .ANY (+RO +XO) + } +} +#endif + +#if __ROM3_SIZE > 0 +LR_ROM3 __ROM3_BASE __ROM3_SIZE { + ER_ROM3 +0 __ROM3_SIZE { + .ANY (+RO +XO) + } +} +#endif diff --git a/TFLmicrospeech/Target/CM55_Ethos/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 b/TFLmicrospeech/Target/CM55_Ethos/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 new file mode 100644 index 0000000..0557c5f --- /dev/null +++ b/TFLmicrospeech/Target/CM55_Ethos/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 @@ -0,0 +1,164 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS-Core Device Startup File for Cortex-M55 Device + * @version V1.1.0 + * @date 16. December 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint32_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/TFLmicrospeech/Target/CM55_Ethos/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 b/TFLmicrospeech/Target/CM55_Ethos/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 new file mode 100644 index 0000000..dc329c7 --- /dev/null +++ b/TFLmicrospeech/Target/CM55_Ethos/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 @@ -0,0 +1,107 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.1.0 + * @date 28. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/TFLmicrospeech/Test/RTE/CMSIS-View/EventRecorderConf.h.base@1.1.0 b/TFLmicrospeech/Test/RTE/CMSIS-View/EventRecorderConf.h.base@1.1.0 new file mode 100644 index 0000000..9802f2a --- /dev/null +++ b/TFLmicrospeech/Test/RTE/CMSIS-View/EventRecorderConf.h.base@1.1.0 @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2016-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: EventRecorderConf.h + * Purpose: Event Recorder software component configuration options + * Rev.: V1.1.0 + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Event Recorder + +// Number of Records +// <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 +// <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 +// <65536=>65536 +// Configures size of Event Record Buffer (each record is 16 bytes) +// Must be 2^n (min=8, max=65536) +#define EVENT_RECORD_COUNT 64U + +// Time Stamp Source +// <0=> DWT Cycle Counter <1=> SysTick <2=> CMSIS-RTOS2 System Timer +// <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) +// Selects source for 32-bit time stamp +#define EVENT_TIMESTAMP_SOURCE 0 + +// Time Stamp Clock Frequency [Hz] <0-1000000000> +// Defines initial time stamp clock frequency (0 when not used) +#define EVENT_TIMESTAMP_FREQ 0U + +// + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/docker_base/armllvm_install.sh b/docker_base/armllvm_install.sh index 03d9a02..4cd1eb6 100644 --- a/docker_base/armllvm_install.sh +++ b/docker_base/armllvm_install.sh @@ -1,5 +1,5 @@ -wget https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-16.0.0/LLVMEmbeddedToolchainForArm-16.0.0-Linux-x86_64.tar.gz -nv -tar -xf LLVMEmbeddedToolchainForArm-16.0.0-Linux-x86_64.tar.gz -C /home/arm_mlops_docker +wget https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-19.1.5/LLVM-ET-Arm-19.1.5-Linux-x86_64.tar.xz -nv +tar -xf LLVM-ET-Arm-19.1.5-Linux-x86_64.tar.xz -C /home/arm_mlops_docker apt install -y libtinfo5 -#echo 'export "/home/arm_mlops_docker/LLVMEmbeddedToolchainForArm-16.0.0-Linux-x86_64/bin:$PATH"' >> /home/arm_mlops_docker/.bashrc -chown -R arm_mlops_docker /home/arm_mlops_docker/LLVMEmbeddedToolchainForArm-16.0.0-Linux-x86_64 \ No newline at end of file +#echo 'export "/home/arm_mlops_docker/LLVM-ET-Arm-19.1.5-Linux-x86_64/bin:$PATH"' >> /home/arm_mlops_docker/.bashrc +chown -R arm_mlops_docker /home/arm_mlops_docker/LLVM-ET-Arm-19.1.5-Linux-x86_64 \ No newline at end of file diff --git a/docker_base/avh-fvp_install.sh b/docker_base/avh-fvp_install.sh index da4ba7c..25fc45c 100644 --- a/docker_base/avh-fvp_install.sh +++ b/docker_base/avh-fvp_install.sh @@ -1,5 +1,5 @@ -wget https://artifacts.tools.arm.com/avh/11.22.39/avh-fvp-linux-amd64.tar.gz -nv -mkdir /home/arm_mlops_docker/avh-fvp-11.22.39 -tar -xvf avh-fvp-linux-amd64.tar.gz -C /home/arm_mlops_docker/avh-fvp-11.22.39 -rm /home/arm_mlops_docker/avh-fvp-11.22.39/avh-linux-x86/bin/models/libpython3.9.so.1.0 -chmod 0755 /home/arm_mlops_docker/avh-fvp-11.22.39 -R +wget https://artifacts.tools.arm.com/avh/11.29.27/avh-linux-x86_11.29_27_Linux64.tgz -nv +mkdir /home/arm_mlops_docker/avh-fvp-11.29.27 +tar -xzf avh-linux-x86_11.29_27_Linux64.tgz -C /home/arm_mlops_docker/avh-fvp-11.29.27 --strip-components=1 +rm /home/arm_mlops_docker/avh-fvp-11.29.27/avh-linux-x86/bin/models/libpython3.9.so.1.0 +chmod 0755 /home/arm_mlops_docker/avh-fvp-11.29.27 -R diff --git a/docker_base/cmsistoolbox_install.sh b/docker_base/cmsistoolbox_install.sh index 8024551..31ea82c 100644 --- a/docker_base/cmsistoolbox_install.sh +++ b/docker_base/cmsistoolbox_install.sh @@ -1,4 +1,4 @@ -wget https://artifacts.tools.arm.com/cmsis-toolbox/2.1.0/cmsis-toolbox-linux-amd64.tar.gz -nv +wget https://artifacts.tools.arm.com/cmsis-toolbox/2.11.0/cmsis-toolbox-linux-amd64.tar.gz -nv wget https://github.com/Kitware/CMake/releases/download/v3.27.4/cmake-3.27.4-linux-x86_64.sh -nv tar -xf cmsis-toolbox-linux-amd64.tar.gz -C /home/arm_mlops_docker chmod +x cmake-3.27.4-linux-x86_64.sh diff --git a/docker_base/vela_install.sh b/docker_base/vela_install.sh index cf05ee7..b805cfe 100644 --- a/docker_base/vela_install.sh +++ b/docker_base/vela_install.sh @@ -4,3 +4,42 @@ pip install numpy==1.21.3 --force pip install "setuptools_scm[toml]<6" wheel pip3 install ethos-u-vela --no-build-isolation --no-cache-dir apt-get install -y --no-install-recommends libpython3.9 +# Basic build tools +apt-get install -y --no-install-recommends \ + build-essential \ + ninja-build \ + git \ + curl \ + wget \ + unzip \ + rsync + +# ARM cross-compilation toolchain +apt-get install -y --no-install-recommends \ + gcc-arm-none-eabi \ + libnewlib-arm-none-eabi + +# Additional build dependencies for ExecuTorch +apt-get install -y --no-install-recommends \ + pkg-config \ + libffi-dev \ + libssl-dev \ + zlib1g-dev \ + libbz2-dev \ + libreadline-dev \ + libsqlite3-dev \ + libncurses5-dev \ + libncursesw5-dev \ + xz-utils \ + tk-dev \ + libxml2-dev \ + libxmlsec1-dev \ + liblzma-dev + +# Additional utilities +apt-get install -y --no-install-recommends \ + vim \ + nano \ + tree + +rm -rf /var/lib/apt/lists/* diff --git a/mlek-kws/.cmsis/MLOps+CM55_Ethos.dbgconf b/mlek-kws/.cmsis/MLOps+CM55_Ethos.dbgconf new file mode 100644 index 0000000..d79f207 --- /dev/null +++ b/mlek-kws/.cmsis/MLOps+CM55_Ethos.dbgconf @@ -0,0 +1,13 @@ +// <<< Use Configuration Wizard in Context Menu >>> + +// Fixed Debug Authentication +// Use a fixed value for Debug Authentication. Only secure debug authentication configurable. +DAuthFixed = 0x1; + +// Secure Invasive Debug +// Secure Non-Invasive Debug +DAuthConfig = 0xF; + +// + +// <<< end of configuration section >>> \ No newline at end of file diff --git a/mlek-kws/.cmsis/MLOps+CM55_Ethos.dbgconf.base@0.0.0 b/mlek-kws/.cmsis/MLOps+CM55_Ethos.dbgconf.base@0.0.0 new file mode 100644 index 0000000..d79f207 --- /dev/null +++ b/mlek-kws/.cmsis/MLOps+CM55_Ethos.dbgconf.base@0.0.0 @@ -0,0 +1,13 @@ +// <<< Use Configuration Wizard in Context Menu >>> + +// Fixed Debug Authentication +// Use a fixed value for Debug Authentication. Only secure debug authentication configurable. +DAuthFixed = 0x1; + +// Secure Invasive Debug +// Secure Non-Invasive Debug +DAuthConfig = 0xF; + +// + +// <<< end of configuration section >>> \ No newline at end of file diff --git a/mlek-kws/Model/ML_Model.cproject.yml b/mlek-kws/Model/ML_Model.cproject.yml index 3d7fd20..473c23d 100644 --- a/mlek-kws/Model/ML_Model.cproject.yml +++ b/mlek-kws/Model/ML_Model.cproject.yml @@ -6,7 +6,7 @@ project: - pack: ARM::CMSIS@>=6.0.0-dev0 - pack: ARM::CMSIS-DSP@1.15.0 - pack: ARM::CMSIS-NN@4.0.0 - - pack: Arm::ethos-u-core-driver@1.22.8 + - pack: ARM::ethos-u-core-driver@1.25.2 - pack: ARM::ml-embedded-eval-kit-uc-api@22.8.0-Beta - pack: tensorflow::flatbuffers@1.22.8 - pack: tensorflow::gemmlowp@1.22.8 @@ -56,10 +56,10 @@ project: - +CM85_Ethos - component: tensorflow::Machine Learning:TensorFlow:Kernel Utils - component: tensorflow::Machine Learning:TensorFlow:Testing - - component: Arm::Machine Learning:NPU Support:Ethos-U Driver&Generic U55 + - component: ARM::Machine Learning:NPU Support:Ethos-U Driver&Generic U55 for-context: - +CM55_Ethos - - component: Arm::Machine Learning:NPU Support:Ethos-U Driver&Generic U65 + - component: ARM::Machine Learning:NPU Support:Ethos-U Driver&Generic U65 for-context: - +CM85_Ethos - component: ARM::ML Eval Kit:Common:API diff --git a/mlek-kws/Model/RTE/Machine_Learning/debug_log.cpp.base@1.22.8 b/mlek-kws/Model/RTE/Machine_Learning/debug_log.cpp.base@1.22.8 new file mode 100644 index 0000000..bc79d43 --- /dev/null +++ b/mlek-kws/Model/RTE/Machine_Learning/debug_log.cpp.base@1.22.8 @@ -0,0 +1,43 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +// Implementation for the DebugLog() function that prints to the debug logger on +// an generic Cortex-M device. + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +#include "tensorflow/lite/micro/debug_log.h" + +#include "tensorflow/lite/micro/cortex_m_generic/debug_log_callback.h" + +static DebugLogCallback debug_log_callback = nullptr; + +void RegisterDebugLogCallback(void (*cb)(const char* s)) { + debug_log_callback = cb; +} + +void DebugLog(const char* s) { +#ifndef TF_LITE_STRIP_ERROR_STRINGS + if (debug_log_callback != nullptr) { + debug_log_callback(s); + } +#endif +} + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus diff --git a/mlek-kws/Model/RTE/Machine_Learning/micro_time.cpp.base@1.22.8 b/mlek-kws/Model/RTE/Machine_Learning/micro_time.cpp.base@1.22.8 new file mode 100644 index 0000000..8842180 --- /dev/null +++ b/mlek-kws/Model/RTE/Machine_Learning/micro_time.cpp.base@1.22.8 @@ -0,0 +1,69 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "tensorflow/lite/micro/micro_time.h" + +// Set in micro/tools/make/targets/cortex_m_generic_makefile.inc. +// Needed for the DWT and PMU counters. +#ifdef CMSIS_DEVICE_ARM_CORTEX_M_XX_HEADER_FILE +#include CMSIS_DEVICE_ARM_CORTEX_M_XX_HEADER_FILE +#endif + +namespace tflite { + +uint32_t ticks_per_second() { return 0; } + +uint32_t GetCurrentTimeTicks() { + static bool is_initialized = false; + + if (!is_initialized) { +#if (!defined(TF_LITE_STRIP_ERROR_STRINGS) && !defined(ARMCM0) && \ + !defined(ARMCM0plus)) +#ifdef ARM_MODEL_USE_PMU_COUNTERS + ARM_PMU_Enable(); + DCB->DEMCR |= DCB_DEMCR_TRCENA_Msk; + + ARM_PMU_CYCCNT_Reset(); + ARM_PMU_CNTR_Enable(PMU_CNTENSET_CCNTR_ENABLE_Msk); + +#else +#ifdef ARMCM7 + DWT->LAR = 0xC5ACCE55; +#endif + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + + // Reset and DWT cycle counter. + DWT->CYCCNT = 0; + DWT->CTRL |= 1UL; + +#endif +#endif + + is_initialized = true; + } + +#if (!defined(TF_LITE_STRIP_ERROR_STRINGS) && !defined(ARMCM0) && \ + !defined(ARMCM0plus)) +#ifdef ARM_MODEL_USE_PMU_COUNTERS + return ARM_PMU_Get_CCNTR(); +#else + return DWT->CYCCNT; +#endif +#else + return 0; +#endif +} + +} // namespace tflite diff --git a/mlek-kws/Model/RTE/Machine_Learning/system_setup.cpp.base@1.22.8 b/mlek-kws/Model/RTE/Machine_Learning/system_setup.cpp.base@1.22.8 new file mode 100644 index 0000000..db4a100 --- /dev/null +++ b/mlek-kws/Model/RTE/Machine_Learning/system_setup.cpp.base@1.22.8 @@ -0,0 +1,25 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "tensorflow/lite/micro/system_setup.h" + +namespace tflite { + +// To add an equivalent function for your own platform, create your own +// implementation file, and place it in a subfolder named after the target. See +// tensorflow/lite/micro/debug_log.cc for a similar example. +void InitializeTarget() {} + +} // namespace tflite diff --git a/mlek-kws/Target/CM4/RTE/Device/ARMCM4/ARMCM4_ac6.sct b/mlek-kws/Target/CM4/RTE/Device/ARMCM4/ARMCM4_ac6.sct new file mode 100644 index 0000000..eb67b5f --- /dev/null +++ b/mlek-kws/Target/CM4/RTE/Device/ARMCM4/ARMCM4_ac6.sct @@ -0,0 +1,80 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m4 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_NOINIT __RW_BASE UNINIT __RW_SIZE { + *(.bss.noinit) + } + + RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { + *(+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/mlek-kws/Target/CM4/RTE/Device/ARMCM4/ac6_linker_script.sct.src b/mlek-kws/Target/CM4/RTE/Device/ARMCM4/ac6_linker_script.sct.src new file mode 100644 index 0000000..7820e1f --- /dev/null +++ b/mlek-kws/Target/CM4/RTE/Device/ARMCM4/ac6_linker_script.sct.src @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE 8 +#else +#define __STACKSEAL_SIZE 0 +#endif + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ + +LR_ROM0 __ROM0_BASE __ROM0_SIZE { + + ER_ROM0 __ROM0_BASE __ROM0_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + *(+RO +XO) + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + ER_CMSE_VENEER AlignExpr(+0, 32) (__ROM0_SIZE - AlignExpr(ImageLength(ER_ROM0), 32)) { + *(Veneer$$CMSE) + } +#endif + + RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { + *.o(.bss.noinit) + *.o(.bss.noinit.*) + } + + RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { + *(+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if __STACKSEAL_SIZE > 0 + STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack + } +#endif + +#if __RAM1_SIZE > 0 + RW_RAM1 __RAM1_BASE __RAM1_SIZE { + .ANY (+RW +ZI) + } +#endif + +#if __RAM2_SIZE > 0 + RW_RAM2 __RAM2_BASE __RAM2_SIZE { + .ANY (+RW +ZI) + } +#endif + +#if __RAM3_SIZE > 0 + RW_RAM3 __RAM3_BASE __RAM3_SIZE { + .ANY (+RW +ZI) + } +#endif +} + +#if __ROM1_SIZE > 0 +LR_ROM1 __ROM1_BASE __ROM1_SIZE { + ER_ROM1 +0 __ROM1_SIZE { + .ANY (+RO +XO) + } +} +#endif + +#if __ROM2_SIZE > 0 +LR_ROM2 __ROM2_BASE __ROM2_SIZE { + ER_ROM2 +0 __ROM2_SIZE { + .ANY (+RO +XO) + } +} +#endif + +#if __ROM3_SIZE > 0 +LR_ROM3 __ROM3_BASE __ROM3_SIZE { + ER_ROM3 +0 __ROM3_SIZE { + .ANY (+RO +XO) + } +} +#endif diff --git a/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0 b/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0 new file mode 100644 index 0000000..5bf4c86 --- /dev/null +++ b/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0 @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::Drivers:USART +#define RTE_USART0 1 + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::Drivers:USART +#define RTE_USART1 1 + +// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] +// Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC +#define RTE_ISRAM0_MPC 1 + +// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] +// Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC +#define RTE_ISRAM1_MPC 1 + +// MPC (Memory Protection Controller) [Driver_SRAM_MPC] +// Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC +#define RTE_SRAM_MPC 1 + +// MPC (Memory Protection Controller) [Driver_QSPI_MPC] +// Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC +#define RTE_QSPI_MPC 1 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0] +// Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN0 1 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP0 1 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP1 1 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0] +// Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH0 1 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1] +// Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH1 1 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP0 1 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP1 1 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP2 1 + +// Flash device emulated by SRAM [Driver_Flash0] +// Configuration settings for Driver_Flash0 in component ::Drivers:Flash +#define RTE_FLASH0 1 + +// I2C SBCon [Driver_I2C0] +// Configuration settings for Driver_I2C0 in component ::Drivers:I2C +#define RTE_I2C0 1 + +#endif /* __RTE_DEVICE_H */ diff --git a/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1 b/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1 new file mode 100644 index 0000000..bfc348f --- /dev/null +++ b/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1 @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_DRIVER_CONFIG_H__ +#define __CMSIS_DRIVER_CONFIG_H__ + +#include "system_SSE300MPS3.h" +#include "device_cfg.h" +#include "device_definition.h" +#include "platform_base_address.h" + +#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3 b/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3 new file mode 100644 index 0000000..2ff3eaa --- /dev/null +++ b/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3 @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2020-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S + +/* I2C_SBCon */ +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S + +/* I2S */ +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S + +/* ARM UART Controller PL011 */ +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S + +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S + +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S + +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S + +/** System Counter Armv8-M */ +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u + +/* System timer */ +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) + +/* CMSDK GPIO driver structures */ +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S + +/* System Watchdogs */ +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S + +/* ARM MPC SIE 300 driver structures */ +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S + +/* ARM PPC driver structures */ +#define PPC_SSE300_MAIN0_S +#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S +#define PPC_SSE300_MAIN_EXP0_S +#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S +#define PPC_SSE300_MAIN_EXP1_S +#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S +#define PPC_SSE300_MAIN_EXP2_S +#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S +#define PPC_SSE300_MAIN_EXP3_S +#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S +#define PPC_SSE300_PERIPH0_S +#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S +#define PPC_SSE300_PERIPH1_S +#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S +#define PPC_SSE300_PERIPH_EXP0_S +#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S +#define PPC_SSE300_PERIPH_EXP1_S +#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S +#define PPC_SSE300_PERIPH_EXP2_S +#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S +#define PPC_SSE300_PERIPH_EXP3_S +#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S + + +#endif /* __DEVICE_CFG_H__ */ diff --git a/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct.base@1.1.0 b/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct.base@1.1.0 new file mode 100644 index 0000000..343c63d --- /dev/null +++ b/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct.base@1.1.0 @@ -0,0 +1,78 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2021 Arm Limited. All rights reserved. +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +#include "region_defs.h" + +LR_CODE S_CODE_START { + ER_CODE S_CODE_START { + *.o (RESET +First) + .ANY (+RO) + } + + /* + * Place the CMSE Veneers (containing the SG instruction) after the code, in + * a separate 32 bytes aligned region so that the SAU can programmed to just + * set this region as Non-Secure Callable. The maximum size of this + * executable region makes it only used the space left over by the ER_CODE + * region so that you can rely on code+veneer size combined will not exceed + * the S_CODE_SIZE value. We also substract from the available space the + * area used to align this section on 32 bytes boundary (for SAU conf). + */ + ER_CODE_CMSE_VENEER +0 ALIGN 32 { + *(Veneer$$CMSE) + } + /* + * This dummy region ensures that the next one will be aligned on a 32 bytes + * boundary, so that the following region will not be mistakenly configured + * as Non-Secure Callable by the SAU. + */ + ER_CODE_CMSE_VENEER_DUMMY +0 ALIGN 32 EMPTY 0 {} + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + CODE_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) + + ER_DATA S_DATA_START { + .ANY (+ZI +RW) + } + + #if HEAP_SIZE > 0 + ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap + } + #endif + + ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE { ; Reserve empty region for stack + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + SRAM_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) +} diff --git a/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/platform_base_address.h.base@1.1.2 b/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/platform_base_address.h.base@1.1.2 new file mode 100644 index 0000000..b813097 --- /dev/null +++ b/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/platform_base_address.h.base@1.1.2 @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2019-2021 Arm Limited + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file platform_base_address.h + * \brief This file defines all the peripheral base addresses for AN552 MPS3 SSE-300 + + * Ethos-U55 platform. + */ + +#ifndef __PLATFORM_BASE_ADDRESS_H__ +#define __PLATFORM_BASE_ADDRESS_H__ + +/* ======= Defines peripherals memory map addresses ======= */ +/* Non-secure memory map addresses */ +#define ITCM_BASE_NS 0x00000000 /* Instruction TCM Non-Secure base address */ +#define SRAM_BASE_NS 0x01000000 /* CODE SRAM Non-Secure base address */ +#define DTCM0_BASE_NS 0x20000000 /* Data TCM block 0 Non-Secure base address */ +#define DTCM1_BASE_NS 0x20020000 /* Data TCM block 1 Non-Secure base address */ +#define DTCM2_BASE_NS 0x20040000 /* Data TCM block 2 Non-Secure base address */ +#define DTCM3_BASE_NS 0x20060000 /* Data TCM block 3 Non-Secure base address */ +#define ISRAM0_BASE_NS 0x21000000 /* Internal SRAM Area Non-Secure base address */ +#define ISRAM1_BASE_NS 0x21100000 /* Internal SRAM Area Non-Secure base address */ +#define QSPI_SRAM_BASE_NS 0x28000000 /* QSPI SRAM Non-Secure base address */ +/* Non-Secure Subsystem peripheral region */ +#define CPU0_PWRCTRL_BASE_NS 0x40012000 /* CPU 0 Power Control Block Non-Secure base address */ +#define CPU0_IDENTITY_BASE_NS 0x4001F000 /* CPU 0 Identity Block Non-Secure base address */ +#define SSE300_NSACFG_BASE_NS 0x40080000 /* SSE-300 Non-Secure Access Configuration Register Block Non-Secure base address */ +/* Non-Secure MSTEXPPILL Peripheral region */ +#define GPIO0_CMSDK_BASE_NS 0x41100000 /* GPIO 0 Non-Secure base address */ +#define GPIO1_CMSDK_BASE_NS 0x41101000 /* GPIO 1 Non-Secure base address */ +#define GPIO2_CMSDK_BASE_NS 0x41102000 /* GPIO 2 Non-Secure base address */ +#define GPIO3_CMSDK_BASE_NS 0x41103000 /* GPIO 3 Non-Secure base address */ +#define FMC_CMSDK_GPIO_0_BASE_NS 0x41104000 /* FMC CMSDK GPIO 0 Non-Secure base address */ +#define FMC_CMSDK_GPIO_1_BASE_NS 0x41105000 /* FMC CMSDK GPIO 1 Non-Secure base address */ +#define FMC_CMSDK_GPIO_2_BASE_NS 0x41106000 /* FMC CMSDK GPIO 2 Non-Secure base address */ +#define FMC_CMSDK_GPIO_3_BASE_NS 0x41107000 /* FMC CMSDK GPIO 3 Non-Secure base address */ +#define EXTERNAL_MANAGER_0_BASE_NS 0x41200000 /* External manager 0 (Unused) Non-Secure base address */ +#define EXTERNAL_MANAGER_1_BASE_NS 0x41201000 /* External manager 1 (Unused) Non-Secure base address */ +#define EXTERNAL_MANAGER_2_BASE_NS 0x41202000 /* External manager 2 (Unused) Non-Secure base address */ +#define EXTERNAL_MANAGER_3_BASE_NS 0x41203000 /* External manager 3 (Unused) Non-Secure base address */ +#define ETHERNET_BASE_NS 0x41400000 /* Ethernet Non-Secure base address */ +#define USB_BASE_NS 0x41500000 /* USB Non-Secure base address */ +#define USER_APB0_BASE_NS 0x41700000 /* User APB 0 Non-Secure base address */ +#define USER_APB1_BASE_NS 0x41701000 /* User APB 1 Non-Secure base address */ +#define USER_APB2_BASE_NS 0x41702000 /* User APB 2 Non-Secure base address */ +#define USER_APB3_BASE_NS 0x41703000 /* User APB 3 Non-Secure base address */ +#define QSPI_CONFIG_BASE_NS 0x41800000 /* QSPI Config Non-Secure base address */ +#define QSPI_WRITE_BASE_NS 0x41801000 /* QSPI Write Non-Secure base address */ +/* Non-Secure Subsystem peripheral region */ +#define SYSTIMER0_ARMV8_M_BASE_NS 0x48000000 /* System Timer 0 Non-Secure base address */ +#define SYSTIMER1_ARMV8_M_BASE_NS 0x48001000 /* System Timer 1 Non-Secure base address */ +#define SYSTIMER2_ARMV8_M_BASE_NS 0x48002000 /* System Timer 2 Non-Secure base address */ +#define SYSTIMER3_ARMV8_M_BASE_NS 0x48003000 /* System Timer 3 Non-Secure base address */ +#define SSE300_SYSINFO_BASE_NS 0x48020000 /* SSE-300 System info Block Non-Secure base address */ +#define SLOWCLK_TIMER_CMSDK_BASE_NS 0x4802F000 /* CMSDK based SLOWCLK Timer Non-Secure base address */ +#define SYSWDOG_ARMV8_M_CNTRL_BASE_NS 0x48040000 /* Non-Secure Watchdog Timer control frame Non-Secure base address */ +#define SYSWDOG_ARMV8_M_REFRESH_BASE_NS 0x48041000 /* Non-Secure Watchdog Timer refresh frame Non-Secure base address */ +#define SYSCNTR_READ_BASE_NS 0x48101000 /* System Counter Read Secure base address */ +/* Non-Secure MSTEXPPIHL Peripheral region */ +#define ETHOS_U55_APB_BASE_NS 0x48102000 /* Ethos-U55 APB Non-Secure base address */ +#define U55_TIMING_ADAPTER_0_BASE_NS 0x48103000 /* Ethos-U55 Timing Adapter 0 APB registers Non-Secure base address */ +#define U55_TIMING_ADAPTER_1_BASE_NS 0x48103200 /* Ethos-U55 Timing Adapter 1 APB registers Non-Secure base address */ +#define FPGA_SBCon_I2C_TOUCH_BASE_NS 0x49200000 /* FPGA - SBCon I2C (Touch) Non-Secure base address */ +#define FPGA_SBCon_I2C_AUDIO_BASE_NS 0x49201000 /* FPGA - SBCon I2C (Audio Conf) Non-Secure base address */ +#define FPGA_SPI_ADC_BASE_NS 0x49202000 /* FPGA - PL022 (SPI ADC) Non-Secure base address */ +#define FPGA_SPI_SHIELD0_BASE_NS 0x49203000 /* FPGA - PL022 (SPI Shield0) Non-Secure base address */ +#define FPGA_SPI_SHIELD1_BASE_NS 0x49204000 /* FPGA - PL022 (SPI Shield1) Non-Secure base address */ +#define SBCon_I2C_SHIELD0_BASE_NS 0x49205000 /* SBCon (I2C - Shield0) Non-Secure base address */ +#define SBCon_I2C_SHIELD1_BASE_NS 0x49206000 /* SBCon (I2C – Shield1) Non-Secure base address */ +#define USER_APB_BASE_NS 0x49207000 /* USER APB Non-Secure base address */ +#define FPGA_DDR4_EEPROM_BASE_NS 0x49208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Non-Secure base address */ +#define FMC_USER_APB0 0x4920C000 /* FMC User APB0 */ +#define FMC_USER_APB1 0x4920D000 /* FMC User APB1 */ +#define FMC_USER_APB2 0x4920E000 /* FMC User APB2 */ +#define FMC_USER_APB3 0x4920F000 /* FMC User APB3 */ +#define FPGA_SCC_BASE_NS 0x49300000 /* FPGA - SCC registers Non-Secure base address */ +#define FPGA_I2S_BASE_NS 0x49301000 /* FPGA - I2S (Audio) Non-Secure base address */ +#define FPGA_IO_BASE_NS 0x49302000 /* FPGA - IO (System Ctrl + I/O) Non-Secure base address */ +#define UART0_BASE_NS 0x49303000 /* UART 0 Non-Secure base address */ +#define UART1_BASE_NS 0x49304000 /* UART 1 Non-Secure base address */ +#define UART2_BASE_NS 0x49305000 /* UART 2 Non-Secure base address */ +#define UART3_BASE_NS 0x49306000 /* UART 3 Non-Secure base address */ +#define UART4_BASE_NS 0x49307000 /* UART 4 Non-Secure base address */ +#define UART5_BASE_NS 0x49308000 /* UART 5 Non-Secure base address */ +#define CLCD_Config_Reg_BASE_NS 0x4930A000 /* CLCD Config Reg Non-Secure base address */ +#define RTC_BASE_NS 0x4930B000 /* RTC Non-Secure base address */ +#define DDR4_BLK0_BASE_NS 0x60000000 /* DDR4 block 0 Non-Secure base address */ +#define DDR4_BLK2_BASE_NS 0x80000000 /* DDR4 block 2 Non-Secure base address */ +#define DDR4_BLK4_BASE_NS 0xA0000000 /* DDR4 block 4 Non-Secure base address */ +#define DDR4_BLK6_BASE_NS 0xC0000000 /* DDR4 block 6 Non-Secure base address */ + +/* Secure memory map addresses */ +#define ITCM_BASE_S 0x10000000 /* Instruction TCM Secure base address */ +#define SRAM_BASE_S 0x11000000 /* CODE SRAM Secure base address */ +#define DTCM0_BASE_S 0x30000000 /* Data TCM block 0 Secure base address */ +#define DTCM1_BASE_S 0x30020000 /* Data TCM block 1 Secure base address */ +#define DTCM2_BASE_S 0x30040000 /* Data TCM block 2 Secure base address */ +#define DTCM3_BASE_S 0x30060000 /* Data TCM block 3 Secure base address */ +#define ISRAM0_BASE_S 0x31000000 /* Internal SRAM Area Secure base address */ +#define ISRAM1_BASE_S 0x31100000 /* Internal SRAM Area Secure base address */ +#define QSPI_SRAM_BASE_S 0x38000000 /* QSPI SRAM Secure base address */ +/* Secure Subsystem peripheral region */ +#define CPU0_SECCTRL_BASE_S 0x50011000 /* CPU 0 Local Security Control Block Secure base address */ +#define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base address */ +#define CPU0_IDENTITY_BASE_S 0x5001F000 /* CPU 0 Identity Block Secure base address */ +#define SSE300_SACFG_BASE_S 0x50080000 /* SSE-300 Secure Access Configuration Register Secure base address */ +#define MPC_ISRAM0_BASE_S 0x50083000 /* Internal SRAM0 Memory Protection Controller Secure base address */ +#define MPC_ISRAM1_BASE_S 0x50084000 /* Internal SRAM1 Memory Protection Controller Secure base address */ +/* Secure MSTEXPPILL Peripheral region */ +#define GPIO0_CMSDK_BASE_S 0x51100000 /* GPIO 0 Secure base address */ +#define GPIO1_CMSDK_BASE_S 0x51101000 /* GPIO 1 Secure base address */ +#define GPIO2_CMSDK_BASE_S 0x51102000 /* GPIO 2 Secure base address */ +#define GPIO3_CMSDK_BASE_S 0x51103000 /* GPIO 3 Secure base address */ +#define FMC_CMSDK_GPIO_0_BASE_S 0x51104000 /* FMC CMSDK GPIO 0 Secure base address */ +#define FMC_CMSDK_GPIO_1_BASE_S 0x51105000 /* FMC CMSDK GPIO 1 Secure base address */ +#define FMC_CMSDK_GPIO_2_BASE_S 0x51106000 /* FMC CMSDK GPIO 2 Secure base address */ +#define FMC_CMSDK_GPIO_3_BASE_S 0x51107000 /* FMC CMSDK GPIO 3 Secure base address */ +#define EXTERNAL_MANAGER0_BASE_S 0x51200000 /* External Manager 0 (Unused) Secure base address */ +#define EXTERNAL_MANAGER1_BASE_S 0x51201000 /* External Manager 1 (Unused) Secure base address */ +#define EXTERNAL_MANAGER2_BASE_S 0x51202000 /* External Manager 2 (Unused) Secure base address */ +#define EXTERNAL_MANAGER3_BASE_S 0x51203000 /* External Manager 3 (Unused) Secure base address */ +#define ETHERNET_BASE_S 0x51400000 /* Ethernet Secure base address */ +#define USB_BASE_S 0x51500000 /* USB Secure base address */ +#define USER_APB0_BASE_S 0x51700000 /* User APB 0 Secure base address */ +#define USER_APB1_BASE_S 0x51701000 /* User APB 1 Secure base address */ +#define USER_APB2_BASE_S 0x51702000 /* User APB 2 Secure base address */ +#define USER_APB3_BASE_S 0x51703000 /* User APB 3 Secure base address */ +#define QSPI_CONFIG_BASE_S 0x51800000 /* QSPI Config Secure base address */ +#define QSPI_WRITE_BASE_S 0x51801000 /* QSPI Write Secure base address */ +#define MPC_SRAM_BASE_S 0x57000000 /* SRAM Memory Protection Controller Secure base address */ +#define MPC_QSPI_BASE_S 0x57001000 /* QSPI Memory Protection Controller Secure base address */ +#define MPC_DDR4_BASE_S 0x57002000 /* DDR4 Memory Protection Controller Secure base address */ +/* Secure Subsystem peripheral region */ +#define SYSTIMER0_ARMV8_M_BASE_S 0x58000000 /* System Timer 0 Secure base address */ +#define SYSTIMER1_ARMV8_M_BASE_S 0x58001000 /* System Timer 1 Secure base address */ +#define SYSTIMER2_ARMV8_M_BASE_S 0x58002000 /* System Timer 0 Secure base address */ +#define SYSTIMER3_ARMV8_M_BASE_S 0x58003000 /* System Timer 1 Secure base address */ +#define SSE300_SYSINFO_BASE_S 0x58020000 /* SSE-300 System info Block Secure base address */ +#define SSE300_SYSCTRL_BASE_S 0x58021000 /* SSE-300 System control Block Secure base address */ +#define SSE300_SYSPPU_BASE_S 0x58022000 /* SSE-300 System Power Policy Unit Secure base address */ +#define SSE300_CPU0PPU_BASE_S 0x58023000 /* SSE-300 CPU 0 Power Policy Unit Secure base address */ +#define SSE300_MGMTPPU_BASE_S 0x58028000 /* SSE-300 Management Power Policy Unit Secure base address */ +#define SSE300_DBGPPU_BASE_S 0x58029000 /* SSE-300 Debug Power Policy Unit Secure base address */ +#define SLOWCLK_WDOG_CMSDK_BASE_S 0x5802E000 /* CMSDK based SLOWCLK Watchdog Secure base address */ +#define SLOWCLK_TIMER_CMSDK_BASE_S 0x5802F000 /* CMSDK based SLOWCLK Timer Secure base address */ +#define SYSWDOG_ARMV8_M_CNTRL_BASE_S 0x58040000 /* Secure Watchdog Timer control frame Secure base address */ +#define SYSWDOG_ARMV8_M_REFRESH_BASE_S 0x58041000 /* Secure Watchdog Timer refresh frame Secure base address */ +#define SYSCNTR_CNTRL_BASE_S 0x58100000 /* System Counter Control Secure base address */ +#define SYSCNTR_READ_BASE_S 0x58101000 /* System Counter Read Secure base address */ +/* Secure MSTEXPPIHL Peripheral region */ +#define ETHOS_U55_APB_BASE_S 0x58102000 /* Ethos-U55 APB Secure base address */ +#define U55_TIMING_ADAPTER_0_BASE_S 0x58103000 /* Ethos-U55 Timing Adapter 0 APB registers Secure base address */ +#define U55_TIMING_ADAPTER_1_BASE_S 0x58103200 /* Ethos-U55 Timing Adapter 1 APB registers Secure base address */ +#define FPGA_SBCon_I2C_TOUCH_BASE_S 0x59200000 /* FPGA - SBCon I2C (Touch) Secure base address */ +#define FPGA_SBCon_I2C_AUDIO_BASE_S 0x59201000 /* FPGA - SBCon I2C (Audio Conf) Secure base address */ +#define FPGA_SPI_ADC_BASE_S 0x59202000 /* FPGA - PL022 (SPI ADC) Secure base address */ +#define FPGA_SPI_SHIELD0_BASE_S 0x59203000 /* FPGA - PL022 (SPI Shield0) Secure base address */ +#define FPGA_SPI_SHIELD1_BASE_S 0x59204000 /* FPGA - PL022 (SPI Shield1) Secure base address */ +#define SBCon_I2C_SHIELD0_BASE_S 0x59205000 /* SBCon (I2C - Shield0) Secure base address */ +#define SBCon_I2C_SHIELD1_BASE_S 0x59206000 /* SBCon (I2C – Shield1) Secure base address */ +#define USER_APB_BASE_S 0x59207000 /* USER APB Secure base address */ +#define FPGA_DDR4_EEPROM_BASE_S 0x59208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Secure base address */ +#define FMC_USER_APB_0_BASE_S 0x5920C000 /* FMC User APB0 registers Secure base address */ +#define FMC_USER_APB_1_BASE_S 0x5920D000 /* FMC User APB1 registers Secure base address */ +#define FMC_USER_APB_2_BASE_S 0x5920E000 /* FMC User APB2 registers Secure base address */ +#define FMC_USER_APB_3_BASE_S 0x5920F000 /* FMC User APB3 registers Secure base address */ +#define FPGA_SCC_BASE_S 0x59300000 /* FPGA - SCC registers Secure base address */ +#define FPGA_I2S_BASE_S 0x59301000 /* FPGA - I2S (Audio) Secure base address */ +#define FPGA_IO_BASE_S 0x59302000 /* FPGA - IO (System Ctrl + I/O) Secure base address */ +#define UART0_BASE_S 0x59303000 /* UART 0 Secure base address */ +#define UART1_BASE_S 0x59304000 /* UART 1 Secure base address */ +#define UART2_BASE_S 0x59305000 /* UART 2 Secure base address */ +#define UART3_BASE_S 0x59306000 /* UART 3 Secure base address */ +#define UART4_BASE_S 0x59307000 /* UART 4 Secure base address */ +#define UART5_BASE_S 0x59308000 /* UART 5 Secure base address */ +#define CLCD_Config_Reg_BASE_S 0x5930A000 /* CLCD Config Reg Secure base address */ +#define RTC_BASE_S 0x5930B000 /* RTC Secure base address */ +#define DDR4_BLK1_BASE_S 0x70000000 /* DDR4 block 1 Secure base address */ +#define DDR4_BLK3_BASE_S 0x90000000 /* DDR4 block 3 Secure base address */ +#define DDR4_BLK5_BASE_S 0xB0000000 /* DDR4 block 5 Secure base address */ +#define DDR4_BLK7_BASE_S 0xD0000000 /* DDR4 block 7 Secure base address */ + +/* Memory map addresses exempt from memory attribution by both the SAU and IDAU */ +#define SSE300_EWIC_BASE 0xE0047000 /* External Wakeup Interrupt Controller + * Access from Non-secure software is only allowed + * if AIRCR.BFHFNMINS is set to 1 */ + +/* Memory size definitions */ +#define ITCM_SIZE (0x00080000) /* 512 kB */ +#define DTCM_BLK_SIZE (0x00020000) /* 128 kB */ +#define DTCM_BLK_NUM (0x4) /* Number of DTCM blocks */ +#define SRAM_SIZE (0x00100000) /* 1 MB */ +#define ISRAM0_SIZE (0x00100000) /* 1 MB */ +#define ISRAM1_SIZE (0x00100000) /* 1 MB */ +#define QSPI_SRAM_SIZE (0x00800000) /* 8 MB */ +#define DDR4_BLK_SIZE (0x10000000) /* 256 MB */ +#define DDR4_BLK_NUM (0x8) /* Number of DDR4 blocks */ + +/* Defines for Driver MPC's */ +/* SRAM -- 2 MB */ +#define MPC_SRAM_RANGE_BASE_NS (SRAM_BASE_NS) +#define MPC_SRAM_RANGE_LIMIT_NS (SRAM_BASE_NS + SRAM_SIZE-1) +#define MPC_SRAM_RANGE_OFFSET_NS (0x0) +#define MPC_SRAM_RANGE_BASE_S (SRAM_BASE_S) +#define MPC_SRAM_RANGE_LIMIT_S (SRAM_BASE_S + SRAM_SIZE-1) +#define MPC_SRAM_RANGE_OFFSET_S (0x0) + +/* QSPI -- 8 MB*/ +#define MPC_QSPI_RANGE_BASE_NS (QSPI_SRAM_BASE_NS) +#define MPC_QSPI_RANGE_LIMIT_NS (QSPI_SRAM_BASE_NS + QSPI_SRAM_SIZE-1) +#define MPC_QSPI_RANGE_OFFSET_NS (0x0) +#define MPC_QSPI_RANGE_BASE_S (QSPI_SRAM_BASE_S) +#define MPC_QSPI_RANGE_LIMIT_S (QSPI_SRAM_BASE_S + QSPI_SRAM_SIZE-1) +#define MPC_QSPI_RANGE_OFFSET_S (0x0) + +/* ISRAM0 -- 2 MB*/ +#define MPC_ISRAM0_RANGE_BASE_NS (ISRAM0_BASE_NS) +#define MPC_ISRAM0_RANGE_LIMIT_NS (ISRAM0_BASE_NS + ISRAM0_SIZE-1) +#define MPC_ISRAM0_RANGE_OFFSET_NS (0x0) +#define MPC_ISRAM0_RANGE_BASE_S (ISRAM0_BASE_S) +#define MPC_ISRAM0_RANGE_LIMIT_S (ISRAM0_BASE_S + ISRAM0_SIZE-1) +#define MPC_ISRAM0_RANGE_OFFSET_S (0x0) + +/* ISRAM1 -- 2 MB*/ +#define MPC_ISRAM1_RANGE_BASE_NS (ISRAM1_BASE_NS) +#define MPC_ISRAM1_RANGE_LIMIT_NS (ISRAM1_BASE_NS + ISRAM1_SIZE-1) +#define MPC_ISRAM1_RANGE_OFFSET_NS (0x0) +#define MPC_ISRAM1_RANGE_BASE_S (ISRAM1_BASE_S) +#define MPC_ISRAM1_RANGE_LIMIT_S (ISRAM1_BASE_S + ISRAM1_SIZE-1) +#define MPC_ISRAM1_RANGE_OFFSET_S (0x0) + +/* DDR4 -- 2GB (8 * 256 MB) */ +#define MPC_DDR4_BLK0_RANGE_BASE_NS (DDR4_BLK0_BASE_NS) +#define MPC_DDR4_BLK0_RANGE_LIMIT_NS (DDR4_BLK0_BASE_NS + ((DDR4_BLK_SIZE)-1)) +#define MPC_DDR4_BLK0_RANGE_OFFSET_NS (0x0) +#define MPC_DDR4_BLK1_RANGE_BASE_S (DDR4_BLK1_BASE_S) +#define MPC_DDR4_BLK1_RANGE_LIMIT_S (DDR4_BLK1_BASE_S + ((DDR4_BLK_SIZE)-1)) +#define MPC_DDR4_BLK1_RANGE_OFFSET_S (DDR4_BLK1_BASE_S - DDR4_BLK0_BASE_NS) +#define MPC_DDR4_BLK2_RANGE_BASE_NS (DDR4_BLK2_BASE_NS) +#define MPC_DDR4_BLK2_RANGE_LIMIT_NS (DDR4_BLK2_BASE_NS + ((DDR4_BLK_SIZE)-1)) +#define MPC_DDR4_BLK2_RANGE_OFFSET_NS (DDR4_BLK2_BASE_NS - DDR4_BLK0_BASE_NS) +#define MPC_DDR4_BLK3_RANGE_BASE_S (DDR4_BLK3_BASE_S) +#define MPC_DDR4_BLK3_RANGE_LIMIT_S (DDR4_BLK3_BASE_S + ((DDR4_BLK_SIZE)-1)) +#define MPC_DDR4_BLK3_RANGE_OFFSET_S (DDR4_BLK3_BASE_S - DDR4_BLK0_BASE_NS) +#define MPC_DDR4_BLK4_RANGE_BASE_NS (DDR4_BLK4_BASE_NS) +#define MPC_DDR4_BLK4_RANGE_LIMIT_NS (DDR4_BLK4_BASE_NS + ((DDR4_BLK_SIZE)-1)) +#define MPC_DDR4_BLK4_RANGE_OFFSET_NS (DDR4_BLK4_BASE_NS - DDR4_BLK0_BASE_NS) +#define MPC_DDR4_BLK5_RANGE_BASE_S (DDR4_BLK5_BASE_S) +#define MPC_DDR4_BLK5_RANGE_LIMIT_S (DDR4_BLK5_BASE_S + ((DDR4_BLK_SIZE)-1)) +#define MPC_DDR4_BLK5_RANGE_OFFSET_S (DDR4_BLK5_BASE_S - DDR4_BLK0_BASE_NS) +#define MPC_DDR4_BLK6_RANGE_BASE_NS (DDR4_BLK6_BASE_NS) +#define MPC_DDR4_BLK6_RANGE_LIMIT_NS (DDR4_BLK6_BASE_NS + ((DDR4_BLK_SIZE)-1)) +#define MPC_DDR4_BLK6_RANGE_OFFSET_NS (DDR4_BLK6_BASE_NS - DDR4_BLK0_BASE_NS) +#define MPC_DDR4_BLK7_RANGE_BASE_S (DDR4_BLK7_BASE_S) +#define MPC_DDR4_BLK7_RANGE_LIMIT_S (DDR4_BLK7_BASE_S + ((DDR4_BLK_SIZE)-1)) +#define MPC_DDR4_BLK7_RANGE_OFFSET_S (DDR4_BLK7_BASE_S - DDR4_BLK0_BASE_NS) + +#endif /* __PLATFORM_BASE_ADDRESS_H__ */ diff --git a/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0 b/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0 new file mode 100644 index 0000000..32ac16b --- /dev/null +++ b/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0 @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2016-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "region_limits.h" + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure regions */ +#define S_CODE_START ( S_ROM_ALIAS ) +#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) +#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) + +#define S_DATA_START ( S_RAM_ALIAS ) +#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) +#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) + +#define S_DDR4_START ( S_DDR4_ALIAS ) +#define S_DDR4_SIZE ( TOTAL_S_DDR4_SIZE ) +#define S_DDR4_LIMIT ( S_DDR4_START + S_DDR4_SIZE ) + +#endif /* __REGION_DEFS_H__ */ diff --git a/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0 b/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0 new file mode 100644 index 0000000..e789786 --- /dev/null +++ b/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0 @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2018-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_LIMITS_H__ +#define __REGION_LIMITS_H__ + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure Code */ +#define S_ROM_ALIAS (0x10000000) /* ITCM_BASE_S */ +#define TOTAL_S_ROM_SIZE (0x00080000) /* 512 kB */ + +/* Secure Data */ +#define S_RAM_ALIAS (0x30000000) /* DTCM_BASE_S */ +#define TOTAL_S_RAM_SIZE (0x00080000) /* 512 kB */ + +/* Secure DDR4 */ +#define S_DDR4_ALIAS (0x70000000) /* DDR4_BLK1_BASE_S */ +#define TOTAL_S_DDR4_SIZE (0x10000000) /* 256 MB */ + +/* Heap and Stack sizes for secure and nonsecure applications */ +#define HEAP_SIZE (0x00000400) /* 1 KiB */ +#define STACK_SIZE (0x00000400) /* 1 KiB */ + +#endif /* __REGION_LIMITS_H__ */ diff --git a/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c.base@1.1.1 b/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c.base@1.1.1 new file mode 100644 index 0000000..d1e59d7 --- /dev/null +++ b/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c.base@1.1.1 @@ -0,0 +1,344 @@ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c + * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void( *pFunc )( void ); + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __WEAK __NO_RETURN handler_name(void); \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TIMER0_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) +DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) +DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_Handler) +DEFAULT_IRQ_HANDLER(CTI_REQ0_IRQHandler) +DEFAULT_IRQ_HANDLER(CTI_REQ1_IRQHandler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Handler) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const pFunc __VECTOR_TABLE[496]; + const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_Handler, /* 0: Non-Secure Watchdog Reset Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TIMER0_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ + SYS_PPU_Handler, /* 15: SYS PPU Handler */ + CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ + TIMER3_Handler, /* 27: TIMER 3 Handler */ + CTI_REQ0_IRQHandler, /* 28: CTI request 0 IRQ Handler */ + CTI_REQ1_IRQHandler, /* 29: CTI request 1 IRQ Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Handler, /* 127: UART 5 combined Interrupt */ + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 b/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 new file mode 100644 index 0000000..1d8c3b6 --- /dev/null +++ b/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.c + * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (32000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __VECTOR_TABLE; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE >= 1U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. Set + * CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU + * into retention state + */ + PWRMODCTL->CPDLPSTATE &= 0xFFFFFF00UL; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + +} diff --git a/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h.base@1.1.1 b/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h.base@1.1.1 new file mode 100644 index 0000000..feba5e9 --- /dev/null +++ b/mlek-kws/Target/CM55_Ethos/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h.base@1.1.1 @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2009-2020 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.h + * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b + */ + +#ifndef __SYSTEM_CORE_INIT_H__ +#define __SYSTEM_CORE_INIT_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency */ + +/** + * \brief Initializes the system + */ +extern void SystemInit(void); + +/** + * \brief Restores system core clock + */ +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_CORE_INIT_H__ */ diff --git a/mlek-kws/Target/CM55_Ethos/Source/BoardInit.cpp b/mlek-kws/Target/CM55_Ethos/Source/BoardInit.cpp index cd137a9..1fc6521 100644 --- a/mlek-kws/Target/CM55_Ethos/Source/BoardInit.cpp +++ b/mlek-kws/Target/CM55_Ethos/Source/BoardInit.cpp @@ -86,7 +86,7 @@ static int arm_ethosu_npu_init(void) arm_ethosu_npu_irq_init(); /* Initialise Ethos-U device */ - const void* ethosu_base_address = (void*)(ETHOS_U55_APB_BASE_S); + void* ethosu_base_address = (void*)(ETHOS_U55_APB_BASE_S); debug("Cache arena: 0x%p\n", get_cache_arena()); diff --git a/mlek-kws/Target/CM55_Ethos/Target.clayer.yml b/mlek-kws/Target/CM55_Ethos/Target.clayer.yml index 8ac52f5..2372815 100644 --- a/mlek-kws/Target/CM55_Ethos/Target.clayer.yml +++ b/mlek-kws/Target/CM55_Ethos/Target.clayer.yml @@ -3,7 +3,7 @@ layer: description: Cortex-M55 with Ethos-U target components and files packs: - - pack: Arm::ethos-u-core-driver@1.22.8 + - pack: ARM::ethos-u-core-driver@1.25.2 components: - component: ARM::Device:Definition @@ -11,7 +11,7 @@ layer: - component: ARM::Native Driver:SysCounter - component: ARM::Native Driver:SysTimer - component: ARM::Native Driver:Timeout - - component: Arm::Machine Learning:NPU Support:Ethos-U Driver&Generic U55 + - component: ARM::Machine Learning:NPU Support:Ethos-U Driver&Generic U55 linker: - script: ./RTE/Device/SSE-300-MPS3/mps3-sse-300.sct diff --git a/mlek-kws/Target/CM85_Ethos/Source/BoardInit.cpp b/mlek-kws/Target/CM85_Ethos/Source/BoardInit.cpp index cd137a9..1fc6521 100644 --- a/mlek-kws/Target/CM85_Ethos/Source/BoardInit.cpp +++ b/mlek-kws/Target/CM85_Ethos/Source/BoardInit.cpp @@ -86,7 +86,7 @@ static int arm_ethosu_npu_init(void) arm_ethosu_npu_irq_init(); /* Initialise Ethos-U device */ - const void* ethosu_base_address = (void*)(ETHOS_U55_APB_BASE_S); + void* ethosu_base_address = (void*)(ETHOS_U55_APB_BASE_S); debug("Cache arena: 0x%p\n", get_cache_arena()); diff --git a/mlek-kws/Target/CM85_Ethos/Target.clayer.yml b/mlek-kws/Target/CM85_Ethos/Target.clayer.yml index 54bc2b7..83c12ab 100644 --- a/mlek-kws/Target/CM85_Ethos/Target.clayer.yml +++ b/mlek-kws/Target/CM85_Ethos/Target.clayer.yml @@ -3,7 +3,7 @@ layer: description: Cortex-M85 with Ethos-U target components and files packs: - - pack: Arm::ethos-u-core-driver@1.22.8 + - pack: ARM::ethos-u-core-driver@1.25.2 components: - component: ARM::Device:Definition @@ -11,7 +11,7 @@ layer: - component: ARM::Native Driver:SysCounter - component: ARM::Native Driver:SysTimer - component: ARM::Native Driver:Timeout - - component: Arm::Machine Learning:NPU Support:Ethos-U Driver&Generic U65 + - component: ARM::Machine Learning:NPU Support:Ethos-U Driver&Generic U65 linker: - script: ./RTE/Device/SSE-310-MPS3_FVP/mps3-sse-310.sct diff --git a/mlek-kws/Test/ML_Test.cproject.yml b/mlek-kws/Test/ML_Test.cproject.yml index 5c175a9..a987ebd 100644 --- a/mlek-kws/Test/ML_Test.cproject.yml +++ b/mlek-kws/Test/ML_Test.cproject.yml @@ -6,6 +6,7 @@ project: - pack: ARM::CMSIS@>=6.0.0-dev0 - pack: ARM::CMSIS-DSP@1.15.0 - pack: ARM::CMSIS-View@1.0.0 + - pack: ARM::CMSIS-NN@4.0.0 - pack: ARM::ml-embedded-eval-kit-uc-api@22.8.0-Beta - pack: tensorflow::flatbuffers@1.22.8 - pack: tensorflow::tensorflow-lite-micro@1.22.8 diff --git a/mlek-kws/Test/RTE/CMSIS-View/EventRecorderConf.h.base@1.1.0 b/mlek-kws/Test/RTE/CMSIS-View/EventRecorderConf.h.base@1.1.0 new file mode 100644 index 0000000..9802f2a --- /dev/null +++ b/mlek-kws/Test/RTE/CMSIS-View/EventRecorderConf.h.base@1.1.0 @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2016-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: EventRecorderConf.h + * Purpose: Event Recorder software component configuration options + * Rev.: V1.1.0 + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Event Recorder + +// Number of Records +// <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 +// <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 +// <65536=>65536 +// Configures size of Event Record Buffer (each record is 16 bytes) +// Must be 2^n (min=8, max=65536) +#define EVENT_RECORD_COUNT 64U + +// Time Stamp Source +// <0=> DWT Cycle Counter <1=> SysTick <2=> CMSIS-RTOS2 System Timer +// <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) +// Selects source for 32-bit time stamp +#define EVENT_TIMESTAMP_SOURCE 0 + +// Time Stamp Clock Frequency [Hz] <0-1000000000> +// Defines initial time stamp clock frequency (0 when not used) +#define EVENT_TIMESTAMP_FREQ 0U + +// + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/vcpkg-configuration.json b/vcpkg-configuration.json index 63f3b22..7f8e157 100644 --- a/vcpkg-configuration.json +++ b/vcpkg-configuration.json @@ -9,8 +9,8 @@ "requires": { "arm:compilers/arm/armclang": "6.20.0", "arm:compilers/arm/arm-none-eabi-gcc": "^12.3.1-0", - "arm:compilers/arm/llvm-embedded": "^16.0.0-0", - "arm:tools/open-cmsis-pack/cmsis-toolbox": "^2.1.0-0", - "arm:models/arm/avh-fvp": "^11.22.39" + "arm:compilers/arm/llvm-embedded": "^19.1.5", + "arm:tools/open-cmsis-pack/cmsis-toolbox": "^2.11.0", + "arm:models/arm/avh-fvp": "^11.29.27" } } \ No newline at end of file