From 34a611ad14228357bda9910b26aac9776feb525d Mon Sep 17 00:00:00 2001 From: Mahesh Kurapati Date: Fri, 15 May 2026 15:01:54 -0500 Subject: [PATCH] arch:arm64:boot:dts: enable MCTP for SP8 platforms Enable MCTP over I3C for SP8 platforms tested: verified on Eagle. Signed-off-by: Mahesh Kurapati --- .../boot/dts/aspeed/aspeed-bmc-amd-eagle.dts | 10 ++++++++-- .../boot/dts/aspeed/aspeed-bmc-amd-falcon.dts | 6 ++++++ .../aspeed/aspeed-bmc-amd-hornbill-mps.dts | 20 +++++++++++++++++++ .../dts/aspeed/aspeed-bmc-amd-hornbill.dts | 20 +++++++++++++++++++ .../dts/aspeed/aspeed-bmc-amd-seagull.dts | 20 +++++++++++++++++++ 5 files changed, 74 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-eagle.dts b/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-eagle.dts index eba33113599cdb..3da2bce36875b1 100644 --- a/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-eagle.dts +++ b/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-eagle.dts @@ -544,8 +544,8 @@ reg = <0x71>; #address-cells = <1>; #size-cells = <0>; - ginger_z_pcie_conn1_i2c: i2c@2 { - reg = <2>; + ginger_z_pcie_conn1_i2c: i2c@0 { + reg = <0>; #address-cells = <1>; #size-cells = <0>; i2cswitch@76 { @@ -882,6 +882,12 @@ reg = <0x0 0x224 0x0000111A>; assigned-address = <0x3c>; }; + + scoob_p0_sp8: scoob@0,2240000211A { + reg = <0x0 0x224 0x0000211A>; + mrl = <69>; + mwl = <69>; + }; }; #define JESD300_SPD_I3C_MODE(bus, index, addr) \ diff --git a/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-falcon.dts b/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-falcon.dts index 97b1b2a961a6e8..38ae442566cd92 100644 --- a/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-falcon.dts +++ b/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-falcon.dts @@ -441,6 +441,12 @@ reg = <0x0 0x224 0x0000111A>; assigned-address = <0x3c>; }; + + scoob_p0_sp8: scoob@0,2240000211A { + reg = <0x0 0x224 0x0000211A>; + mrl = <69>; + mwl = <69>; + }; }; #define JESD300_SPD_I3C_MODE(bus, index, addr) \ diff --git a/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-hornbill-mps.dts b/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-hornbill-mps.dts index 92a85bf514ae4b..71fd0b9eebba81 100644 --- a/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-hornbill-mps.dts +++ b/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-hornbill-mps.dts @@ -834,6 +834,12 @@ assigned-address = <0x3c>; dimm-ids = <0x80 0x90 0x81 0x91 0x82 0x92 0x83 0x93 0x84 0x94 0x85 0x95 0x86 0x96 0x87 0x97>; }; + + scoob_p0_sp8: scoob@0,2240000211A { + reg = <0x0 0x224 0x0000211A>; + mrl = <69>; + mwl = <69>; + }; }; &i3c5 { @@ -849,6 +855,20 @@ assigned-address = <0x38>; dimm-ids = <0x80 0x90 0x81 0x91 0x82 0x92 0x83 0x93 0x84 0x94 0x85 0x95 0x86 0x96 0x87 0x97>; }; + + /* SCOOB SP8 2P */ + scoob_2p_p1_sp8: scoob@0,2240100211A { + reg = <0x0 0x224 0x0100211A>; + mrl = <69>; + mwl = <69>; + }; + + /* SCOOB SP8 2x1P */ + scoob_2x1p_p1_sp8: scoob@0,2240000211A { + reg = <0x0 0x224 0x0000211A>; + mrl = <69>; + mwl = <69>; + }; }; #define JESD300_SPD_I3C_MODE(bus, index, addr) \ diff --git a/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-hornbill.dts b/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-hornbill.dts index 33f8d0879abe2d..5a6b62e87d2d6a 100644 --- a/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-hornbill.dts +++ b/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-hornbill.dts @@ -839,6 +839,12 @@ assigned-address = <0x3c>; dimm-ids = <0x80 0x90 0x81 0x91 0x82 0x92 0x83 0x93 0x84 0x94 0x85 0x95 0x86 0x96 0x87 0x97>; }; + + scoob_p0_sp8: scoob@0,2240000211A { + reg = <0x0 0x224 0x0000211A>; + mrl = <69>; + mwl = <69>; + }; }; &i3c5 { @@ -861,6 +867,13 @@ dimm-ids = <0x80 0x90 0x81 0x91 0x82 0x92 0x83 0x93 0x84 0x94 0x85 0x95 0x86 0x96 0x87 0x97>; }; + /* SCOOB SP8 2P */ + scoob_2p_p1_sp8: scoob@0,2240100211A { + reg = <0x0 0x224 0x0100211A>; + mrl = <69>; + mwl = <69>; + }; + /* TSI SP8 2x1P */ sbtsi_2x1p_p1_sp8: sbtsi@0,2240000011A { reg = <0x0 0x224 0x0000011A>; @@ -873,6 +886,13 @@ assigned-address = <0x38>; dimm-ids = <0x80 0x90 0x81 0x91 0x82 0x92 0x83 0x93 0x84 0x94 0x85 0x95 0x86 0x96 0x87 0x97>; }; + + /* SCOOB SP8 2x1P */ + scoob_2x1p_p1_sp8: scoob@0,2240000211A { + reg = <0x0 0x224 0x0000211A>; + mrl = <69>; + mwl = <69>; + }; }; #define JESD300_SPD_I3C_MODE(bus, index, addr) \ diff --git a/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-seagull.dts b/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-seagull.dts index a5e0bb0301d5f0..17d7d877776d96 100644 --- a/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-seagull.dts +++ b/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-seagull.dts @@ -564,6 +564,12 @@ reg = <0x0 0x224 0x0000111A>; assigned-address = <0x3c>; }; + + scoob_p0_sp8: scoob@0,2240000211A { + reg = <0x0 0x224 0x0000211A>; + mrl = <69>; + mwl = <69>; + }; }; &i3c5 { @@ -586,6 +592,13 @@ assigned-address = <0x38>; }; + /* SCOOB SP8 2P */ + scoob_2p_p1_sp8: scoob@0,2240100211A { + reg = <0x0 0x224 0x0100211A>; + mrl = <69>; + mwl = <69>; + }; + /* TSI SP8 2x1P */ sbtsi_2x1p_p1_sp8: sbtsi@0,2240000011A { reg = <0x0 0x224 0x0000011A>; @@ -597,6 +610,13 @@ reg = <0x0 0x224 0x0000111A>; assigned-address = <0x38>; }; + + /* SCOOB SP8 2x1P */ + scoob_2x1p_p1_sp8: scoob@0,2240000211A { + reg = <0x0 0x224 0x0000211A>; + mrl = <69>; + mwl = <69>; + }; }; #define JESD300_SPD_I3C_MODE(bus, index, addr) \