From e9ce439dab53b852bb150cee97d6082a936d14d7 Mon Sep 17 00:00:00 2001 From: HenryHe0123 <13600668331@163.com> Date: Tue, 31 Oct 2023 11:14:27 +0800 Subject: [PATCH 1/5] W7D1 by henryhe --- Computer Architecture Note W7D1.md | 55 ++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Computer Architecture Note W7D1.md diff --git a/Computer Architecture Note W7D1.md b/Computer Architecture Note W7D1.md new file mode 100644 index 0000000..98a08ad --- /dev/null +++ b/Computer Architecture Note W7D1.md @@ -0,0 +1,55 @@ +# Computer Architecture Note W7D1 + +## Reduce the Miss Rate + +### How can we reduce misses? + +1. change Block Size + +2. change Associativity + +3. **change Compiler** + +### Reducing misses by compiler optimizations + +1. merging arrays + + e.g. 把key和value放在结构体里再一起开数组，而不是开两个数组 + +2. loop interchange + + e.g. 改变遍历二维数组的循环顺序 + +3. blocking + + e.g. 分块计算矩阵乘法 + +## Reduce the Miss Penalty + +### L2 Cache + +Q: Why not increase L1 Cache directly? + +A: Larger capacity would lead to lower hit speed. + +### Write Policy + +- Write-through + + update cache and underlying memory/cache + +- Write-back + + simply update cache, another *dirty* control bit + +### Read Priority over Write on Miss + +Using **Write Buffer** for both write-through and write-back. + +Special case: *Read miss replacing dirty block (write-back)* + +- Copy the dirty block to a write buffer, then do the read and write parallel + +### Early Restart and Critical Word First + +Generally useful only in large blocks. \ No newline at end of file From 2646561ac07b33df7e4486848d6a203243653771 Mon Sep 17 00:00:00 2001 From: HenryHe0123 <13600668331@163.com> Date: Fri, 24 Nov 2023 22:58:57 +0800 Subject: [PATCH 2/5] W11D1 by henryhe --- Computer Architecture Note W11D1.md | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 Computer Architecture Note W11D1.md diff --git a/Computer Architecture Note W11D1.md b/Computer Architecture Note W11D1.md new file mode 100644 index 0000000..1af6033 --- /dev/null +++ b/Computer Architecture Note W11D1.md @@ -0,0 +1,14 @@ +# Computer Architecture Note W11D1 + +Q: Why we need memory reorder buffer? + +A: For Process SYNC & IPC (Inter-Process Communication). (e.g. we may have memory barrier) + +Q: Is it always better to have more stages in the CPU pipeline? + +A: No. (e.g. the story of Pentium 4) + +*Some interesting stories and comments about Kuan Yang...* + +- Hyper-threading Technology (HTT) (e.g. one core, two registers) +- Simultaneous Multi-threading (SMT) From 8a3692128e9d4989aa338c479e87408165cc3396 Mon Sep 17 00:00:00 2001 From: HenryHe0123 <13600668331@163.com> Date: Fri, 22 Dec 2023 23:38:02 +0800 Subject: [PATCH 3/5] W15D1 by henryhe --- Computer Architecture Note W15D1.md | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Computer Architecture Note W15D1.md diff --git a/Computer Architecture Note W15D1.md b/Computer Architecture Note W15D1.md new file mode 100644 index 0000000..86bf5d6 --- /dev/null +++ b/Computer Architecture Note W15D1.md @@ -0,0 +1,24 @@ +# Computer Architecture Note W15D1 + +(Recitation by A.Lei) + +## Virtual Cache VS Physical Cache + +1. Core + Cache (P) + VM + + synonym & alias problem: page table per process + +2. Core + VM + Cache (V) + + performance problem: TLB (translation lookaside buffer) + +**Distinguish Synonym from Alias** + +Synonym: one va to different pa + +Alias: different va to same pa + +## VLIW (Very Long Instruction Word) + +a technology of parallelism + From e9e45f3a32acae36c4bc9c130e58e102317b5e3a Mon Sep 17 00:00:00 2001 From: HenryHe0123 <13600668331@163.com> Date: Fri, 22 Dec 2023 23:42:33 +0800 Subject: [PATCH 4/5] fix typo in W15D1 --- Computer Architecture Note W15D1.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Computer Architecture Note W15D1.md b/Computer Architecture Note W15D1.md index 86bf5d6..f6bc25b 100644 --- a/Computer Architecture Note W15D1.md +++ b/Computer Architecture Note W15D1.md @@ -4,11 +4,11 @@ ## Virtual Cache VS Physical Cache -1. Core + Cache (P) + VM +1. Core + Cache (V) + VM synonym & alias problem: page table per process -2. Core + VM + Cache (V) +2. Core + VM + Cache (P) performance problem: TLB (translation lookaside buffer) From 26f9f74a31a166e9ade09054d33028a8034c3e22 Mon Sep 17 00:00:00 2001 From: HenryHe0123 <13600668331@163.com> Date: Thu, 18 Jan 2024 09:33:44 +0800 Subject: [PATCH 5/5] fix typo --- Computer Architecture Note W11D1.md | 2 +- Computer Architecture Note W15D1.md | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Computer Architecture Note W11D1.md b/Computer Architecture Note W11D1.md index 1af6033..6378f1e 100644 --- a/Computer Architecture Note W11D1.md +++ b/Computer Architecture Note W11D1.md @@ -1,6 +1,6 @@ # Computer Architecture Note W11D1 -Q: Why we need memory reorder buffer? +Q: Why do we need memory reorder buffer? A: For Process SYNC & IPC (Inter-Process Communication). (e.g. we may have memory barrier) diff --git a/Computer Architecture Note W15D1.md b/Computer Architecture Note W15D1.md index f6bc25b..216a4aa 100644 --- a/Computer Architecture Note W15D1.md +++ b/Computer Architecture Note W15D1.md @@ -1,6 +1,6 @@ # Computer Architecture Note W15D1 -(Recitation by A.Lei) +(Recitation by Alei) ## Virtual Cache VS Physical Cache